JPH01313996A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH01313996A JPH01313996A JP14507288A JP14507288A JPH01313996A JP H01313996 A JPH01313996 A JP H01313996A JP 14507288 A JP14507288 A JP 14507288A JP 14507288 A JP14507288 A JP 14507288A JP H01313996 A JPH01313996 A JP H01313996A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- layer
- plating layer
- land
- nickel plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 60
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 33
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000126 substance Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims description 53
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 47
- 239000000758 substrate Substances 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は印刷配線板の製造方法に係り、特にパートリア
ディティブ法による印刷配線板の製造方法の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a printed wiring board, and more particularly to an improvement in a method for manufacturing a printed wiring board by a part-rediative method.
(従来の技術)
両面型印刷配線板を比較的容易に製造する手段として次
のようなパートリアディティブ法が知られている。すな
わち、両面銅張り板を先ず用意し、この銅張り板の所定
位置に打抜き加工或いはドリルによる穴明は加工を施し
てスルホール孔を適宜形成した後そのスルホール孔につ
いてメッキ前処理する。次いで前記銅張り板の銅面上に
所望する回路パターン状にエツチングレジストでマスキ
ングし、選択エツチングによって露出している銅を除去
してから前記エツチングレジストを取り除いて所定の回
路パターンを得る。しかる後、前記形成した回路パター
ンのランドおよびスルホール孔内壁面以外の面にはメッ
キレジスト層を被覆形成し、化学銅メッキを選択的に施
すことによってスルホール孔内壁面に導電層を被着形成
して両面型印刷配線板を製造している。(Prior Art) The following part-reactive method is known as a means for relatively easily manufacturing a double-sided printed wiring board. That is, a double-sided copper-clad plate is first prepared, and through-holes are formed by punching or drilling at predetermined positions on the copper-clad plate, and then the through-holes are subjected to a pre-plating treatment. Next, a desired circuit pattern is masked on the copper surface of the copper clad plate with an etching resist, and the exposed copper is removed by selective etching, and then the etching resist is removed to obtain a predetermined circuit pattern. After that, a plating resist layer is coated on surfaces other than the land and the inner wall surface of the through-hole hole of the formed circuit pattern, and a conductive layer is formed on the inner wall surface of the through-hole hole by selectively applying chemical copper plating. The company manufactures double-sided printed wiring boards.
(発明が解決しようとする課題)
しかしながら上記パートリアディティブ法によって製造
した両面型印刷配線板においては次のような不都合が往
々認められる。すなわち前記方法で製造された両面型印
刷配線板の所謂るスルホール導電層が必ずしも常に一様
に形成されずスルホール導通の信頼性が十分と言い難い
。つまりスルホール導通層を形成するために用いる化学
銅メッキ液は経時に伴い劣化したり或いは組成変化を招
来するため形成したメッキ層にバラツキを生じ易く、こ
のためスルホール導電の信頼性低下が起生じていると解
される。(Problems to be Solved by the Invention) However, the following disadvantages are often observed in double-sided printed wiring boards manufactured by the above-mentioned part-additive method. That is, the so-called through-hole conductive layer of the double-sided printed wiring board manufactured by the above method is not always formed uniformly, and the reliability of through-hole conduction cannot be said to be sufficient. In other words, the chemical copper plating solution used to form the through-hole conductive layer deteriorates over time or changes its composition, which tends to cause variations in the formed plating layer, which reduces the reliability of through-hole conduction. It is understood that there is.
[発明の構成]
(課題を解決するための手段)
本発明は前記パートリアディティブ法において、銅とニ
ッケルとの選択エツチング性を利用しランドおよびスル
ホール孔内壁面に電気銅メッキ層を形成させることを骨
子とする。つまりスルホール孔内壁面およびランドを含
め全面に先ず化学ニッケルメッキ層を形成し、次いで前
記スルホール孔内壁面およびランドに電気銅メッキを選
択的に施してからさらにニッケルメッキ層で被覆した状
態にした後、回路パターン上の化学ニッケルメッキ層、
スルホール孔内壁面およびランドを被覆するニッケルメ
ッキ層を選択的にエツチング除去して高精度、高密度の
スルホール導電層を備えたものとする。[Structure of the Invention] (Means for Solving the Problems) The present invention involves forming an electrolytic copper plating layer on the inner wall surfaces of lands and through-holes by utilizing the selective etching properties of copper and nickel in the above-mentioned part additive method. The main point is In other words, a chemical nickel plating layer is first formed on the entire surface including the inner wall surface of the through-hole hole and the land, then electrolytic copper plating is selectively applied to the inner wall surface of the through-hole hole and the land, and then the layer is further covered with a nickel plating layer. , chemical nickel plating layer on the circuit pattern,
The nickel plating layer covering the inner wall surface of the through-hole and the land is selectively etched away to provide a through-hole conductive layer with high precision and high density.
(作用)
本発明によればスルホール孔内壁面およびランドを含め
全体的に化学ニッケルメッキ層を下地的に形成してあり
、この下地層を用いスルホール孔内壁面およびランドに
電気メッキ性で緻密な銅層を被覆形成する。このため被
覆形成される銅層は前記緻密性(高密度)に伴い常に略
−様な性状を維持する。しかも前記形成した電気銅メッ
キ層をニッケルメッキ層にて被覆した形で、回路パター
ンを被覆している前記化学ニッケルメッキ層とともにエ
ツチング除去される。つまり回路パターン上などを被覆
し且つ露出している化学ニッケルメッキ層のエツチング
除去においてスルホール孔内壁面上およびランド上の電
気銅メッキ層領域ではそれらを被覆しているニッケルメ
ッキ層が先ず選択的にエツチングされるため前記電気銅
メッキ層の損傷は起らない。(Function) According to the present invention, a chemical nickel plating layer is formed as a base on the entire surface including the inner wall surface of the through hole and the land, and this base layer is used to coat the inner wall surface of the through hole and the land with electroplating. Coat with a copper layer. Therefore, the copper layer formed as a coating always maintains substantially -like properties due to the denseness (high density). Furthermore, the formed electrolytic copper plating layer is covered with a nickel plating layer, which is removed by etching together with the chemical nickel plating layer covering the circuit pattern. In other words, in the etching removal of the exposed chemical nickel plating layer covering the circuit pattern, etc., the nickel plating layer covering the through-hole inner wall surface and land is first selectively removed. Since it is etched, the electrolytic copper plating layer is not damaged.
(実施例) 以下添附の図面を参照して本発明の詳細な説明する。(Example) The present invention will now be described in detail with reference to the accompanying drawings.
図は本発明方法の各工程における印刷配線板の状態を示
す断面図であり、先ず絶縁性基板1の両面に銅箔2を貼
り合せて成る両面銅張り板3を用意した(第1図)。次
いでこの銅張り板3の所定位置に例えばドリルによる穴
明は加工を施して所要のスルホール孔4を穿設する(第
2図)一方、エツチングレジスト5でマスキングしく第
3図)、選択エツチングを施して所要の回路パターン(
ランド6を含む)を形成した。しかる後マスキングレジ
スト6を除去しく第4図)、スルホール孔内壁面を含む
全面に化学ニッケルメッキを施してニッケルメッキ層7
を形成した(第5図)。かくして全面に亙って化学ニッ
ケルメッキ層7を形成せしめた絶縁性基板1のスルホー
ル孔4内壁面およびランド6を除いた他の面上にメッキ
レジスト層8を塗布形成しく第6図)、この状態で電気
銅メッキ処理を施した。つまり前記絶縁性基板1に対し
て電気銅メッキを行ない露出しているスルホール孔4内
壁面およびランド6面上に選択的に電気銅メッキ層9を
被覆形成した。次いで前記メッキレジスト層8を着けた
まま電気メッキまたは化学ニッケルメッキを施して前記
形成した電気銅メッキ層9上にニッケルメッキ層7を被
覆形成してから(第7図)、前記メッキレジスト層8を
除去した(第8図)。かくして第8図の如く絶縁性基板
1の最外層をニッケルメッキ層7.7′で全面的に被覆
した状態のものを得、これについてニッケルメッキ層7
.7′のエツチング除去処理を施した。すなわち絶縁性
基板1の表面層をなしているニッケルメッキ層7.7′
を二・ソケル用工、ツチンダ液にて選択的にエツチング
除去して前記スルホール孔4内壁面およびランド6に化
学ニッケルメッキ層7と電気銅メッキ層9との復層形導
電層の形成された印刷配線板が得られた(第9図)。The figures are cross-sectional views showing the state of the printed wiring board in each step of the method of the present invention. First, a double-sided copper-clad board 3 was prepared by laminating copper foil 2 on both sides of an insulating substrate 1 (Fig. 1). . Next, the copper clad plate 3 is drilled, for example, at a predetermined position to form the required through hole 4 (Fig. 2), while masking with an etching resist 5 (Fig. 3), and selective etching is performed. and create the required circuit pattern (
(including land 6) was formed. After that, the masking resist 6 is removed (Fig. 4), and chemical nickel plating is applied to the entire surface including the inner wall surface of the through hole to form a nickel plating layer 7.
was formed (Fig. 5). In this way, a plating resist layer 8 is coated on the inner wall surface of the through-hole hole 4 of the insulating substrate 1 on which the chemical nickel plating layer 7 has been formed over the entire surface, and on other surfaces excluding the land 6 (FIG. 6). Electrolytic copper plating treatment was performed in this state. That is, electrolytic copper plating was performed on the insulating substrate 1, and an electrolytic copper plating layer 9 was selectively formed on the exposed inner wall surfaces of the through holes 4 and the surfaces of the lands 6. Next, electroplating or chemical nickel plating is performed with the plating resist layer 8 still attached to form a nickel plating layer 7 on the electrolytic copper plating layer 9 formed above (FIG. 7), and then the plating resist layer 8 is coated with the nickel plating layer 7. was removed (Figure 8). In this way, the outermost layer of the insulating substrate 1 is completely covered with the nickel plating layer 7,7' as shown in FIG.
.. 7' etching removal treatment was performed. That is, the nickel plating layer 7.7' forming the surface layer of the insulating substrate 1
2. After selectively etching and removing with Tsuchinda solution, a double-layered conductive layer consisting of a chemical nickel plating layer 7 and an electrolytic copper plating layer 9 was formed on the inner wall surface of the through-hole hole 4 and the land 6. A wiring board was obtained (Figure 9).
[発明の効果]
上記実施例から分るように本発明方法によれば絶縁性基
板の主面に形成される主回路パターンは肉厚が比較的−
様な(厚さにバラツキがない)銅箔で構成されているた
め、高精度に形成される。[Effects of the Invention] As can be seen from the above embodiments, according to the method of the present invention, the main circuit pattern formed on the main surface of the insulating substrate has a relatively -
Because it is made of copper foil with a uniform thickness, it can be formed with high precision.
またスルホール孔内壁面の導電層はランドを含め電気銅
メッキによって形成されるため緻密で被着量のバラツキ
もなく(厚さが一様)、信頼性の高い導電層として常に
作用する。つまりスルホール孔内壁面に被覆形成した電
気銅メッキ層上に予めニッケルメッキ層を被覆形成した
状態で、基板上の主回路パターン面など他の面に被覆形
成されている化学ニッケルメッキ層の選択エツチングを
行なうため前記銅箔パターンおよび電気銅メッキ層は損
傷されることも防止され所要の肉厚など容易に維持する
。しかも上記電気銅メッキ層の形成はスルホール孔内壁
面およびランド面のみであるためコスト面でも有利であ
り、前記印刷配線板としての高信性と相まって実用上条
(の利点をもたらす製造方法と言える。Furthermore, since the conductive layer on the inner wall surface of the through-hole, including the land, is formed by electrolytic copper plating, it is dense and has no variation in the amount of coating (uniform thickness), and always functions as a highly reliable conductive layer. In other words, a nickel plating layer is pre-coated on the electrolytic copper plating layer formed on the inner wall surface of the through hole, and selective etching of the chemical nickel plating layer formed on other surfaces such as the main circuit pattern surface on the board is performed. Because of this, the copper foil pattern and the electrolytic copper plating layer are prevented from being damaged and the required thickness can be easily maintained. Moreover, since the electrolytic copper plating layer is formed only on the inner wall surface of the through-hole and the land surface, it is advantageous in terms of cost, and in combination with the high reliability of the printed wiring board, it can be said that this manufacturing method provides practical advantages. .
第1図ないし第9図は本発明に係る印刷配線板の製造方
法を説明するためのもので、各工程における印刷配線板
の態様を示す断面図である。
1・・・・・・・・・絶縁性基板
2・・・・・・・・・銅箔
3・・・・・・・・・両面銅張り板
4・・・・・・・・・スルホール孔
5・・・・・・・・・エツチングレジスト6・・・・・
・・・・ランド
7・・・・・・・・・化学ニッケルメッキ層8・・・・
・・・・・メッキレジスト層9・・・・・・・・・電気
銅メッキ層FIGS. 1 to 9 are cross-sectional views for explaining the method of manufacturing a printed wiring board according to the present invention, and showing aspects of the printed wiring board in each step. 1...Insulating board 2...Copper foil 3...Double-sided copper clad plate 4...Through hole Hole 5...Etching resist 6...
... Land 7 ... Chemical nickel plating layer 8 ...
・・・・・・Plating resist layer 9・・・・・・・・・Electrolytic copper plating layer
Claims (1)
と、前記スルホール孔を設けた両面銅張り板の銅面上に
エッチングレジストでマスキングし選択エッチングを施
して所要の回路パターンを形成する工程と、前記マスキ
ングレジストを除去し、スルホール孔内壁面を含む全面
に化学ニッケルメッキを施してニッケルメッキ層を形成
する工程と、前記スルホール孔内壁面およびランド以外
の面をメッキレジスト層で被覆する工程と、前記メッキ
レジスト層被覆後、露出しているスルホール内壁面およ
びランド面に選択的に電気銅メッキ層を被覆形成する工
程と、前記電気銅メッキ層上にニッケルメッキ層を被覆
形成する工程と、前記メッキレジスト層を除去し露出し
ているニッケルメッキ層をエッチング除去する工程とを
具備して成ることを特徴とする印刷配線板の製造方法。a step of providing through-hole holes at predetermined positions on a double-sided copper-clad plate; a step of masking the copper surface of the double-sided copper-clad plate with the through-hole holes with an etching resist and performing selective etching to form a desired circuit pattern; a step of removing the masking resist and applying chemical nickel plating to the entire surface including the inner wall surface of the through-hole hole to form a nickel plating layer; a step of covering the surface other than the inner wall surface of the through-hole hole and the land with a plating resist layer; After coating the plating resist layer, selectively forming an electrolytic copper plating layer on the exposed inner wall surfaces and land surfaces of the through holes; forming a nickel plating layer on the electrolytic copper plating layer; A method for manufacturing a printed wiring board, comprising the steps of removing a plating resist layer and etching away an exposed nickel plating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14507288A JPH01313996A (en) | 1988-06-13 | 1988-06-13 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14507288A JPH01313996A (en) | 1988-06-13 | 1988-06-13 | Manufacture of printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01313996A true JPH01313996A (en) | 1989-12-19 |
Family
ID=15376731
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14507288A Pending JPH01313996A (en) | 1988-06-13 | 1988-06-13 | Manufacture of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01313996A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103675584A (en) * | 2013-09-10 | 2014-03-26 | 镇江华印电路板有限公司 | A circuit board black pore conductivity test method |
-
1988
- 1988-06-13 JP JP14507288A patent/JPH01313996A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103675584A (en) * | 2013-09-10 | 2014-03-26 | 镇江华印电路板有限公司 | A circuit board black pore conductivity test method |
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