JPH03228396A - Manufacture of multilayer printed circuit board - Google Patents

Manufacture of multilayer printed circuit board

Info

Publication number
JPH03228396A
JPH03228396A JP2492490A JP2492490A JPH03228396A JP H03228396 A JPH03228396 A JP H03228396A JP 2492490 A JP2492490 A JP 2492490A JP 2492490 A JP2492490 A JP 2492490A JP H03228396 A JPH03228396 A JP H03228396A
Authority
JP
Japan
Prior art keywords
layer
multilayer printed
hole
plated
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2492490A
Other languages
Japanese (ja)
Inventor
Koichiro Shibayama
耕一郎 柴山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2492490A priority Critical patent/JPH03228396A/en
Publication of JPH03228396A publication Critical patent/JPH03228396A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily obtain a multilayer printed circuit board sufficiently and effectively having a predetermined through hole conducting function by bringing a cathode electrode into opposite contact with an inner layer circuit pattern electrically connected to the conduction hole of the board to be electrically plated. CONSTITUTION:Inner layer circuit board materials having predetermined outer and inner layer circuit patterns 8a, 8b are laminated through a prepreg layer disposed therebetween, and drilled to obtain a multilayer printed circuit board 1 having a predetermined blind hole 2. Thereafter, the board 1 is coated at a predetermined area with a plated resist layer, chemically copper-plated, and covered on the wall in the hole 2 with a chemical copper-plated layer 3. Then, a cathode electrode is brought into opposite contact with the region 8b' in which the pattern 8b in contact with the layer 3 is exposed, electrically copper- plated, and covered with a plated layer 5 having a conducting function.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、多層プリント配線板の製造方法に係り、特に
スルホール接続やブラインドホール接続などの導通穴を
有する多層プリント配線板の製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a multilayer printed wiring board, and particularly to a multilayer printed wiring board having conductive holes such as through-hole connections and blind-hole connections. Relating to a manufacturing method.

(従来の技術) 電子機器類の小型化や高機能化などに対応して、回路構
成の高密度化ないし回路部分の小型化を目的として、多
層プリント配線板が実用に供されている。すなわち、絶
縁体層を介して内層回路パターンを多段的に配設一体化
するとともに、外表面回路パターンを一体的に設けて複
雑な回路を構成して成る多層プリント配線板か、広く各
種の電子機器に使用されている。
(Prior Art) In response to the miniaturization and higher functionality of electronic devices, multilayer printed wiring boards have been put into practical use for the purpose of increasing the density of circuit configurations or miniaturizing circuit parts. In other words, there are multilayer printed wiring boards in which inner layer circuit patterns are arranged and integrated in multiple stages via insulating layers, and outer surface circuit patterns are integrated to form a complex circuit, and a wide variety of electronic devices are used. used in equipment.

ところで、この種の多層プリント配線板においては、外
層回路パターン同士を、ある内層回路パターン同士を、
もしくはある内層回路パターンと外層回路パターンとを
電気的に接続する場合が往々ある。しかして、前記回路
パターン間の電気的な接続は次のように行われている。
By the way, in this kind of multilayer printed wiring board, outer layer circuit patterns are connected to each other, certain inner layer circuit patterns are connected to each other,
Alternatively, there are often cases where a certain inner layer circuit pattern and an outer layer circuit pattern are electrically connected. Electrical connections between the circuit patterns are made as follows.

すなわち、所要の内層回路板および外層回路板を、プリ
プレグ層を介して重ね合せ、加圧成形して多層プリント
配線板を得た後、所定の領域に下リル加工やレザ加工に
より、所要のスルホールやブラインドホルを穿設し、こ
れらスルホールなどの内壁面に、化学めっきおよび電気
めっきを順次施し回路バタン層間の導体接続を行なって
いる。
That is, after the required inner layer circuit board and outer layer circuit board are stacked together with a prepreg layer in between and pressure-molded to obtain a multilayer printed wiring board, the required through holes are formed in predetermined areas by bottom drilling or laser processing. Through-holes and blind holes are drilled, and chemical plating and electroplating are sequentially applied to the inner walls of these through-holes to connect conductors between the circuit batten layers.

(発明が解決しようとする課題) しかし、上記導通穴としてスルホール接続やブラインド
ホール接続を有する多層プリント配線板の製造方法には
次のような不都合かある。すなわち、多層成形した後、
たとえばトリル加工で所要のスルホールなどを穿設し、
この穿設したスルホール内壁面に、化学銅めっきおよび
電気銅めっきを順次施して所要の接続層を形成した場合
、充分な電気的な接続を保持し得ない場合かしばしばあ
る。
(Problems to be Solved by the Invention) However, the method for manufacturing a multilayer printed wiring board having through-hole connections or blind-hole connections as the conductive holes has the following disadvantages. That is, after multilayer molding,
For example, by drilling the required through holes using trill processing,
When a required connection layer is formed by successively applying chemical copper plating and electrolytic copper plating to the inner wall surface of the drilled through hole, it is often impossible to maintain a sufficient electrical connection.

つまり、化学銅めっきでスルホール内壁面なとに被着形
成される銅層(膜)の厚さは通常数μ程度と薄いため、
外層回路パターン(外層銅箔層)を介して印加されるカ
ソード電位かスルホール内で電圧降下し、その結果スル
ホール内中程では所要の電流密度か得られない。したか
って、たとえば第2図に断面的に示すように、電気めっ
き不盾もしくは電気めっき膜厚不定か生じて、所要の1
−i気的な導通機能を十分に果さないという問題かある
。なお、第2図は多層プリント配線板のブラインドホー
ルの場合を示したもので、1は多層プリント配線板本体
、2はブラインドホール、3は化学銅めっき層、4は内
層回路パターン層、5は電気銅めっき層をそれぞれ示す
In other words, the thickness of the copper layer (film) deposited on the inner wall surface of the through hole during chemical copper plating is usually as thin as a few microns.
The cathode potential applied via the outer layer circuit pattern (outer layer copper foil layer) causes a voltage drop within the through hole, and as a result, the required current density cannot be obtained in the middle of the through hole. Therefore, as shown in the cross section in FIG.
-There is a problem that the electrical conduction function is not sufficiently performed. In addition, Fig. 2 shows the case of a blind hole in a multilayer printed wiring board, where 1 is the multilayer printed wiring board main body, 2 is the blind hole, 3 is the chemical copper plating layer, 4 is the inner circuit pattern layer, and 5 is the Each electrolytic copper plating layer is shown.

本発明は、上記事情に対処して、所要のスルホル導通機
能を充分かつ、確実に備えた多層プリント配線板を容易
に得ることのできる製造方法の提(共を目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, the present invention aims to provide a manufacturing method that can easily obtain a multilayer printed wiring board that is sufficiently and reliably provided with the required sulfol conduction function.

[発明の構成] (課題を解決するための手段) 本発明は、多層プリント配線板の導通穴内壁面に電気め
っき処理により導電層を被着形成する工程を含む多層プ
リント配線板の製造方法において、前記電気めっき処理
を多層プリン]・配線板の導通穴と電気的に接続する内
層回路パターンにカソード電極を対接させて行うことを
特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method for manufacturing a multilayer printed wiring board, which includes a step of depositing a conductive layer on the inner wall surface of a conductive hole of the multilayer printed wiring board by electroplating. The electroplating process is performed by placing a cathode electrode in contact with an inner layer circuit pattern that is electrically connected to a conductive hole of a multilayer printed wiring board.

(作 用) 上記本発明方法によれば、スルホールやブラインドホー
ルなとの導通穴内壁面に形成された化学めっき層は内層
回路パターンを介して、所要の電気めっき電位か付与さ
れる。つまり、導通穴内壁面の化学めっき層の中程にカ
ソード電極か接続された形となり、電位降下か回避ない
し防止されるため、電気めっき層の不着部など生しるこ
となく常に−様な電気めっき被着層か形成されることに
なる。
(Function) According to the method of the present invention, the chemical plating layer formed on the inner wall surface of the conductive hole such as a through hole or a blind hole is provided with a required electroplating potential via the inner layer circuit pattern. In other words, the cathode electrode is connected to the middle of the chemical plating layer on the inner wall surface of the conductive hole, and potential drop is avoided or prevented, so that electroplating is always possible without any non-adhesion of the electroplating layer. An adhesion layer will be formed.

(実施例) 以下、本発明の実施態様を模式的に示す第1図(a)〜
(d)を参照して、実施例を説明する。
(Example) The following is a diagram schematically showing embodiments of the present invention.
An example will be described with reference to (d).

先ず、第1図(a)に断面的に示すような、厚さ1.2
1の絶縁層6aの少くとも一方の面に厚さ18μmの銅
箔7を張合せて成る回路板用素材6を用意した。次いで
、上記回路板用素材6の銅箔7層について、それぞれフ
ォトエツチング処理を施して所要の外層回路パターンや
内層回路パターンを備えた回路素板を得た。
First, as shown in cross section in Figure 1(a), the thickness is 1.2 mm.
A circuit board material 6 was prepared by laminating a copper foil 7 with a thickness of 18 μm on at least one surface of an insulating layer 6a. Next, each of the seven copper foil layers of the circuit board material 6 was photoetched to obtain a circuit board having the required outer layer circuit pattern and inner layer circuit pattern.

上記構成した所要の外層回路パターン8aを備えた内層
回路素板または所要の内層回路パターン8bを備えた内
層回路素板とを、その間にプリプレグ層を介在させて積
層し、加圧成形を施して多層プリント配線板を得た。な
お、上記積層・加圧成形において、形成するブラインド
ホール2に連接する内層回路パターン8bの外形加工側
の一部を、カソード電極を対接し得る程度に露出さてお
く。この内層回路パターン8bの一部露出は、前記積層
・加圧成形に当っての座ぐり加工(層順序や位置合せの
マーク検出)の穿設孔を利用してもよい。
The inner layer circuit board having the required outer layer circuit pattern 8a or the inner layer circuit board having the required inner layer circuit pattern 8b configured as described above is laminated with a prepreg layer interposed therebetween, and pressure molding is performed. A multilayer printed wiring board was obtained. In the above-described lamination and pressure molding, a part of the externally processed side of the inner layer circuit pattern 8b that is connected to the blind hole 2 to be formed is exposed to the extent that the cathode electrode can be brought into contact with the inner layer circuit pattern 8b. This partial exposure of the inner layer circuit pattern 8b may be achieved by using holes formed in the counterbore process (detection of marks for layer order and alignment) during the lamination and pressure molding.

次いて、前記形成した多層プリント配線板の所要領域に
、先端角165〜170’ 、直径0,41の超硬ドリ
ル8を用い、穿設加工を施して所要のブラインドホール
2を設け、第1図(b)に断面的に示すようなブライン
ドホールを有する多層プリント配線板1を得た。
Next, using a carbide drill 8 with a tip angle of 165 to 170' and a diameter of 0.41, a required blind hole 2 is formed in a required area of the multilayer printed wiring board formed as described above. A multilayer printed wiring board 1 having blind holes as shown in cross section in Figure (b) was obtained.

しかる後、上記で得たブラインドホール2を有する多層
プリント配線板の所要領域面にめっきレジスト層を被着
し、化学銅めっき処理を施して前記ブラインドホール2
内壁面に化学銅めっき層3を被着形成した。次いで、前
記化学銅めっき処理で被着形成したブラインドホール2
内壁面の化学銅めっき層3に連接する内層回路パターン
8bの露出させた領域8b’ に、カソード電極を対接
させて、所要の電気銅めっき処理を施す。この電気めっ
き処理においては、内層回路パターン8bを介して所要
のめっき電圧か前記化学銅めっき層3に印加されるため
、Cuイオンは電気的に容易にブラインドホール2内に
誘導され、所要の電気銅めっきが進行して−様なかつ、
充分な導通機能を有するめっき層5か被告形成される(
第1図C)。
After that, a plating resist layer is applied to the desired area of the multilayer printed wiring board having the blind holes 2 obtained above, and a chemical copper plating process is performed to form the blind holes 2.
A chemical copper plating layer 3 was deposited on the inner wall surface. Next, the blind hole 2 formed by the chemical copper plating process is
The exposed region 8b' of the inner layer circuit pattern 8b, which is connected to the chemical copper plating layer 3 on the inner wall surface, is brought into contact with the cathode electrode and subjected to the required electrolytic copper plating treatment. In this electroplating process, since a required plating voltage is applied to the chemical copper plating layer 3 via the inner layer circuit pattern 8b, Cu ions are easily electrically induced into the blind hole 2 and the required electrical As copper plating progresses,
A plating layer 5 having a sufficient conductive function is formed (
Figure 1C).

なお、上記ではブラインドホールを有する多層プリント
配線板の製造方法の例を説明したが、いわゆるスルホー
ル接続を有する多層プリント配線板の製造方法にも適用
でき、たとえば板厚1 、6mmで径0 、2tmのス
ルホール内壁面に化学銅めっきおよび電気銅めっきによ
り接続層を形成しても同様に、−様かつ、充分な導通機
能を有するめっき層か被着形成された。また、上記では
化学めっき法として化学銅めっき法を、電気めっき法と
して電気銅めっき法をそれぞれ用いたかこれらに限定さ
れないことは勿論である。
Although the example of the method for manufacturing a multilayer printed wiring board having blind holes has been described above, it can also be applied to a method for manufacturing a multilayer printed wiring board having a so-called through-hole connection. Even when a connection layer was formed on the inner wall surface of the through hole by chemical copper plating and electrolytic copper plating, a plating layer having a -like and sufficient conductive function was similarly deposited. Further, in the above description, a chemical copper plating method was used as the chemical plating method, and an electrolytic copper plating method was used as the electroplating method, but it goes without saying that the method is not limited to these.

[発明の効果コ 本発明によれば、小径スルホールないし高アスペクト比
スルホールあるいはインターステシャルハイアホールを
有しかつ、これらの内壁面に導通層(接続層)を形成す
る多層プリント配線板を歩留りよく、また容易に製造し
得る。しかも、前記めっき法で形成されるスルホール接
続層などは、−様てすぐれた導通機能を保持し、プリン
ト配線板自体の信頼性向上に寄与する。
[Effects of the Invention] According to the present invention, a multilayer printed wiring board having small-diameter through holes, high aspect ratio through holes, or interstitial higher holes and forming a conductive layer (connection layer) on the inner wall surface of these can be produced with high yield. , and can be easily manufactured. Furthermore, the through-hole connection layer formed by the plating method maintains an excellent conductive function and contributes to improving the reliability of the printed wiring board itself.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は本発明に係る製造方法の実施態
様を模式的に示したもので、第1図(a)は回路板用素
材の要部断面図、第1図(b)はブラインドホールを穿
設した多層プリント配線板の要部断面図、第1図(C)
はブラインドホール内壁面に所要の導通層を形成した多
層プリント配線板の要部断面図、第2図は従来のブライ
ンドホール内壁面に所要の導通層を形成した多層プリン
ト配線板の要部断面図である。 1・・・・・多層プリント配線板 2・・・・・・・ブラインドホ 3・・・・・・・化学めっき層 5・・・・・・・・・電気めっき層 6・・・・・・・回路用素材 7・・・・・・・銅箔 8a・・・・・・・・外層回路パタ 8b・・・・・・・・内層回路バタ gb’ ・・内層回路バタ (導通穴) ンの露出領域 出1頭人
1(a) to 1(c) schematically show an embodiment of the manufacturing method according to the present invention, and FIG. 1(a) is a sectional view of the main part of the circuit board material, b) is a cross-sectional view of the main part of a multilayer printed wiring board with blind holes, Figure 1 (C)
2 is a cross-sectional view of a main part of a multilayer printed wiring board in which a required conductive layer is formed on the inner wall surface of a blind hole, and FIG. It is. 1...Multilayer printed wiring board 2...Blind hole 3...Chemical plating layer 5...Electroplating layer 6... ...Circuit material 7...Copper foil 8a...Outer layer circuit pattern 8b...Inner layer circuit pattern gb'...Inner layer circuit pattern (continuity hole) 1 person with exposed area

Claims (1)

【特許請求の範囲】  多層プリント配線板の導通穴内壁面に化学めっき処理
および電気めっき処理により導電層を被着形成する工程
を含む多層プリント配線板の製造方法において、 前記電気めっき処理を、多層プリント配線板の導通穴と
電気的に接続する内層回路パターンにカソード電極を対
接させて行うことを特徴とする多層プリント配線板の製
造方法。
[Scope of Claim] A method for manufacturing a multilayer printed wiring board, which includes a step of depositing a conductive layer on the inner wall surface of a conductive hole of a multilayer printed wiring board by chemical plating treatment and electroplating treatment, wherein the electroplating treatment is performed by multilayer printing. A method for manufacturing a multilayer printed wiring board, characterized in that the manufacturing method is carried out by bringing a cathode electrode into contact with an inner layer circuit pattern that is electrically connected to a conductive hole of the wiring board.
JP2492490A 1990-02-01 1990-02-01 Manufacture of multilayer printed circuit board Pending JPH03228396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2492490A JPH03228396A (en) 1990-02-01 1990-02-01 Manufacture of multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2492490A JPH03228396A (en) 1990-02-01 1990-02-01 Manufacture of multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPH03228396A true JPH03228396A (en) 1991-10-09

Family

ID=12151680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2492490A Pending JPH03228396A (en) 1990-02-01 1990-02-01 Manufacture of multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPH03228396A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016106428A1 (en) * 2014-12-23 2016-06-30 Sanmina Corporation Hole plug for thin laminate
US10237983B2 (en) 2014-12-23 2019-03-19 Sanmina Corporation Method for forming hole plug

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016106428A1 (en) * 2014-12-23 2016-06-30 Sanmina Corporation Hole plug for thin laminate
KR20170098239A (en) * 2014-12-23 2017-08-29 산미나 코포레이션 Hole plug for thin laminate
CN107211539A (en) * 2014-12-23 2017-09-26 桑米纳公司 The stopple of thin laminate
US10237983B2 (en) 2014-12-23 2019-03-19 Sanmina Corporation Method for forming hole plug
US11246226B2 (en) 2014-12-23 2022-02-08 Sanmina Corporation Laminate structures with hole plugs and methods of forming laminate structures with hole plugs

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