JPH04239796A - Fabrication of printed wiring board - Google Patents

Fabrication of printed wiring board

Info

Publication number
JPH04239796A
JPH04239796A JP637291A JP637291A JPH04239796A JP H04239796 A JPH04239796 A JP H04239796A JP 637291 A JP637291 A JP 637291A JP 637291 A JP637291 A JP 637291A JP H04239796 A JPH04239796 A JP H04239796A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
layer
solder
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP637291A
Other languages
Japanese (ja)
Inventor
Kenji Goto
謙二 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP637291A priority Critical patent/JPH04239796A/en
Publication of JPH04239796A publication Critical patent/JPH04239796A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To provide a fabrication method capable of ensuring a high reliability printed wiring board suitable for packaging of electronic parts with high yield. CONSTITUTION:A feature is such that prior to forming a solder layer on a wiring board surface having a conductor circuit area including a surface packaging pad electroless plating is previously applied on a solder layer formation area surface. Hereby, the area surface on which the solder layer is selectively formed is pretreated by the electroless plating. Accordingly, a plating layer having fine uneven surface as a base is formed with separation of uniform fine particles so that deposition of a uniform thickness solder layer is easily and securely achieved and a high reliability printed wiring board is fabricated with high yield.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【発明の目的】[Purpose of the invention]

【0002】0002

【産業上の利用分野】本発明はプリント配線板の製造方
法に係り、特に表面実装用パッドを具備するプリント配
線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed wiring board, and more particularly to a method of manufacturing a printed wiring board provided with surface mounting pads.

【0003】0003

【従来の技術】電子機器類の軽小化ないしコンパクト化
を目的として、回路機構の小形化なども図られている。 すなわち、表面実装用パッドを具備するプリント配線板
面に、所要の電子部品を実装して成る実装回路装置(実
装回路ユニット)が、各種の電子機器類で広く実用に供
されつつあり、またこのために、高密度プリント配線板
の開発も進められている。
2. Description of the Related Art In order to make electronic equipment lighter and more compact, attempts have been made to make circuit mechanisms smaller. In other words, mounted circuit devices (mounted circuit units), in which required electronic components are mounted on a printed wiring board surface equipped with surface mounting pads, are being widely put into practical use in various electronic devices. Therefore, the development of high-density printed wiring boards is also progressing.

【0004】前記表面実装用のプリント配線板としては
、(a) 表面実装用パッドがCu(下地層)およびめ
っきされた半田(上層)の2層構造を成す半田めっきプ
リント配線板、(b) 導体回路の中、ソルダーレジス
トで被覆される領域がCu1の1層で形成され、ソルダ
ーレジスト3で被覆されない領域がCu(下地層)およ
びホットエアーレベリングされた半田(上層)の2層構
造に形成された半田レベラープリント配線板などが知ら
れている。
The printed wiring board for surface mounting is (a) a solder-plated printed wiring board in which the surface mounting pad has a two-layer structure of Cu (base layer) and plated solder (upper layer); (b) In the conductor circuit, the area covered with solder resist is formed with a single layer of Cu1, and the area not covered with solder resist 3 is formed with a two-layer structure of Cu (base layer) and hot air leveled solder (upper layer). Solder leveler printed wiring boards, etc., are known.

【0005】しかして、前記構造の表面実装用のプリン
ト配線板は、一般に次のようにして製造されている。た
とえばCu箔を選択的にエッチングして所要の実装用パ
ッドを含む導体回路を形成した後、要すればエッチング
レジストを剥離・除去してからソルダーレジスト層を印
刷により被着形成する。つまり、所要の半田層を形成す
る領域以外の部分を選択的にマスキングする。その後、
露出している実装用パッドを含む導体回路面の酸化膜を
、たとえばソフトエッチング処理もしくは硫酸処理(前
処理)によって除去し、表面を清浄化ないし活性化した
後、溶融半田浴に浸漬して、前記露出面に選択的に半田
層を被着形成することにより所要のプリント配線板を得
ている。
[0005] The surface-mount printed wiring board having the above structure is generally manufactured in the following manner. For example, after selectively etching Cu foil to form a conductor circuit including required mounting pads, if necessary, the etching resist is peeled off and removed, and then a solder resist layer is deposited by printing. That is, parts other than the area where the required solder layer is to be formed are selectively masked. after that,
The oxide film on the conductor circuit surface, including the exposed mounting pads, is removed by soft etching or sulfuric acid treatment (pretreatment), the surface is cleaned or activated, and then immersed in a molten solder bath. A desired printed wiring board is obtained by selectively depositing a solder layer on the exposed surface.

【0006】[0006]

【発明が解決しようとする課題】しかし、前記表面実装
用プリント配線板の製造方法には、実用上次のような問
題がある。すなわち、前記半田層の被着形成(コーティ
ング)に先だって、ソフトエッチング処理もしくは硫酸
処理(前処理)により、露出している実装用パッドを含
む導体回路面の酸化膜を除去する手段を採用した場合、
コーティングされる半田層の膜厚が不均一性を帯び易い
。したがって、前記露出している実装用パッドを含む導
体回路が、高密度配線化などに伴って狭ピッチ化した場
合など、隣接する導体回路間でブリッジが生じることが
しばしば起こる。つまり、信頼性の高い表面実装用プリ
ント配線板を歩留まりよく製造することは、困難なのが
実状である。
[Problems to be Solved by the Invention] However, the method for manufacturing the surface-mount printed wiring board has the following practical problems. That is, when a method is adopted in which the oxide film on the conductor circuit surface including the exposed mounting pad is removed by soft etching treatment or sulfuric acid treatment (pretreatment) prior to the adhesion formation (coating) of the solder layer. ,
The thickness of the solder layer to be coated tends to be non-uniform. Therefore, when conductor circuits including the exposed mounting pads have a narrower pitch due to higher wiring density, etc., bridges often occur between adjacent conductor circuits. In other words, the reality is that it is difficult to manufacture highly reliable printed wiring boards for surface mounting with a high yield.

【0007】本発明は上記事情に対処してなされたもの
で、所要の電子部品の実装に適する信頼性の高いプリン
ト配線板を歩留まりよく得ることが可能な製造方法の提
供を目的とする。
The present invention has been made in response to the above-mentioned circumstances, and an object of the present invention is to provide a manufacturing method capable of obtaining a highly reliable printed wiring board suitable for mounting required electronic components at a high yield.

【0008】[0008]

【発明の構成】[Structure of the invention]

【0009】[0009]

【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、表面実装用パッドを含む導体回路領
域を有する配線基板面に被半田層形成領域を除き選択的
にソルダーレジストで被覆する工程と、前記露出してい
る被半田層形成領域面に無電解めっき処理を施してめっ
き層を形成する工程と、前記形成しためっき層面上に半
田層を選択的に被着形成する工程とを具備して成ること
を特徴とする。
[Means for Solving the Problems] A method for manufacturing a printed wiring board according to the present invention is to selectively cover a wiring board surface having a conductor circuit area including surface mounting pads with a solder resist except for the area where a solder layer is to be formed. a step of performing electroless plating on the exposed surface of the solder layer formation region to form a plating layer; and a step of selectively depositing and forming a solder layer on the surface of the formed plating layer. It is characterized by comprising the following.

【0010】0010

【作用】本発明に係るプリント配線板の製造方法におい
ては、半田層を選択的に形成する領域面が、無電解めっ
きにより前処理される。しかして、この前処理によって
、均一な微粒子の析出で下地を成す微細な凹凸面のめっ
き層が形成されるため、容易かつ確実に厚さの均一な半
田層の被着形成が可能となり、信頼性の高いプリント配
線板を歩留まりよく製造し得る。
[Operation] In the method for manufacturing a printed wiring board according to the present invention, the area surface on which the solder layer is to be selectively formed is pretreated by electroless plating. Through this pretreatment, a finely uneven underlying plating layer is formed through the precipitation of uniform particles, making it possible to easily and reliably form a solder layer with a uniform thickness, making it reliable. Printed wiring boards with high properties can be manufactured with high yield.

【0011】[0011]

【実施例】以下図1〜図8を参照して本発明の実施例を
説明する。
Embodiments An embodiment of the present invention will be described below with reference to FIGS. 1 to 8.

【0012】図1〜図8は本発明に係るプリント配線板
の製造方法の実施態様例を模式的に示した断面図で、次
のように行われる。先ず図1に断面的に示すごとく、C
u箔1張り基板2を用意し、この基板2に表面実装用パ
ッド領域形成用の穴3を開ける。次いで、前記穴開け加
工した基板2について、無電解Cuめっき液を用いてめ
っき処理し、穴3内壁面およびCu箔1面上にたとえば
厚さ0.3 μm 程度の化学Cuめっき層4を被着形
成した後(図2)、さらにたとえば電気Cuめっき処理
を施して、たとえば厚さ25μm 程度の電気Cuめっ
き層5を被着形成する(図3)。
FIGS. 1 to 8 are cross-sectional views schematically showing embodiments of the method for manufacturing a printed wiring board according to the present invention, which is carried out as follows. First, as shown cross-sectionally in Figure 1, C
A substrate 2 covered with U foil is prepared, and a hole 3 for forming a surface mounting pad area is bored in this substrate 2. Next, the board 2 with the holes drilled is plated using an electroless Cu plating solution, and a chemical Cu plating layer 4 having a thickness of, for example, about 0.3 μm is coated on the inner wall surface of the hole 3 and the surface of the Cu foil 1. After the deposition (FIG. 2), for example, an electrolytic Cu plating process is performed to form an electrolytic Cu plating layer 5 having a thickness of, for example, about 25 μm (FIG. 3).

【0013】上記めっき層4,5を被着形成した後、両
主面にドライフィルム6をラミネートし、露光・現像処
理を順次施すことによって、所要の表面実装用パッドを
含む導体回路に対応する画像形成(エッチング用マスキ
ング)を行う(図4)。かくした状態で、所要のエッチ
ング処理を施して表面実装用パッド7aを含む導体回路
7を形成した後、前記ドライフィルム6を剥離・除去す
る(図5)。
After the plating layers 4 and 5 have been deposited, a dry film 6 is laminated on both main surfaces, and exposure and development are sequentially performed to form a conductive circuit including the required surface mounting pads. Image formation (masking for etching) is performed (FIG. 4). In this state, a necessary etching process is performed to form a conductive circuit 7 including a surface mounting pad 7a, and then the dry film 6 is peeled off and removed (FIG. 5).

【0014】次いで、前記基板2の表面実装用パッド7
aを含む導体回路7を形成面に、たとえぱ印刷法によっ
て半田層形成領域を除いてソルダーレジスト層8を被着
形成する(図6)。しかる後、たとえば硫酸処理によっ
て露出している実装用パッド7aを含む導体回路7面の
酸化膜を除去し、たとえば無電解Snめっき浴を用い、
前記露出している実装用パッド7aを含む導体回路7面
に、Snめっき層9を選択的に被着形成する(図7)。 その後さらに、半田溶融浴に浸漬してSnめっき層9面
上に所要の半田層10を選択的に被着形成(ソルダーコ
ート)する(図8)。前記無電解めっき処理によって形
成されためっき層9面には、比較的微細な凹凸がほぼ均
一に存在しているため、ソルダーコート処理において半
田ののりも良好で被着し易いので、ほぼ均一でかつ膜厚
の大きい半田層10が形成されていた。
Next, the surface mounting pad 7 of the substrate 2
A solder resist layer 8 is formed on the surface on which the conductor circuit 7 including the conductive circuit 7 (a) is formed, for example by a printing method, except for the solder layer forming area (FIG. 6). Thereafter, the oxide film on the surface of the conductor circuit 7 including the exposed mounting pad 7a is removed, for example, by sulfuric acid treatment, and then, for example, using an electroless Sn plating bath,
A Sn plating layer 9 is selectively deposited on the surface of the conductor circuit 7 including the exposed mounting pad 7a (FIG. 7). Thereafter, a desired solder layer 10 is selectively formed (solder coated) on the surface of the Sn plating layer 9 by immersion in a solder melting bath (FIG. 8). On the surface of the plating layer 9 formed by the electroless plating process, relatively fine irregularities exist almost uniformly, so that the solder adheres well and is easy to adhere in the solder coating process, so that the plated layer 9 is almost uniformly formed. In addition, a solder layer 10 having a large thickness was formed.

【0015】なお、上記においては表面実装用パッド7
aを含む導体回路7を、いわゆるティンティング法で形
成したが、Cu箔のみで形成してもよく、またCu箔の
みで形成した場合は、Snめっき層9および半田層10
の選択的な被着形成(ソルダーコート)に先立って、下
処理として化学Cuめっき層4など被着形成しておくこ
とが好ましい。さらに、前記ではSnめっき層9の被着
形成に先立って、硫酸処理により酸化膜を除去したが、
硫酸−過酸化水素系あるいは過硫酸ソーダなどによって
処理してもよい。また、前記無電解Snめっきの代わり
に、たとえば無電解はんだめっきもしくは無電解Cuめ
っきを行ってもよい。かくして、本発明は前記実施例に
限定されるものでなく、その要旨の範囲内でいろいろの
態様で実施し得る。
Note that in the above, the surface mounting pad 7
Although the conductor circuit 7 including a is formed by the so-called tinting method, it may be formed only with Cu foil, and if it is formed only with Cu foil, the Sn plating layer 9 and the solder layer 10
Prior to the selective adhesion formation (solder coating), it is preferable to form a chemical Cu plating layer 4 as a pretreatment. Furthermore, in the above, the oxide film was removed by sulfuric acid treatment prior to the formation of the Sn plating layer 9.
Treatment may be performed using a sulfuric acid-hydrogen peroxide system or sodium persulfate. Further, instead of the electroless Sn plating, for example, electroless solder plating or electroless Cu plating may be performed. Thus, the present invention is not limited to the above embodiments, but can be implemented in various ways within the scope of the invention.

【0016】[0016]

【発明の効果】上記したように、本発明に係るプリント
配線板の製造方法においては、比較的微細な凹凸が均一
に形成されているめっき層を下地として半田層が被着形
成される。つまり、半田層は十分な膜厚で、かつ膜厚に
バラツキのない均一な状態に被着形成されるため、狭ピ
ッチで隣接する導体回路間でブリッジを発生する恐れも
容易に回避される。換言すると配線密度を低下させるこ
となく、所要のソルダーコートがなされた信頼性の高い
高密度実装用プリント配線板を容易に、かつ歩留まりよ
く製造し得ることになる。
As described above, in the method of manufacturing a printed wiring board according to the present invention, a solder layer is deposited on a plating layer on which relatively fine irregularities are uniformly formed. In other words, since the solder layer has a sufficient thickness and is uniformly deposited without any variation in thickness, the possibility of bridging between adjacent conductor circuits at a narrow pitch can be easily avoided. In other words, it is possible to easily produce a highly reliable printed wiring board for high-density mounting with the required solder coating without reducing the wiring density and with a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明のプリント配線板の製造方法におい
てCu箔張り基板にパッド領域形成用の穴をあけた状態
を示す断面図。
FIG. 1 is a cross-sectional view showing a state in which a hole for forming a pad region is formed in a Cu foil-covered substrate in the printed wiring board manufacturing method of the present invention.

【図2】  本発明のプリント配線板の製造方法におい
てCu箔張り基板面化学Cuめっき層を被着形成した状
態を示す断面図。
FIG. 2 is a cross-sectional view showing a state in which a chemical Cu plating layer is deposited on the surface of a Cu foil-clad substrate in the printed wiring board manufacturing method of the present invention.

【図3】  本発明のプリント配線板の製造方法におい
てCu箔張り基板面化学Cu鍍金層上に電気めっき層を
被着形成した状態を示す断面図。
FIG. 3 is a cross-sectional view showing a state in which an electroplating layer is deposited on a chemical Cu plating layer on the surface of a Cu foil-clad substrate in the printed wiring board manufacturing method of the present invention.

【図4】  本発明のプリント配線板の製造方法におい
て電気めっき層面上にエッチングレジスト層を形成した
状態を示す断面図。
FIG. 4 is a cross-sectional view showing a state in which an etching resist layer is formed on an electroplated layer surface in the printed wiring board manufacturing method of the present invention.

【図5】  本発明のプリント配線板の製造方法におい
て選択的にエッチング処理して実装用パッドを含む導体
回路を形成した状態を示す断面図。
FIG. 5 is a cross-sectional view showing a conductive circuit including mounting pads formed by selective etching in the printed wiring board manufacturing method of the present invention.

【図6】  本発明のプリント配線板の製造方法におい
て実装用パッドを含む導体回路を形成した面にソルダー
レジスト層を被着形成した状態を示す断面図。
FIG. 6 is a cross-sectional view showing a state in which a solder resist layer is adhered to a surface on which a conductor circuit including mounting pads is formed in the printed wiring board manufacturing method of the present invention.

【図7】  本発明のプリント配線板の製造方法におい
てソルダーレジスト層を被着形成後、露出した面に化学
Snめっき層を被着形成した状態を示す断面図。
FIG. 7 is a cross-sectional view showing a state in which a chemical Sn plating layer is deposited on the exposed surface after a solder resist layer is deposited in the printed wiring board manufacturing method of the present invention.

【図8】  本発明のプリント配線板の製造方法におい
て化学Snめっき層形成面にソルダーコートした状態を
示す断面図。
FIG. 8 is a cross-sectional view showing a state in which the surface on which the chemical Sn plating layer is formed is solder-coated in the printed wiring board manufacturing method of the present invention.

【符号の説明】[Explanation of symbols]

1…Cu箔    2…基板    3…穴(スルホー
ル)    4…無電解Cuめっき層 5…電気めっき層    6…ドライフィルム    
7…導体回路    7a…表面実装用パッド    
8…ソルダーレジスト層    9…無電解Snめっき
層    10…ソルダーコート(半田層)
1... Cu foil 2... Substrate 3... Hole (through hole) 4... Electroless Cu plating layer 5... Electroplating layer 6... Dry film
7...Conductor circuit 7a...Surface mounting pad
8...Solder resist layer 9...Electroless Sn plating layer 10...Solder coat (solder layer)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  表面実装用パッドを含む導体回路領域
を有する配線基板面に被半田層形成領域を除き選択的に
ソルダーレジストで被覆する工程と、前記露出している
被半田層形成領域面に無電解めっき処理を施してめっき
層を形成する工程と、前記形成しためっき層面上に半田
層を選択的に被着形成する工程とを具備して成ることを
特徴とするプリント配線板の製造方法。
1. A step of selectively covering a wiring board surface having a conductive circuit region including a surface mounting pad with a solder resist except for a solder layer formation region; A method for manufacturing a printed wiring board, comprising the steps of forming a plating layer by electroless plating, and selectively depositing a solder layer on the surface of the formed plating layer. .
JP637291A 1991-01-23 1991-01-23 Fabrication of printed wiring board Withdrawn JPH04239796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP637291A JPH04239796A (en) 1991-01-23 1991-01-23 Fabrication of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP637291A JPH04239796A (en) 1991-01-23 1991-01-23 Fabrication of printed wiring board

Publications (1)

Publication Number Publication Date
JPH04239796A true JPH04239796A (en) 1992-08-27

Family

ID=11636543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP637291A Withdrawn JPH04239796A (en) 1991-01-23 1991-01-23 Fabrication of printed wiring board

Country Status (1)

Country Link
JP (1) JPH04239796A (en)

Similar Documents

Publication Publication Date Title
US4278511A (en) Plug plating
EP0127955B1 (en) Manufacture of printed circuit boards
JP4129665B2 (en) Manufacturing method of substrate for semiconductor package
JPH05335713A (en) Printed substrate lamination board with fine through-hole with one side closed and conduction plating method of the board
JPH05327224A (en) Manufacture of multilayer wiring board and multi-layer wiring board manufactured by the manufacture
EP0277148A1 (en) Method for manufacture of printed circuit boards
JPH05259639A (en) Manufacture of printed wiring board
KR20020026849A (en) Wiring circuit board having bumps and method of producing same
JPH04239796A (en) Fabrication of printed wiring board
JPH036880A (en) Printed wiring board and manufacture thereof
JP2713037B2 (en) Printed wiring board and manufacturing method thereof
JP2665293B2 (en) Printed circuit board
JP3130707B2 (en) Printed circuit board and method of manufacturing the same
JPH04355994A (en) Manufacture of printed wiring board
JPH01295489A (en) Manufacture of printed wiring board and wiring board obtained by this manufacturing method
GB2026918A (en) Component-carrying printed circuit board
JPH03225894A (en) Manufacture of printed wiring board
JPH08186357A (en) Printed wiring board and manufacture thereof
JPH05335723A (en) Manufacture of printed circuit board
JPH09181422A (en) Printed circuit board manufacturing method
JPS5924560B2 (en) Printed wiring board manufacturing method
JPH05251848A (en) Manufacture of printed wiring board
JPS5846698A (en) Method of producing printed circuit board
JPH07183644A (en) Manufacture of printed wiring board
JPH0548249A (en) Surface treating method for printed circuit board

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980514