JPS55123147A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55123147A
JPS55123147A JP3023279A JP3023279A JPS55123147A JP S55123147 A JPS55123147 A JP S55123147A JP 3023279 A JP3023279 A JP 3023279A JP 3023279 A JP3023279 A JP 3023279A JP S55123147 A JPS55123147 A JP S55123147A
Authority
JP
Japan
Prior art keywords
film
layer
polycrystalline
diffusion layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3023279A
Other languages
Japanese (ja)
Inventor
Kazunari Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3023279A priority Critical patent/JPS55123147A/en
Publication of JPS55123147A publication Critical patent/JPS55123147A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain wirings of low resistance, small diffusion layer capacity and high density by a method wherein an impurity is introudced through a polycrystalline Si layer to have a diffusion layer as a conductive body for wiring. CONSTITUTION:A polycrystalline Si film 2 on a p-type Si substrate 1 is opened by an Si3N4 film 3, and a p<+>-channel stopper and field oxide film is provided. The Si3N4 film is opened extensively, a shallow n-layer is formed on the substrate 1 and a double wiring layer of low resistance is provided. An SiO2 film 7 is selectively formed, the Si3N4 film 3 and polycrystalline Si film 2 are removed by engraving, a gate oxide film is formed and a gate electrode 9' and a conductive body 9'' for wiring by an n-type polycrystalline Si layer are selectively formed. Then, a shallow n-layer is provided on it with the electrode 9' as a mask, convered with a PSG film 11 and selectively opened a window to have an Al-electrode 12 provided on. With this constitution, a diffusion layer is made shallow with less horizontal diffusion, a wiring density is improved and a diffusion layer capacity is also small. It can have other wirings crossed, further, if the polycrystalline Si film on the diffusion layer is oxidized to form an insulation film on the surface.
JP3023279A 1979-03-15 1979-03-15 Semiconductor device Pending JPS55123147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3023279A JPS55123147A (en) 1979-03-15 1979-03-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3023279A JPS55123147A (en) 1979-03-15 1979-03-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55123147A true JPS55123147A (en) 1980-09-22

Family

ID=12297957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3023279A Pending JPS55123147A (en) 1979-03-15 1979-03-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55123147A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085285A (en) * 1973-11-23 1975-07-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085285A (en) * 1973-11-23 1975-07-09

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