JPS55122293A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS55122293A
JPS55122293A JP2877879A JP2877879A JPS55122293A JP S55122293 A JPS55122293 A JP S55122293A JP 2877879 A JP2877879 A JP 2877879A JP 2877879 A JP2877879 A JP 2877879A JP S55122293 A JPS55122293 A JP S55122293A
Authority
JP
Japan
Prior art keywords
information
memory
circuit
module
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2877879A
Other languages
Japanese (ja)
Other versions
JPS6144345B2 (en
Inventor
Isamu Yasui
Kazuo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2877879A priority Critical patent/JPS55122293A/en
Publication of JPS55122293A publication Critical patent/JPS55122293A/en
Publication of JPS6144345B2 publication Critical patent/JPS6144345B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Shift Register Type Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To reduce the number of additional memories to be installed to simplify a circuit constitution, by using a common additional memory where defective loop information is written for every plural unit information. CONSTITUTION:Bubble memory information is read out from bubble module 1a, and AND between this information and selection command signal A is operated by data selector 4 and is inputted to data re-arrangement circuit 6. Simultaneously, defective loop information for bytes of module 1a is read out from memory 2 on a basis of additional memory address register 3 and is inputted to circuit 6. In circuit 6, data information read from module 1a is re-arranged to the correct bit position dependent upon only good loops where defective loops are removed according to input information from memory 2. In this case, information read from memory 2 for modules 1a as well as 1b is the same information in respect to the same byte position.
JP2877879A 1979-03-14 1979-03-14 Memory control system Granted JPS55122293A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2877879A JPS55122293A (en) 1979-03-14 1979-03-14 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2877879A JPS55122293A (en) 1979-03-14 1979-03-14 Memory control system

Publications (2)

Publication Number Publication Date
JPS55122293A true JPS55122293A (en) 1980-09-19
JPS6144345B2 JPS6144345B2 (en) 1986-10-02

Family

ID=12257851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2877879A Granted JPS55122293A (en) 1979-03-14 1979-03-14 Memory control system

Country Status (1)

Country Link
JP (1) JPS55122293A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485643A (en) * 1977-12-20 1979-07-07 Nec Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485643A (en) * 1977-12-20 1979-07-07 Nec Corp Memory unit

Also Published As

Publication number Publication date
JPS6144345B2 (en) 1986-10-02

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