JPS6144345B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a memory device suitable for a magnetic bubble memory, a charge-coupled device (CCD) memory, and an IC memory, which are shift register memories.

In memory devices that are shift register type and consist of multiple information loops, such as magnetic bubble memory and charge-coupled device memory used as file memory for electronic switching equipment, some information loops may not be usable, including chips. It is used to improve chip yield. In order to avoid using this unusable information loop, an additional memory is provided in the magnetic bubble memory device to store the loop position information of the unusable loop (hereinafter referred to as a defective loop). When it is read, it is identified and the defective loop is not used.

1 and 2 are diagrams explaining conventional position information read control of a defective loop, and FIGS. 1a and 2c are information loop arrangement diagrams of a magnetic bubble memory including a defective loop, and FIG. b, d are additional memory write state diagrams of the defective loop corresponding to FIGS. 1a, 1c. Further, FIG. 2 is a circuit block diagram for achieving the control method shown in FIG. 1.

In FIGS. 1a and 1c, the horizontal axis numbers indicate minor loop numbers for storing information, and the vertical axis indicates information bit positions of each chip. The good loops that can be used are shown in an empty state, and the bad loops that cannot be used are shown with an x mark. In FIG. 1a, for example, it can be seen that the chip showing ²⁰ has no defective loops, and the chips showing ²¹ have defective loops at the 7th and 11th.

The magnetic bubble memory device of this example has 1 byte (8
This is a device that uses the information of
The 0th byte in figure a is 2 ⁰ ~ as shown by the broken line.
2 Use the 0th 8 minor loops of each up to ₇ chips. Next, as the first byte, 2 ⁰ to 2 ³ , 2 ⁵
~2 Use the first 8 minor loops of each of the ⁸ chips. Then, paying attention to the 7th byte, the valid minor loop is 7 of ²⁰ , ²² , ²⁴ , ²⁶ to ²⁸ chips.
Since there are only two minor loops, it is impossible to construct one byte, and in such a case, the seventh byte is skipped and the eighth of the ²⁰ to ²⁷ chips is accessed at the next timing in time. Assign the information of the 7th byte to the minor loop.

FIG. 1b shows the information in the additional memory for FIG.
Bad loop position + "1", if there are two or more bad loops (for example, the 7th minor loop in Figure 1 a)
are set to write all "1"s. The same applies to the additional memory of FIG. 1d, which corresponds to FIG. 1c.

On the other hand, such as magnetic bubble memory devices,
In a mass file storage device, in order to make the direct peripheral part of the memory more economical, the direct peripheral part is shared. In magnetic bubble memory devices, coil drivers, chip drivers, sense amplifiers, etc. are switched and used for each bubble module. That is, in FIG. 1, the portions a and c correspond to bubble modules, and the corresponding additional memory information corresponds to b and d.

Next, read control of the defective loop position information shown in FIG. 1 will be explained with reference to the circuit block shown in FIG. 2. In the figure, 1a and 1b are bubble modules, 2a and 2b are additional memories, and 3 is additional memory 2.
4 is a data selector consisting of AND circuits 7 and 8, which outputs the output of the bubble module 1a and the selection command signal A, and the output of the bubble module 1b and the selection command signal B. The logical product is calculated. 5 is
An additional memory data selector 5 comprising AND circuits 9 and 10 performs a logical product between the output of the additional memory 2a and the selection command signal A, and the output of the additional memory 2b and the selection command signal B. Reference numeral 6 denotes a data rearrangement circuit which receives the output signals of the data selector 4 and the additional memory data selector 5 and rearranges the data of the bubble modules 1a and 1b.

According to the circuit block in FIG. 2, in accessing by a command from a host device (not shown),
For example, bubble memory information is bubble module 1a.
When the byte is read out, the defective loop information corresponding to that byte is read out from the additional memory 2a based on the address information from the additional memory address register 3. That is, the selection command signal A that is input when the bubble module 1a is selected and the read information of each bubble module 1a and the additional memory 2a are logically multiplied by the data selector 4 and the additional data selector 5. and inputs it to the data rearrangement circuit 6. Here too, the output of the bubble module 1a excludes the defective loop,
The bits are rearranged to the correct bit positions forming a so-called good loop. The same applies to the control operation of the other bubble module 1b, and the same configuration is used even when a plurality of bubble modules are provided, in which case the additional memory naturally corresponds to the number of bubble modules. It will increase.

The magnetic bubble memory control method explained in Figures 1 and 2 is an effective means for improving the yield of bubble chips, but since the rate of occurrence of defective loops in bubble chips is almost determined by the manufacturing process, If the loop occurrence rate is extremely low, the usage efficiency of the additional memory provided for each bubble module will decrease, resulting in waste of the additional memory installed. There is also the problem of defects in IC memory. Same as magnetic bubble and CCD
Even in IC memory, defects occur in the storage area (including defects in the IC element itself and defects in the drive part), and countermeasures to these defects can be solved to a certain extent by using additional memory, similar to magnetic bubbles and CCDs. . However, in the case of a memory device that uses a plurality of IC memories, if additional memory is provided for each memory device, the number of additional memories will increase.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, increase the efficiency of use of additional memory, and provide an economical memory control method.

The present invention eliminates the conventional method of writing defective loop information to an additional memory for each unit of information, and instead writes defective loop information for each of a plurality of units of information. In other words, it has an additional memory that can write position information of a defective loop for multiple units of information to the same address, and reads predetermined position information from the additional memory to avoid and use defective loops. It is something. below,
An embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

Figure 3 a is the OR information of the defective loops in Figure 1 a and c, and the coded version of this is the third
Figure b. That is, one additional memory is provided for each of the two bubble modules shown in FIGS. 1a and 1c, as shown in FIG. I try to write the information that was originally coded. Therefore, whether you access the bubble module shown in FIG. 1a or the bubble module shown in FIG. 1c, the same additional memory shown in FIG. The form of the minor loop is the same for both bubble modules. In this case, since the OR information of the defective loop information is stored in the additional memory, the defective loop will not be used in either bubble module.

This will be explained according to the circuit block of FIG. In FIG. 4, the same reference numerals as those in FIG. 2 indicate the same things, but in this example, one additional memory 2 is commonly used for the bubble modules 1a and 1b. It is. This eliminates the need for the additional data selector provided between the additional memory 2 and the data rearrangement circuit 6.

According to FIG. 4, upon access by a command from a host device (not shown), bubble memory information is read from the bubble module 1a, and the data selector 4 performs a logical product with the selection command signal A to reproduce the data. It is input to the array circuit 6. At the same time, the defective loop information for the byte of the bubble module is read from the additional memory 2 based on the additional memory address register 3 and input to the data rearrangement circuit 6. Data rearrangement circuit 6
In this case, the data information read from the bubble module 1a is rearranged in accordance with the input information from the additional memory 2 to the correct bit position with only good loops excluding bad loops. In this case, for the same byte position, the information read from the additional memory 2 is the same for both bubble modules 1a and 1b. It will be explained in further detail.

Bubble memory modules 1a and 1b have the same storage capacity. For example, if we look at the example in Figure 3a,
It becomes 9 x 131 bits. Generally, it is several kilobytes or tens of kilobytes, and can even reach several tens of kilobytes. These two bubble memory modules 1a and 1b are, for example, module 1a uses addresses (byte units) of 0 to 4K, and module 1b uses addresses (byte units) of 4K or more.
When using 8K, addresses are divided.

In FIG. 4, selection command signal A selects the output of bubble memory module 1a, and selection command signal B selects the output of bubble module 1b.

First, while the selection command signal A is input, the read data from the bubble module 1a passes through the AND gate 7 and the OR gate 4 to the data rearrangement circuit 6.
sent to. On the other hand, the same address as the access address of the bubble module (in the above description, it is an address within the module; in this case, it is not a complete address match) is given to the address register 3, and the additional memory 2 is accessed. The contents of the additional memory 2 are read out according to this address.

When the read data from the additional memory 2 is the eighth data "1111" in FIG. 3b, the data rearrangement circuit 6 determines that the eighth loop of the bubble module 1a is defective and unusable. do.
On the other hand, when the read data from the additional memory 2 is the second data "1010" in FIG. Yes, it is judged to be unusable. The remaining bits are then used in place of the unusable bits.

Based on this judgment, the data rearrangement circuit 6
In this case, loops such as the seventh loop, where the entire loop is unusable, are not used as data. Also, the second
The fifth bit of the second loop is also not used as data. The data is rearranged for the portions excluding these defective portions.

On the other hand, while the selection command signal B is input, the read data from the bubble module 1a passes through the AND gate 8 and the OR gate 4 to the data rearrangement circuit 6.
sent to. On the other hand, the same address as the access address of the bubble module is given to the address register 3, and the additional memory 2 is accessed. The contents of the additional memory 2 are read out according to this address.

The read data from the additional memory 2 is shown in FIG.
When the eighth data is "1111", the data rearrangement circuit 6 determines that the eighth loop of the bubble module 1b is defective and unusable. However, since the data in the additional memory uses OR logic of the defect information of modules 1a and 1b, there is no defect in the 8th loop of module 1b, but there is a defect in the 8th loop of module 1a. Maybe. Furthermore, module 1a may not be defective, but module 1b may be defective. Also, both modules may be defective. In both of these cases, defect information is stored in the additional memory.

On the other hand, when the second data in FIG. 3B is "1010", it is determined that there is a defect in the fifth bit position in the second loop. Since this defect also uses OR logic, it cannot be specified as either module 1a or 1b. If at least one of the bits is defective, that bit is considered defective and replaces the other bit.

When reading data from the module 1b, the data rearrangement circuit 6 makes the above judgment and then rearranges the data excluding defective portions.

As mentioned above, one additional memory is provided that can be used commonly by two bubble modules, and data can be rearranged even in good loops excluding bad loops. Additional memory can be used effectively even when the rate of occurrence of defective loops within a module or the same bubble module is low.

In addition, in the above-mentioned embodiment, the case where one additional memory was provided for two bubble modules was explained as an example, but the number is not limited to this. In addition, although we have described the case where the additional memory is shared for the corresponding bytes in each module, it is also possible to share the additional memory for each multiple bytes within the same module, for example, the Nth byte (N+1)th byte. is also easily possible. By using a common additional memory even for IC memory, common efficient use has become possible.

As described above, the present invention includes an additional memory that can write position information of a defective loop for a plurality of units of information to the same address, and removes a defective loop based on the position information read from the additional memory. The data information is rearranged. Therefore, according to the present invention, since the additional memory can be used in common for each unit of information, the number of additional memories to be installed can be reduced, and the circuit configuration can be simplified, resulting in great economic effects.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining the conventional memory control method, in which FIGS. 1a and 1c show the presence or absence of a defective loop in the information loop, and FIGS. 1b and d show the presence or absence of a defective loop in the information loop. Figures 3 and 4 are diagrams showing information states of the additional memory corresponding to Figures a and c, and are for explaining an embodiment of the present invention.
is an information loop state diagram when the defective loops in FIG. 1 a and c are added, FIG. 3 b is a diagram showing the information state of the additional memory for FIG. 3 a, and FIG. FIG. 2 is a circuit block diagram for achieving the above. 1a, 1b... Bubble module, 2... Additional memory, 3... Address register, 4... Data selector, 6... Data rearrangement circuit, 7, 8...
AND circuit, A, B...selection command signal.

Claims (1)

[Scope of Claims] 1. First and second memory devices that are accessed separately from each other, and information on the presence or absence of defects at mutually corresponding positions in the storage areas of the first and second memory devices by OR logic. and an additional memory for storing the common defect display information as common defect display information; and when the first and second memory devices are read accessed, the additional memory is also accessed, the common defect display information is read from the additional memory, and the common defect display information is stored as the common defect display information. The displayed information is determined, and if it is defective information, the data read from the first and second memory devices read at that time is excluded as defective data, and if it is not defective data, the data read from the first and second memory devices read at that time is excluded. A control device for a memory device, comprising means for selecting data read from the memory as normal data.