JPS5485643A - Memory unit - Google Patents
Memory unitInfo
- Publication number
- JPS5485643A JPS5485643A JP15392677A JP15392677A JPS5485643A JP S5485643 A JPS5485643 A JP S5485643A JP 15392677 A JP15392677 A JP 15392677A JP 15392677 A JP15392677 A JP 15392677A JP S5485643 A JPS5485643 A JP S5485643A
- Authority
- JP
- Japan
- Prior art keywords
- magnetic field
- memory
- driving circuit
- bubble
- memory unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To reduce the capacity of the memory loop state memory unit as well as to reduce the cost for the memory unit as a whole by classifying the memory loop into some groups and then storing the normal and defective information with every group. CONSTITUTION:More than one unit of the magnetic bubble element containing the defective minor loop is stored in memory brain 301, and the following units are provided as the peripheral circuits to be connected to each component element of the magnetic bubble element: generator driving circuit 302; eraser driving circuit 303; transfer gate driving circuit 304; and sense amplifier 305 respectively. Furthermore, bias magnetic field device 306 is installed to supply the bias magnetic field for the steady existence of the bubble domain, along with rotary magnetic field device 307 to supply the magnetic field to shift the bubble domain. These circuits and devices are controlled by control circuit 308.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15392677A JPS5485643A (en) | 1977-12-20 | 1977-12-20 | Memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15392677A JPS5485643A (en) | 1977-12-20 | 1977-12-20 | Memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5485643A true JPS5485643A (en) | 1979-07-07 |
Family
ID=15573091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15392677A Pending JPS5485643A (en) | 1977-12-20 | 1977-12-20 | Memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5485643A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55122293A (en) * | 1979-03-14 | 1980-09-19 | Hitachi Ltd | Memory control system |
-
1977
- 1977-12-20 JP JP15392677A patent/JPS5485643A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55122293A (en) * | 1979-03-14 | 1980-09-19 | Hitachi Ltd | Memory control system |
JPS6144345B2 (en) * | 1979-03-14 | 1986-10-02 | Hitachi Ltd |
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