JPS5694577A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS5694577A JPS5694577A JP17195279A JP17195279A JPS5694577A JP S5694577 A JPS5694577 A JP S5694577A JP 17195279 A JP17195279 A JP 17195279A JP 17195279 A JP17195279 A JP 17195279A JP S5694577 A JPS5694577 A JP S5694577A
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- pair
- transistors
- dummy
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To increase the read-in margin, by making the level of bit line pair to the read level, through the connection of dummy cell group with dummy bit line pair by the arrangement toward bit line and the connection of the bit line pair to the base of detection transistors. CONSTITUTION:The dummy cell DC group is arranged toward the bit line B at a suitable location lengthwise the word line W, and each of them is connected to the respective word line W and common dummy bit line DB line pair. Further, this bit line DB pair is connected to the base of detection transistors T8, T10 and the voltage level of the bit line DB pair is taken as the read level RL. For example, the circuit as shown in Figure is constituted with the memory cell MC using FF consisting of multiemitter transistors Q1, Q2, dummy cell DC with the same construction, and constant current sources J1-J7 and the like, so that the transistors in o-mark are ON and those in x-mark are OFF.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17195279A JPS5694577A (en) | 1979-12-28 | 1979-12-28 | Semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17195279A JPS5694577A (en) | 1979-12-28 | 1979-12-28 | Semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5694577A true JPS5694577A (en) | 1981-07-31 |
Family
ID=15932824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17195279A Pending JPS5694577A (en) | 1979-12-28 | 1979-12-28 | Semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5694577A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0100851A2 (en) * | 1982-07-20 | 1984-02-22 | Siemens Aktiengesellschaft | Circuit arrangement for reading bipolar memory cells |
JPS60237698A (en) * | 1985-04-23 | 1985-11-26 | Hitachi Ltd | Sense circuit of semiconductor memory |
JPS63122090A (en) * | 1986-11-12 | 1988-05-26 | Hitachi Ltd | Semiconductor device |
-
1979
- 1979-12-28 JP JP17195279A patent/JPS5694577A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0100851A2 (en) * | 1982-07-20 | 1984-02-22 | Siemens Aktiengesellschaft | Circuit arrangement for reading bipolar memory cells |
JPS60237698A (en) * | 1985-04-23 | 1985-11-26 | Hitachi Ltd | Sense circuit of semiconductor memory |
JPH0378715B2 (en) * | 1985-04-23 | 1991-12-16 | Hitachi Ltd | |
JPS63122090A (en) * | 1986-11-12 | 1988-05-26 | Hitachi Ltd | Semiconductor device |
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