JPS55120130A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55120130A
JPS55120130A JP2850879A JP2850879A JPS55120130A JP S55120130 A JPS55120130 A JP S55120130A JP 2850879 A JP2850879 A JP 2850879A JP 2850879 A JP2850879 A JP 2850879A JP S55120130 A JPS55120130 A JP S55120130A
Authority
JP
Japan
Prior art keywords
substrate
layer
gate electrode
oxidizing atmosphere
good reproducibility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2850879A
Other languages
Japanese (ja)
Inventor
Kenji Shibata
Takahiko Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP2850879A priority Critical patent/JPS55120130A/en
Publication of JPS55120130A publication Critical patent/JPS55120130A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a diffusion layer with good reproducibility, by forming an impurity-added Si layer on an Si substrate or a substrate having an Si layer by a CVD method, heat-treating the product in high-temperature oxidizing atmosphere, and diffusing impurities into the substrate. CONSTITUTION:After a field-oxide film 2, a gate-oxide film 3', and a gate electrode 4' have been provided on a p-type Si substrate 1, Si layer 6 containing As of from 1X10<18>/cm<2>-5X10<22>/cm<2> is grown by the CVD method under the pressure within the range of 0.1-20 Torr, and is covered by an SiO2 film 7 to prevent in high- temperature oxidizing atmosphere. Thus, As is diffused and n<+> layers 8 and 9 are formed, and the resistance of the poly-Si-gate electrode becomes low. Then, the films 6 and 7 are removed, windows are selectively opened in a CVD SiO2 film 10, and electrodes 11 and 13 are formed. By this method, shallow diffusion layers having good reproducibility can be formed without generation of protrusions or excessive etching on the substrate.
JP2850879A 1979-03-12 1979-03-12 Manufacture of semiconductor device Pending JPS55120130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2850879A JPS55120130A (en) 1979-03-12 1979-03-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2850879A JPS55120130A (en) 1979-03-12 1979-03-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55120130A true JPS55120130A (en) 1980-09-16

Family

ID=12250617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2850879A Pending JPS55120130A (en) 1979-03-12 1979-03-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55120130A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942814A (en) * 1972-09-01 1974-04-22
JPS5358490A (en) * 1976-11-05 1978-05-26 Mitsubishi Electric Corp Forming method for film
JPS5398775A (en) * 1977-02-09 1978-08-29 Hitachi Ltd Gas phase growth unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942814A (en) * 1972-09-01 1974-04-22
JPS5358490A (en) * 1976-11-05 1978-05-26 Mitsubishi Electric Corp Forming method for film
JPS5398775A (en) * 1977-02-09 1978-08-29 Hitachi Ltd Gas phase growth unit

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