JPS5511347A - Manufacture of dielectric insulated separation substrate - Google Patents

Manufacture of dielectric insulated separation substrate

Info

Publication number
JPS5511347A
JPS5511347A JP8393778A JP8393778A JPS5511347A JP S5511347 A JPS5511347 A JP S5511347A JP 8393778 A JP8393778 A JP 8393778A JP 8393778 A JP8393778 A JP 8393778A JP S5511347 A JPS5511347 A JP S5511347A
Authority
JP
Japan
Prior art keywords
film
sio
grooves
wafer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8393778A
Other languages
Japanese (ja)
Other versions
JPS6056291B2 (en
Inventor
Setsuro Yagyu
Takaya Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8393778A priority Critical patent/JPS6056291B2/en
Publication of JPS5511347A publication Critical patent/JPS5511347A/en
Publication of JPS6056291B2 publication Critical patent/JPS6056291B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To obtain substrates almost without pinhole through the process consisting providing separating grooves on the surface of a monocrystalline wafer, covering the whole surface of said substrate with SiO2 film, placing said substrate in an epitaxial formation furnace for the formation of SiO2 and polycrystalline Si layers on said film by CVD method, and alternatively laying a required quantity of said layers one upon another.
CONSTITUTION: A monocrystalline Si wafer 12 is selectively etched for forming separating grooves 13 and, after the whole surface thereof covered with SiO2 film 14, placed in an epitaxial formation reactor furnace. Next, SiO2 film layer 15 is first formed on said film 14 by CVD method with said water 12 heated up to 1,100W 1,250°C while SiHCl3, H2 and CO2 are kept flowing. Therefore, polycrystalline Si layer 16 is formed on said film 15 by using Si chloride on said reactor furnace, and a dielectris is made of said layer 16 and film 15. Said dielectric is increased to a desired thickness by repeating the process described heretofore if necessary, SiO2 film is deposited on the whole surface including the grooves 17 corresponding to said grooves 13 still remaining after shallowing, of said wafer 12, and thus-obtained surface is smoothened.
COPYRIGHT: (C)1980,JPO&Japio
JP8393778A 1978-07-12 1978-07-12 Manufacturing method of dielectric insulation isolation substrate Expired JPS6056291B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8393778A JPS6056291B2 (en) 1978-07-12 1978-07-12 Manufacturing method of dielectric insulation isolation substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8393778A JPS6056291B2 (en) 1978-07-12 1978-07-12 Manufacturing method of dielectric insulation isolation substrate

Publications (2)

Publication Number Publication Date
JPS5511347A true JPS5511347A (en) 1980-01-26
JPS6056291B2 JPS6056291B2 (en) 1985-12-09

Family

ID=13816497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8393778A Expired JPS6056291B2 (en) 1978-07-12 1978-07-12 Manufacturing method of dielectric insulation isolation substrate

Country Status (1)

Country Link
JP (1) JPS6056291B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139042A (en) * 1984-12-10 1986-06-26 エイ・ティ・アンド・ティ・コーポレーション Reduction of spring back in warp of substrate using polysilicon subsurface strain layer
JPS63182836A (en) * 1987-01-24 1988-07-28 Matsushita Electric Works Ltd Manufacture of dielectric isolation substrate
US5081061A (en) * 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139042A (en) * 1984-12-10 1986-06-26 エイ・ティ・アンド・ティ・コーポレーション Reduction of spring back in warp of substrate using polysilicon subsurface strain layer
JPS63182836A (en) * 1987-01-24 1988-07-28 Matsushita Electric Works Ltd Manufacture of dielectric isolation substrate
US5081061A (en) * 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers

Also Published As

Publication number Publication date
JPS6056291B2 (en) 1985-12-09

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