GB2289060A - Method for producing an insulation layer on a silicon wafer - Google Patents
Method for producing an insulation layer on a silicon wafer Download PDFInfo
- Publication number
- GB2289060A GB2289060A GB9508954A GB9508954A GB2289060A GB 2289060 A GB2289060 A GB 2289060A GB 9508954 A GB9508954 A GB 9508954A GB 9508954 A GB9508954 A GB 9508954A GB 2289060 A GB2289060 A GB 2289060A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon
- layer
- insulation layer
- oxide
- porous structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 33
- 239000010703 silicon Substances 0.000 title claims description 33
- 229910052710 silicon Inorganic materials 0.000 title claims description 31
- 238000009413 insulation Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 238000000034 method Methods 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000000354 decomposition reaction Methods 0.000 claims 1
- ALIFPGGMJDWMJH-UHFFFAOYSA-N n-phenyldiazenylaniline Chemical compound C=1C=CC=CC=1NN=NC1=CC=CC=C1 ALIFPGGMJDWMJH-UHFFFAOYSA-N 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 25
- XJKVPKYVPCWHFO-UHFFFAOYSA-N silicon;hydrate Chemical compound O.[Si] XJKVPKYVPCWHFO-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005755 formation reaction Methods 0.000 description 3
- 235000012149 noodles Nutrition 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- SURLGNKAQXKNSP-DBLYXWCISA-N chlorin Chemical compound C\1=C/2\N/C(=C\C3=N/C(=C\C=4NC(/C=C\5/C=CC/1=N/5)=CC=4)/C=C3)/CC\2 SURLGNKAQXKNSP-DBLYXWCISA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- -1 oxygen Ions Chemical class 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
Description
4 2289060 productnct an insulation I&Xor on a silicon 5 waf er
Prior art
The Invention Is based on a zamthod for producing an Insulation layer on a silicon water onto which a monocrystalline silicon Is applied, according to the prechar- acter zing clause of the main claim. in the so-called 1 S111con-on- Insulator' technology It ils already known, for example, to bond a solid silicon water directly onto a second, thermally oxidized silicon water and subaecniently to grind It back and/a= etch It to the desired thickness. ?or thickness control In thin came, use may be =ado ot temporally controlled methods, nocalled grinding atops using oxide landa or etching stop In elect=ochomical etching.
In another known method, highly energetic oxygen Ions are i=lanted Into the silicon surface of the water, 00 that a buried oxygen-enriched silicon lay= In produced below a partially amorphized silicon surface. in a the=mal annealing step, the oxygen-enriched layer in converted into silicon dioxide and the overlying, par- tIally -orphized silicon surface layer Is recrystallized (SIMOX method). This thin silicon surface layer can subsequently be Opitaxially reinforced.
in another method, polyallicon In deposited onto a structured silicon oxide layer and In converted 3D according to a zone-zaeltlng method to form full-Ourfaco monocrystalline silicon on oxide.
The kncnm methods have tile disadvantage that their Individual working stages are relatively expenolve and cost-intensive. The Ion implantation method In, In particular, very expensive. In addition, In the known methods, the recrystallized silicon-on-inoulator layer 0 (501 layer) ban a high defect density, so that failures In Integration of the circuits are frequently to be expected.
Advantages of the Invention The method according to the Invention for produc ing an Insulation layer on a silicon water, according to the procharacteri=ing clause of the main claim, has the advantage thereover that it can be carried out with few and simple working stops. An a result of this, the insulation layer can be produced cost-effectively on the silicon water. in addition# relatively few crystal defects occur during foroation of the insulation layer. so that the Insulation properties arm outf lclent for many. applications.
by virtu Qt the measures Slym In the dependent claims, advantageous developments and 1Wrovementa of the method specified in the main claim are possible. it Is particularly advantageous that, before growth of the Insulation layer, the surface of the 0111con water he converted do to a prodotcod depth into a porous structure with a dense arrangement of silicon needles. By virtue of the needle arrangement, a large surface area results, which in particularly well-ouited for the subsequent oxidation. A porous structure of this type can, for c lot be formed by an eloctrochemical etcUng process In aqueous hydrofluoric acid or by a plasma etching process.
It l& also advantageous that, during the subsequent thermal oxidation, the silicon needles be partly decomposed and the Intermediate spaces be filled up with oxide. Depending on the duration of action of the temperature and reaction games, thle oxidation process results, On the One hand. In a relatively smooth surface and, on the other hand, good control of the oxidation process can he obtained by controlling the duration of action.
A further 15110 wor stop also consists in that, after the oxidation process, the excess silicon t dioxide on the surface is selectively removed dow to the silicon needle surfaces, so that a planar surface with silicon and silicon dioxide regions results. Preferably monocrystalline silicon can then subsequently be deposited onto this surface according to known opitaxial methods. it la J1.urther advantageous that the oxygen enclosed In the Insulation layer he redistributed In a simple high-t=Werature process and thereby to= a stable Insulation layer which In not susceptible to reaction.
Drawing An exe=plary embodlacwt of tChe Invention Is reuresented In the drawing dad explained In more detail In the following description. Figures I&, 1b, le and ld allow a silicon water in various processing Stagese is Description of the ex lary emb odiment in the method according to the Invention, a silicon dioxide layer In firat produced an the insulation layer 4, which silicon dioxide layer contains suffIcient silicon seed calls for an ordered, epitaxial growth of a monocrystailine aillcon layer. =a thin case, the crystal orientation corresponds to that of the substrate. After this growth process# the silicon oxide layer In converted by a high-temperature process into ordinary oxide and the mentioned seed calls are thereby eliminated. The method according to the invention is based, corresponding to ?Igure I&, on a sillcon water 1, In which one surface Initially has a porous structure with a predetermined depth a. A structure ci thin type can, for ole, be formed by elactrochemical anodic treatment In aqueous hydrofluoric acid or also by a plan etching process with "black alllcona formation. A nblack silicon forma tion occurs, for ex amp is, in a chlorin etching process which In Intentionally carried out under process condi tions which load to the normally =desired black allicono formatIon. By virruo of thin process. a dwme arrangement, corresponding to Figure I&, of silicon needles 2 is formed In the porous structure 4. The depth a of the porous structure 4 can h controlled by vi=tue of the arrangement of the etching process.
Figure lb shown the silicon water 1 in a subsequent working stop after the the oxidation. An a 5 result of the influence of toWerature and, oxygen, an SIO, layer 3 has to=ed on the porous structure 4 and has accumulated both on the silicon noodles 2 and la the Intermediate spaces. An a result of the thermal oxidation, a proportion of tho willcon noodlen 2 has boon consumed and the enlarged Intermediate spaces have been filled up by the silicon oxide 3. Since, In the case of an advanced oxidation proccost In which the Intermediate spaces are already filled up with silicon oxide 3, additional oxygen can then only diffuse In úrcna the surface# the oxidation process proceeds t=cxa then = cnaly at a slowed rate. This Is advantagemm for controlling the process. wince the oxide layer thickness can thereby be controlled "It accurately by mcane of tin& andlor tmWmrature. Thin In favourable for advantageous process control.
In a subsequent efzch4- or grinding process. the excess silicon oxide 3 lying on the surface over the noodles 2 Is then stripped off, In order to obtain a planar surface. Silicon and silicon oxide regions air then arranged on the surface In close sepaxation. The silicon regions in this case servo an mend calls for the growth of the preferably monocrystalline opItaxial layer 5, an in represented In Pigure lc. The epitaxial layer 5 can In thin case be deposited according to the known method In the desired thúckness. Since the silicon noodles 2 from the previous porous structure 4 are arranged In clone asparation, even the Intermediate spaces are bridged during the opitaxial growth with a well- ordered crystal structure. A hmogenmous opltaxlal layer 5 therefore results.
After the growth of the apItaxial layer 5, the rmln:Lng oen 1= the Insulation laye:r In =ndistrlbuted with the partially oxidized porous silicon layer 4 In a further h:igh-te"a=ature process. In this can# the It 9 relatively unstable thin silicon needles 2 are decooned and likewise converted Into silicon oxide. Corresponding to Figure ld, an Inaulation layer 3 having slightly silicon-enriched the=aal oxide then reaults on the substrate wafer 1. The epitaxial layer 5 with preferably monocrystalline silicon Is arranged on thin thermal oxide 3. In this state, the silicon water 1 In then the starting material for Integration of electronic circuits.
is
Claims (10)
1. Method for producing an Insulation lay=, preferably a silicon oxide layer, on a silicon wafer, a silicon layer then being epitaxially applied onto the Insulation layer (ailic=-on-insulator), characterized by the following stepst a) an insulation layer (3) In applied by thermal oxIdation onto one surface of the silicon wafer (1) such that autticiant seed cello for an epitaxial growth of the preferably =onocrystalline silicon layer (OPItaxIal layer 5) are formed, h) an epitaxial layer (5) Is applied onto the ingulation layer (3), c) In a high-t-crature process, with decomposition of the remaining silicon so In the Insulation layer. the insulation layer (3) is converted into a h geneous silicon oxide layer (3).
2. Method according to Claim 1, characterized In that, betore the thermal oxidation. a surface of the silicon wafer (1) with a porous structure (4) In developed by forming a preferably branched silicon needle structure (2), the silicon needles (2) having a predeterainable depth (a) and being densely arranged.
3. Method according to Claim 2, chamacterized In that the porous structure (4) Isformed by clect=o- ch-ical anodic treatment In aqueous hydrofluoric acid.
4. Method according to Claim 2, characte=:L=ed In that the porous structure (4) Is to=acd by a plasma etching process with "black allicono formation.
5. Method according to Claim 2 or 3, characterized In that the porous structure (4) Is thermally oxidized such that the silicon needles (2) are partly decomponed by conversion Into oxide and the Inte=adiate spaces are therefore filled up zw= o= lens c=plately with oxide.
6. Method according to Claim 5, characterized in that the oxidation process can be controlled by the 4 IN duration of action andlor the twWorature.
7. Method according to one of the preceding claims. characterized In that, on the surface, the oxide of the insulation layer (3) Is selectively removed down to the rpm-ining excuse silicon of the needle structure (2), so that a planar surface of silicon and silicon oxide regions In close separation from each other results, the silicon-needle surfaces preferably retaining the crystal st=ctu=a of the substrate.
8. blethod according to Claim 7. characterized in that a preferably monocryntalline epitaxial layer (5) In applied onto the planar euriace.
9. Method according to Claim 8, characterized In that a high-tmWerature process la used which, In the insulation layer (3), converts the remaining silicon needles (2) Into silicon oxide by redistribution of the oxygen in the layer.
10. A method of producing an insulation layer substantially as herein described with reference to the accompanying drawing.
An insulation layer produced by a method as claimed in any of the preceding claims
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4415567A DE4415567B4 (en) | 1994-05-03 | 1994-05-03 | Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9508954D0 GB9508954D0 (en) | 1995-06-21 |
| GB2289060A true GB2289060A (en) | 1995-11-08 |
| GB2289060B GB2289060B (en) | 1998-01-07 |
Family
ID=6517169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9508954A Expired - Fee Related GB2289060B (en) | 1994-05-03 | 1995-05-03 | Method for producing an insulation layer on a silicon wafer |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE4415567B4 (en) |
| GB (1) | GB2289060B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007042521A2 (en) * | 2005-10-10 | 2007-04-19 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10345990B4 (en) * | 2003-10-02 | 2008-08-14 | Infineon Technologies Ag | Method for producing an oxide layer |
| DE102005048361B4 (en) * | 2005-10-10 | 2011-07-14 | X-FAB Semiconductor Foundries AG, 99097 | Method for locally coating semiconductor circuits and discrete components with a thermal SiO 2 layer whose surfaces contain areas with needle-shaped structures in nanometer dimensions |
| DE102005048366A1 (en) | 2005-10-10 | 2007-04-19 | X-Fab Semiconductor Foundries Ag | A process for the preparation of low-defect self-organized needle-like structures with nano-dimensions in the range below the usual light wavelengths with high aspect ratio |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0179491A2 (en) * | 1984-10-25 | 1986-04-30 | Nec Corporation | Formation of single-crystal silicon layer by recrystallization |
| US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
| JPH02194522A (en) * | 1989-01-23 | 1990-08-01 | Fuji Electric Co Ltd | Manufacture of soi substrate |
| GB2241114A (en) * | 1990-02-16 | 1991-08-21 | Mitsubishi Electric Corp | Method of producing soi structures |
| US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3053678B2 (en) * | 1991-10-23 | 2000-06-19 | ローム株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-05-03 DE DE4415567A patent/DE4415567B4/en not_active Expired - Fee Related
-
1995
- 1995-05-03 GB GB9508954A patent/GB2289060B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0179491A2 (en) * | 1984-10-25 | 1986-04-30 | Nec Corporation | Formation of single-crystal silicon layer by recrystallization |
| US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
| JPH02194522A (en) * | 1989-01-23 | 1990-08-01 | Fuji Electric Co Ltd | Manufacture of soi substrate |
| GB2241114A (en) * | 1990-02-16 | 1991-08-21 | Mitsubishi Electric Corp | Method of producing soi structures |
| US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
Non-Patent Citations (1)
| Title |
|---|
| WPI Accession No. 90-278169/37 & JP 2 194 522 A * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007042521A2 (en) * | 2005-10-10 | 2007-04-19 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
| WO2007042521A3 (en) * | 2005-10-10 | 2008-06-12 | X Fab Semiconductor Foundries | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
| US8350209B2 (en) | 2005-10-10 | 2013-01-08 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9508954D0 (en) | 1995-06-21 |
| DE4415567A1 (en) | 1995-11-09 |
| GB2289060B (en) | 1998-01-07 |
| DE4415567B4 (en) | 2004-11-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090503 |