DE4415567B4 - Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon - Google Patents
Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon Download PDFInfo
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- DE4415567B4 DE4415567B4 DE4415567A DE4415567A DE4415567B4 DE 4415567 B4 DE4415567 B4 DE 4415567B4 DE 4415567 A DE4415567 A DE 4415567A DE 4415567 A DE4415567 A DE 4415567A DE 4415567 B4 DE4415567 B4 DE 4415567B4
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- silicon
- layer
- insulation layer
- oxide
- porous structure
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 239000010703 silicon Substances 0.000 title claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 65
- 238000009413 insulation Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 239000012212 insulator Substances 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910021418 black silicon Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000002048 anodisation reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 58
- 238000005530 etching Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009303 advanced oxidation process reaction Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 210000004602 germ cell Anatomy 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
Abstract
Verfahren
zur Erzeugung einer SOI-Struktur (Silicon-on-Insulator) mit einer Isolationsschicht
auf einem Siliziumwafer und einer darauf epitaktisch aufgebrachten
Siliziumschicht, mit folgenden Schritten:
a) auf einer Oberfläche des
Siliziumwafers (1) wird eine Isolationsschicht (3) durch thermische
Oxidation derart aufgebracht, dass genügend Siliziumkeime für ein epitaktisches
Aufwachsen der Siliziumschicht (5) gebildet werden,
b) auf
die Isolationsschicht (3) wird eine Siliziumschicht (5) epitaktisch
aufgebracht,
c) in einem Hochtemperaturprozess wird die Isolationsschicht
(3) unter Abbau der verbliebenen Siliziumkeime in der Isolationsschicht
in eine homogene Siliziumoxidschicht (3) umgewandelt.Method for producing an SOI structure (Silicon-on-Insulator) with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon, with the following steps:
a) an insulation layer (3) is applied to a surface of the silicon wafer (1) by thermal oxidation in such a way that sufficient silicon nuclei are formed for epitaxial growth of the silicon layer (5),
b) a silicon layer (5) is applied epitaxially to the insulation layer (3),
c) in a high-temperature process, the insulation layer (3) is converted into a homogeneous silicon oxide layer (3) while the remaining silicon nuclei in the insulation layer are broken down.
Description
Die Erfindung geht aus von einem Verfahren zur Herstellung einer Isolationsschicht auf einem Siliziumwafer, auf der monokristallines Silizium aufgebracht wird, nach der Gattung des Hauptanspruchs. Bei der sogenannten 'Silicon-on-Insulator'-Technik ist schon bekannt, beispielsweise einen massiven Siliziumwafer gegen einen zweiten, thermisch oxidierten Siliziumwafer direkt zu bonden und anschließend rückzuschleifen und/oder auf die gewünschte Dicke zu ätzen. Zur Dickenkontrolle können dabei zeitkontrollierte Verfahren, sogenannte Schleifstopps mit Hilfe von Oxidinseln oder Ätzstopps bei elektrochemischem Ätzen eingesetzt werden.The The invention is based on a method for producing an insulation layer on a silicon wafer on which monocrystalline silicon is applied is, according to the genus of the main claim. With the so-called 'silicon-on-insulator' technology is already known, for example a massive silicon wafer against one to bond the second, thermally oxidized silicon wafer directly and then loop back and / or to the desired one Etch thickness. For thickness control time-controlled processes, so-called grinding stops With the help of oxide islands or etch stops in electrochemical etching be used.
Bei einem weiteren bekannten Verfahren werden hochenergetische Sauerstoffionen in die Siliziumoberfläche des Wafers implantiert, so daß eine vergrabene sauerstoffangereicherte Siliziumschicht unter einer teilweise amorphisierten Siliziumoberfläche erzeugt wird. In einem thermischen Ausheilschritt wird die sauerstoffangereicherte Schicht in Siliziumdioxid umgewandelt und die darüber liegende, teilweise amorphisierte Siliziumoberflächenschicht rekristallisiert (SIMOX-Verfahren). Diese dünne Siliziumoberflächenschicht kann anschließend epitaktisch verstärkt werden.at Another known method uses high-energy oxygen ions into the silicon surface implanted of the wafer so that a buried oxygen-enriched silicon layer under a partially amorphized silicon surface is produced. In a thermal annealing step, the oxygen-enriched Layer in silicon dioxide and the overlying, partially amorphized silicon surface layer recrystallized (SIMOX) method. This thin one Silicon surface layer can then epitaxially reinforced become.
Bei einem weiteren Verfahren wird auf einer strukturierten Siliziumoxidschicht Polysilizium abgeschieden, das nach einem Zonenschmelzverfahren zu ganzflächigem, einkristallinem Silizium auf Oxid umgewandelt wird.at Another method is on a structured silicon oxide layer Polysilicon deposited, which after a zone melting process All Over, monocrystalline silicon is converted to oxide.
In
Schließlich wird
in
Die bekannten Verfahren haben den Nachteil, daß ihre einzelnen Arbeitsgänge relativ aufwändig und kostenintensiv sind. Insbesondere das Ionenimplantationsverfahren ist sehr aufwändig. Hinzu kommt, daß bei den bekannten Verfahren die rekristallisierte Silicon-on-Insulator-Schicht (SOI-Schicht) hohe Defektdichten aufweist, so daß häufig Ausfälle bei der Integration der Schaltungen zu erwarten sind.The known methods have the disadvantage that their individual operations are relative costly and are expensive. Especially the ion implantation procedure is very complex. In addition, at the known methods, the recrystallized silicone-on-insulator layer (SOI layer) has high defect densities, so that often failures in the integration of the Circuits are expected.
Das erfindungsgemäße Verfahren zur Herstellung einer Isolationsschicht auf einem Siliziumwafer nach der Gattung des Hauptanspruchs hat demgegenüber den Vorteil, daß es mit wenigen und einfachen Arbeitsschritten durchführbar ist. Dadurch ist die Isolationsschicht auf dem Siliziumwafer kostengünstig herstellbar. Hinzu kommt, daß bei der Bildung der Isolationsschicht re lativ wenig Kristalldefekte auftreten, so daß die Isolationseigenschaften für viele Anwendungen ausreichen.The inventive method for producing an insulation layer on a silicon wafer according to the genus of the main claim has the advantage that it with a few simple steps can be carried out. This is the Insulation layer on the silicon wafer can be produced inexpensively. Come in addition, that at the formation of the insulation layer relatively few crystal defects occur so that the Isolation properties for many applications are sufficient.
Durch die in den abhängigen Ansprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen des im Hauptanspruch angegebenen Verfahrens möglich. Besonders vorteilhaft ist, daß vor dem Aufwachsen der Isolationsschicht die Oberfläche des Siliziumwafers bis zu einer vorgegebenen Tiefe in eine poröse Struktur mit einer dichten Anordnung von Siliziumnadeln umgewandelt wird. Durch die Nadelanordnung ergibt sich eine große Oberfläche, die zur nachfolgenden Oxidation besonders gut geeignet ist. Eine derartige poröse Struktur kann beispiels weise durch einen elektrochemischen Ätzprozeß in wässriger Flußsäure oder durch einen Plasmaätzprozeß gebildet werden.The measures listed in the dependent claims allow advantageous developments and improvements of the method specified in the main claim. Especially before It is partial that, before the insulation layer is grown, the surface of the silicon wafer is converted to a predetermined depth into a porous structure with a dense arrangement of silicon needles. The needle arrangement results in a large surface area which is particularly well suited for the subsequent oxidation. Such a porous structure can, for example, be formed by an electrochemical etching process in aqueous hydrofluoric acid or by a plasma etching process.
Vorteilhaft ist auch, daß bei der anschließenden thermischen Oxidation die Siliziumnadeln zum Teil abgebaut werden und die Zwischenräume mit Oxid aufgefüllt werden. Je nach Einwirkdauer der Temperatur und Reaktionsgase ergibt sich bei diesem Oxidationsprozeß einerseits eine relativ glatte Oberfläche und andererseits ist der Oxidationsprozeß durch die Steuerung der Einwirkdauer gut beherrschbar.Advantageous is also that at the subsequent thermal oxidation the silicon needles are partially broken down and the gaps filled up with oxide become. Depending on the duration of exposure to temperature and reaction gases on the one hand in this oxidation process a relatively smooth surface and on the other hand the oxidation process is controlled by the exposure time easy to control.
Ein weiterer einfacher Arbeitsschritt besteht auch darin, daß nach dem Oxidationsprozeß das an der Oberfläche überschüssige Siliziumdioxid selektiv bis zu den Siliziumnadeloberflächen entfernt wird, so daß sich eine plane Oberfläche mit Silizium- und Siliziumdioxidbereichen ergibt. Auf diese Oberfläche kann dann anschließend nach bekannten epitaktischen Verfahren vorzugsweise monokristallines Silizium abgeschieden werden. Vorteilhaft ist weiter, daß der in der Isolationsschicht eingeschlossene Sauerstoff in einem einfachen Hochtemperaturprozeß umverteilt wird und damit eine stabile reaktionsgehemmte Isolationsschicht bildet.On Another simple step is that after Oxidation process that excess silicon dioxide on the surface is selectively removed up to the silicon needle surfaces, so that a flat surface with silicon and silicon dioxide areas. Can on this surface then afterwards according to known epitaxial processes, preferably monocrystalline Silicon are deposited. Another advantage is that the in the oxygen layer enclosed in a simple Redistributed high temperature process and thus a stable reaction-inhibited insulation layer forms.
Ein
Ausführungsbeispiel
der Erfindung ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung
näher erläutert. Die
Bei
dem erfindungsgemäßen Verfahren
wird zunächst
als Isolationsschicht
In
einem anschließenden Ätz- oder
Schleifprozeß wird
nun das auf der Oberfläche über den
Nadeln
Nach
dem Aufwachsen der Epitaxieschicht
Claims (8)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4415567A DE4415567B4 (en) | 1994-05-03 | 1994-05-03 | Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon |
GB9508954A GB2289060B (en) | 1994-05-03 | 1995-05-03 | Method for producing an insulation layer on a silicon wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4415567A DE4415567B4 (en) | 1994-05-03 | 1994-05-03 | Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon |
Publications (2)
Publication Number | Publication Date |
---|---|
DE4415567A1 DE4415567A1 (en) | 1995-11-09 |
DE4415567B4 true DE4415567B4 (en) | 2004-11-04 |
Family
ID=6517169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE4415567A Expired - Fee Related DE4415567B4 (en) | 1994-05-03 | 1994-05-03 | Method for producing an SOI structure with an insulation layer on a silicon wafer and a silicon layer epitaxially applied thereon |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE4415567B4 (en) |
GB (1) | GB2289060B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005048361A1 (en) * | 2005-10-10 | 2007-04-12 | X-Fab Semiconductor Foundries Ag | Method for passivating the surface of semiconductor silicon circuits and discrete components involves locally exposing surface of silicon and producing primary needle-like silicon structures by reactive ion etching |
US8350209B2 (en) | 2005-10-10 | 2013-01-08 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10345990B4 (en) * | 2003-10-02 | 2008-08-14 | Infineon Technologies Ag | Method for producing an oxide layer |
DE102005048366A1 (en) | 2005-10-10 | 2007-04-19 | X-Fab Semiconductor Foundries Ag | A process for the preparation of low-defect self-organized needle-like structures with nano-dimensions in the range below the usual light wavelengths with high aspect ratio |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
JPH05114561A (en) * | 1991-10-23 | 1993-05-07 | Rohm Co Ltd | Manufacture of semiconductor device |
US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61106484A (en) * | 1984-10-25 | 1986-05-24 | Nec Corp | Substrate for semiconductor device and its preparation |
JPH02194522A (en) * | 1989-01-23 | 1990-08-01 | Fuji Electric Co Ltd | Manufacture of soi substrate |
JP2802449B2 (en) * | 1990-02-16 | 1998-09-24 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-05-03 DE DE4415567A patent/DE4415567B4/en not_active Expired - Fee Related
-
1995
- 1995-05-03 GB GB9508954A patent/GB2289060B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
JPH05114561A (en) * | 1991-10-23 | 1993-05-07 | Rohm Co Ltd | Manufacture of semiconductor device |
US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005048361A1 (en) * | 2005-10-10 | 2007-04-12 | X-Fab Semiconductor Foundries Ag | Method for passivating the surface of semiconductor silicon circuits and discrete components involves locally exposing surface of silicon and producing primary needle-like silicon structures by reactive ion etching |
DE102005048361B4 (en) * | 2005-10-10 | 2011-07-14 | X-FAB Semiconductor Foundries AG, 99097 | Method for locally coating semiconductor circuits and discrete components with a thermal SiO 2 layer whose surfaces contain areas with needle-shaped structures in nanometer dimensions |
US8350209B2 (en) | 2005-10-10 | 2013-01-08 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
Also Published As
Publication number | Publication date |
---|---|
GB9508954D0 (en) | 1995-06-21 |
DE4415567A1 (en) | 1995-11-09 |
GB2289060B (en) | 1998-01-07 |
GB2289060A (en) | 1995-11-08 |
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