JPS5468175A - Electric field effect transistor of isolation gate type - Google Patents

Abstract

PURPOSE: To enable high dielectric strength and low turn-on resistance, by providing separate semiconductor layer between the semiconductor layer and the low concentration semiconductor substrate and by adjusting the thickness and the impurity concentration.

CONSTITUTION: On the first semiconductor layer 25 of the same conduction type on the low concentration semiconductor substrate 24, the source region 26 and the drain region 27 formed with different conduction type of high concentration impurity region are formed. Next, the channel region 28, gate insulation film 30, source electrode 31, and drain electrode 32 and gate electrode 33 are formed. In addition, by implanting boron, the second semiconductor layer 29 different in the conduction type from the substrate 24 is formed. In this manufacture process, the thickness and the impurity concentration of the first and second semiconductor layers 25 and 29 are constituted so that the depletion layer caused from the junction of the first and second semiconductor layers 25 and 29 causes pinch off in the second semiconductor layer 29 before the channel region 28 does not reaches the break down electric field at the drain voltage increase and the first semiconductor layer 25 is spread and reaches the low concentration semiconductor substrate 24 before the junctions of the first semiconductor layer 25 and the drain region 27 do not reach the breakdown electric field.

COPYRIGHT: (C)1979,JPO&Japio