JPS5466786A - Semiconductor integaated circuit device - Google Patents

Semiconductor integaated circuit device

Info

Publication number
JPS5466786A
JPS5466786A JP13375977A JP13375977A JPS5466786A JP S5466786 A JPS5466786 A JP S5466786A JP 13375977 A JP13375977 A JP 13375977A JP 13375977 A JP13375977 A JP 13375977A JP S5466786 A JPS5466786 A JP S5466786A
Authority
JP
Japan
Prior art keywords
type
region
regions
substrate
bundle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13375977A
Other languages
Japanese (ja)
Inventor
Junichi Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13375977A priority Critical patent/JPS5466786A/en
Publication of JPS5466786A publication Critical patent/JPS5466786A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make easy manufacture and to increase the reliability, by forming the element formation P<-> type region at the bundle for the N channel MOS transistor and NPN bipolar transistor in the one N type semiconductor substrate. CONSTITUTION:The SiO2 film 2 is coated on the N type Si substrate 1 and selective etching is made, and the P<+>type regions 3 and 4 for N channel MOS transistor and NPN bipolar transistor are formed at a bundle by injecting P type impurity ions to it. After that, in the region 3, the N<+> type source and drain regions 6 and 7 are formed by diffusion, it is enclosed with the P<+> type region, and the gate electrode 8 is coated via the SiO2 film between the regions 6 and 7. Further, in the region 4, the N<+> type emitter region 10, P<+> type base contact region 11 are formed by diffusion and the N<+> type collector contact region 12 is placed in the substrate 1.
JP13375977A 1977-11-08 1977-11-08 Semiconductor integaated circuit device Pending JPS5466786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13375977A JPS5466786A (en) 1977-11-08 1977-11-08 Semiconductor integaated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13375977A JPS5466786A (en) 1977-11-08 1977-11-08 Semiconductor integaated circuit device

Publications (1)

Publication Number Publication Date
JPS5466786A true JPS5466786A (en) 1979-05-29

Family

ID=15112274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13375977A Pending JPS5466786A (en) 1977-11-08 1977-11-08 Semiconductor integaated circuit device

Country Status (1)

Country Link
JP (1) JPS5466786A (en)

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