JPS5442977A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5442977A
JPS5442977A JP10937177A JP10937177A JPS5442977A JP S5442977 A JPS5442977 A JP S5442977A JP 10937177 A JP10937177 A JP 10937177A JP 10937177 A JP10937177 A JP 10937177A JP S5442977 A JPS5442977 A JP S5442977A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
manufacture
type
type lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10937177A
Other languages
Japanese (ja)
Inventor
Mitsuru Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10937177A priority Critical patent/JPS5442977A/en
Publication of JPS5442977A publication Critical patent/JPS5442977A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To facilitate and easy bonding for the dual-line type mold device by forming the first-type lead frame into flat form with the semiconductor device soldered to the island part of the first lead frame to be then pressed down until the second-type lead frame which is positioned in the opposite direction to the device bonding surface.
COPYRIGHT: (C)1979,JPO&Japio
JP10937177A 1977-09-09 1977-09-09 Manufacture of semiconductor device Pending JPS5442977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10937177A JPS5442977A (en) 1977-09-09 1977-09-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10937177A JPS5442977A (en) 1977-09-09 1977-09-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5442977A true JPS5442977A (en) 1979-04-05

Family

ID=14508533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10937177A Pending JPS5442977A (en) 1977-09-09 1977-09-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5442977A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147260A (en) * 1981-03-05 1982-09-11 Matsushita Electronics Corp Manufacture of resin-sealed semiconductor device and lead frame used therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147260A (en) * 1981-03-05 1982-09-11 Matsushita Electronics Corp Manufacture of resin-sealed semiconductor device and lead frame used therefor
JPS6220705B2 (en) * 1981-03-05 1987-05-08 Matsushita Electronics Corp

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