JPS5437294B2 - - Google Patents

Info

Publication number
JPS5437294B2
JPS5437294B2 JP13829875A JP13829875A JPS5437294B2 JP S5437294 B2 JPS5437294 B2 JP S5437294B2 JP 13829875 A JP13829875 A JP 13829875A JP 13829875 A JP13829875 A JP 13829875A JP S5437294 B2 JPS5437294 B2 JP S5437294B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13829875A
Other languages
Japanese (ja)
Other versions
JPS5180965A (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5180965A publication Critical patent/JPS5180965A/ja
Publication of JPS5437294B2 publication Critical patent/JPS5437294B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L25/00—Recording or indicating positions or identities of vehicles or trains or setting of track apparatus
    • B61L25/02—Indicating or recording positions or identities of vehicles or trains
    • B61L25/04—Indicating or recording train identities
    • B61L25/045—Indicating or recording train identities using reradiating tags
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP13829875A 1974-12-31 1975-11-19 Expired JPS5437294B2 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7443622A FR2296988A1 (fr) 1974-12-31 1974-12-31 Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique

Publications (2)

Publication Number Publication Date
JPS5180965A JPS5180965A (en:Method) 1976-07-15
JPS5437294B2 true JPS5437294B2 (en:Method) 1979-11-14

Family

ID=9146935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13829875A Expired JPS5437294B2 (en:Method) 1974-12-31 1975-11-19

Country Status (7)

Country Link
US (1) US4024629A (en:Method)
JP (1) JPS5437294B2 (en:Method)
CA (1) CA1043189A (en:Method)
DE (1) DE2558361C2 (en:Method)
FR (1) FR2296988A1 (en:Method)
GB (1) GB1487800A (en:Method)
IT (1) IT1049009B (en:Method)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
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JPS5328266A (en) * 1976-08-13 1978-03-16 Fujitsu Ltd Method of producing multilayer ceramic substrate
US4181387A (en) * 1978-06-21 1980-01-01 Western Electric Company, Inc. Interconnect sockets and assemblies
US4327247A (en) * 1978-10-02 1982-04-27 Shin-Kobe Electric Machinery Co., Ltd. Printed wiring board
US4191789A (en) * 1978-11-02 1980-03-04 Bell Telephone Laboratories, Incorporated Fabrication of bi-level circuits
JPS55138294A (en) * 1979-04-11 1980-10-28 Matsushita Electric Industrial Co Ltd Method of forming through hole connector
US4247981A (en) * 1979-06-18 1981-02-03 Western Electric Company, Inc. Methods of assembling interconnect members with printed circuit boards
US4301192A (en) * 1980-06-02 1981-11-17 Western Electric Co., Inc. Method for coating thru holes in a printed circuit substrate
US4383495A (en) * 1980-06-02 1983-05-17 Western Electric Company, Inc. Apparatus for coating surfaces of a substrate
US4369557A (en) * 1980-08-06 1983-01-25 Jan Vandebult Process for fabricating resonant tag circuit constructions
US4434134A (en) 1981-04-10 1984-02-28 International Business Machines Corporation Pinned ceramic substrate
FR2522459A1 (fr) * 1982-02-26 1983-09-02 Serras Paulet Edouard Circuit electrique imprime
DE3214097A1 (de) * 1982-04-16 1983-10-20 ITALTEL Società Italiana Telecomunicazioni S.p.A., 20149 Milano Verfahren, mit dem durchgehende loecher in elektrischen schaltungstraegern leitfaehig gemacht werden
JPS5923548A (ja) * 1982-07-30 1984-02-07 Fujitsu Ltd 半導体装置
DE3245458A1 (de) * 1982-12-08 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von durchkontaktierungen in dickschichttechnik
JPS6047495A (ja) * 1983-08-25 1985-03-14 株式会社日立製作所 セラミツク配線基板
JPS6084711A (ja) * 1983-10-14 1985-05-14 株式会社日立製作所 スル−ホ−ル充填用ペ−スト
GB2176942A (en) * 1983-11-10 1987-01-07 Donald Fort Sullivan Making printed circuit boards
FR2556503B1 (fr) * 1983-12-08 1986-12-12 Eurofarad Substrat d'interconnexion en alumine pour composant electronique
US4544577A (en) * 1984-04-26 1985-10-01 E. F. Johnson Company Process for metallization of dielectric substrate through holes
JPS6112054A (ja) * 1984-06-22 1986-01-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体パツケ−ジ製造方法
GB2188194A (en) * 1986-03-21 1987-09-23 Plessey Co Plc Carrier for high frequency integrated circuits
JPH0714105B2 (ja) * 1986-05-19 1995-02-15 日本電装株式会社 混成集積回路基板及びその製造方法
US4919970A (en) * 1986-09-15 1990-04-24 International Business Machines Corporation Solder deposition control
JPH0754872B2 (ja) * 1987-06-22 1995-06-07 古河電気工業株式会社 二層印刷回路シ−トの製造方法
US4802741A (en) * 1987-10-09 1989-02-07 Eastman Kodak Company In-depth electrode light valve array devices and improved fabrication method therefor
US4785989A (en) * 1987-11-16 1988-11-22 Gte Products Corporation Clad system for brazing to alumina
US5089881A (en) * 1988-11-03 1992-02-18 Micro Substrates, Inc. Fine-pitch chip carrier
JPH02152105A (ja) * 1988-12-01 1990-06-12 Fujitsu Ltd 導電材料およびその製造方法
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
US4985601A (en) * 1989-05-02 1991-01-15 Hagner George R Circuit boards with recessed traces
DE68912932T2 (de) * 1989-05-12 1994-08-11 Ibm Deutschland Glas-Keramik-Gegenstand und Verfahren zu dessen Herstellung.
JPH0480991A (ja) * 1990-07-24 1992-03-13 Cmk Corp プリント配線板の製造方法
US5283104A (en) * 1991-03-20 1994-02-01 International Business Machines Corporation Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
AT398876B (de) * 1991-10-31 1995-02-27 Philips Nv Zwei- oder mehrlagige leiterplatte
US5282312A (en) * 1991-12-31 1994-02-01 Tessera, Inc. Multi-layer circuit construction methods with customization features
US5367764A (en) * 1991-12-31 1994-11-29 Tessera, Inc. Method of making a multi-layer circuit assembly
JP2601128B2 (ja) * 1992-05-06 1997-04-16 松下電器産業株式会社 回路形成用基板の製造方法および回路形成用基板
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
JP3015621B2 (ja) * 1993-05-10 2000-03-06 松下電器産業株式会社 導体ペ−スト組成物
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US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5538582A (en) * 1994-09-14 1996-07-23 International Business Machines Corporation Method for forming cavities without using an insert
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5707476A (en) * 1995-09-19 1998-01-13 International Business Machines Corporation Method for forming multiple cavity products
US5707480A (en) * 1995-09-19 1998-01-13 International Business Machines Corporation Apparatus for forming multiple cavity products
US5746874A (en) * 1995-09-29 1998-05-05 International Business Machines Corporation Apparatus and method for forming cavity substrates using flexible preform insert
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5915756A (en) * 1996-08-22 1999-06-29 Altera Corporation Method to fill via holes between two conductive layers
US6622603B1 (en) * 1997-03-12 2003-09-23 International Business Machines Corporation Linear via punch
US6288344B1 (en) * 1999-08-20 2001-09-11 Cardiac Pacemakers, Inc. Integrated EMI shield utilizing a hybrid edge
US6352014B1 (en) * 1999-12-15 2002-03-05 International Business Machines Corporation Method for making punches using multi-layer ceramic technology
US6833615B2 (en) * 2000-12-29 2004-12-21 Intel Corporation Via-in-pad with off-center geometry
US6762380B2 (en) * 2001-06-29 2004-07-13 Icorp Membrane switch circuit layout and method for manufacturing
US20050108875A1 (en) * 2003-11-26 2005-05-26 Mathieu Gaetan L. Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
US7024763B2 (en) 2003-11-26 2006-04-11 Formfactor, Inc. Methods for making plated through holes usable as interconnection wire or probe attachments
WO2009029804A2 (en) * 2007-08-31 2009-03-05 Reactive Nanotechnologies, Inc. Method for low temperature bonding of electronic components
KR20110049247A (ko) * 2009-11-04 2011-05-12 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR101596098B1 (ko) * 2013-11-25 2016-02-29 주식회사 잉크테크 인쇄회로기판의 제조방법
US12020956B2 (en) 2019-05-03 2024-06-25 Therm-X Of California, Inc. High temperature aluminum nitride heater pedestal with multi-zone capability

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DE1188157B (de) * 1961-04-21 1965-03-04 Litton Industries Inc Verfahren zur Herstellung einer geschichteten, gedruckten Schaltungsplatte
FR1386216A (fr) * 1963-04-25 1965-01-22 Rca Corp Circuits électriques multicouches
US3838204A (en) * 1966-03-30 1974-09-24 Ibm Multilayer circuits
US3518756A (en) * 1967-08-22 1970-07-07 Ibm Fabrication of multilevel ceramic,microelectronic structures
US3770529A (en) * 1970-08-25 1973-11-06 Ibm Method of fabricating multilayer circuits
US3948706A (en) * 1973-12-13 1976-04-06 International Business Machines Corporation Method for metallizing ceramic green sheets

Also Published As

Publication number Publication date
IT1049009B (it) 1981-01-20
DE2558361C2 (de) 1982-04-08
FR2296988A1 (fr) 1976-07-30
GB1487800A (en) 1977-10-05
JPS5180965A (en:Method) 1976-07-15
DE2558361A1 (de) 1976-07-08
FR2296988B1 (en:Method) 1977-07-08
US4024629A (en) 1977-05-24
CA1043189A (en) 1978-11-28

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