JPS54137282A - Lateral transistor - Google Patents

Lateral transistor

Info

Publication number
JPS54137282A
JPS54137282A JP4558278A JP4558278A JPS54137282A JP S54137282 A JPS54137282 A JP S54137282A JP 4558278 A JP4558278 A JP 4558278A JP 4558278 A JP4558278 A JP 4558278A JP S54137282 A JPS54137282 A JP S54137282A
Authority
JP
Japan
Prior art keywords
region
type
transistor
base region
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4558278A
Other languages
Japanese (ja)
Inventor
Goro Mitarai
Hiroshi Saikai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4558278A priority Critical patent/JPS54137282A/en
Publication of JPS54137282A publication Critical patent/JPS54137282A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE: To reduce the extension of the depletion layer to avoid occurrence of the punch-through and thus to secure a high dielectric strength, high fFE and high fT respectively by giving an inclination to the impurity density so that the impurity density in the base region may be reduced from the emitter region toward the collector region.
CONSTITUTION: N-type layer 2 is epitaxial-grown on P-type Si substrate 1 and then separated at P-type region 3 into island region 21 and 22, and N-type region 8 is formed by diffusion within region 22 to be used later as the base region of the PNP transistor. In this case, the surface impurity density of region 8 is set higher than that of region 22 to be used as the base region featuring the density inclination. After this, P-type base region 4 of the NPN transistor, P-type base region 4 of the NPN transistor and N-type emitter region 5 are formed by diffusion at region 21, 22 and 8 respectively. And N-type emitter region 7 is provided within region 4 to form the desired complementary transistor of NPN and PNP.
COPYRIGHT: (C)1979,JPO&Japio
JP4558278A 1978-04-17 1978-04-17 Lateral transistor Pending JPS54137282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4558278A JPS54137282A (en) 1978-04-17 1978-04-17 Lateral transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4558278A JPS54137282A (en) 1978-04-17 1978-04-17 Lateral transistor

Publications (1)

Publication Number Publication Date
JPS54137282A true JPS54137282A (en) 1979-10-24

Family

ID=12723332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4558278A Pending JPS54137282A (en) 1978-04-17 1978-04-17 Lateral transistor

Country Status (1)

Country Link
JP (1) JPS54137282A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55137370U (en) * 1980-04-02 1980-09-30
CN1062234C (en) * 1994-01-20 2001-02-21 永田昭俊 Box pallet

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55137370U (en) * 1980-04-02 1980-09-30
CN1062234C (en) * 1994-01-20 2001-02-21 永田昭俊 Box pallet

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