JPS54121080A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54121080A
JPS54121080A JP2893978A JP2893978A JPS54121080A JP S54121080 A JPS54121080 A JP S54121080A JP 2893978 A JP2893978 A JP 2893978A JP 2893978 A JP2893978 A JP 2893978A JP S54121080 A JPS54121080 A JP S54121080A
Authority
JP
Japan
Prior art keywords
film
substrate
sio2
layer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2893978A
Other languages
Japanese (ja)
Inventor
Mitsuru Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2893978A priority Critical patent/JPS54121080A/en
Publication of JPS54121080A publication Critical patent/JPS54121080A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the capacity per unit plane by drilling plural units of holes on the substrate to secure the uneven longitudinal structure to the surface of the semiconductor substrate and then forming the information storage capacity part by providing the electrodes along the uneven surface and via the dielectric. CONSTITUTION:The lamination pattern of SiO2 film 202 and Si3N4 film 203 is formed on P-type Si substrate 201, and the oxidation is given using the lamination pattern as the mask to grow thick SiO2 film 204 at the both edge of substrate 201. The mask is then removed, and thin SiO2 film 205 is coated on exposed substrate 201. Then plural units of opening 206 are drilled, and concavity 207 is formed within 201 b etching. Film 205 is then removed to coat SiO2 film 208 newly from the inside of 207 through its surface, and N- or P-type poly-crystal Si layer 209 is grown on film 208 while filling 207. Then only the surface of layer 209 is oxidized to obtain SiO2, film 210, and layer 209 is etched after patterning given to be made to remain as electrode 211 and gate electrode 212 at the information memory capacity part.
JP2893978A 1978-03-13 1978-03-13 Semiconductor device Pending JPS54121080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2893978A JPS54121080A (en) 1978-03-13 1978-03-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2893978A JPS54121080A (en) 1978-03-13 1978-03-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54121080A true JPS54121080A (en) 1979-09-19

Family

ID=12262367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2893978A Pending JPS54121080A (en) 1978-03-13 1978-03-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54121080A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6037765A (en) * 1983-08-11 1985-02-27 Nec Corp Semiconductor device and manufacture thereof
JPS60113963A (en) * 1983-11-25 1985-06-20 Toshiba Corp Semiconductor memory device
JPS61160969A (en) * 1984-12-07 1986-07-21 テキサス　インスツルメンツ　インコ−ポレイテツド Memory cell and manufacture thereof
JPS61228660A (en) * 1985-04-02 1986-10-11 Mitsubishi Electric Corp Manufacture of semiconductor integrated circuit
JPS61276356A (en) * 1985-05-31 1986-12-06 Toshiba Corp Manufacture of semiconductor device
US4658283A (en) * 1984-07-25 1987-04-14 Hitachi, Ltd. Semiconductor integrated circuit device having a carrier trapping trench arrangement
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
JPS6323351A (en) * 1987-05-22 1988-01-30 Toshiba Corp Manufacture of semiconductor device
US4751557A (en) * 1982-03-10 1988-06-14 Hitachi, Ltd. Dram with FET stacked over capacitor
US4819054A (en) * 1982-09-29 1989-04-04 Hitachi, Ltd. Semiconductor IC with dual groove isolation
US5073515A (en) * 1989-09-29 1991-12-17 Siemens Aktiengesellschaft Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode
US5759903A (en) * 1991-08-14 1998-06-02 Siemens Aktiengesellschaft Circuit structure having at least one capacitor and a method for the manufacture thereof
WO2007069292A1 (en) * 2005-12-12 2007-06-21 Fujitsu Limited Semiconductor device and method of manufacturing the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751557A (en) * 1982-03-10 1988-06-14 Hitachi, Ltd. Dram with FET stacked over capacitor
US4819054A (en) * 1982-09-29 1989-04-04 Hitachi, Ltd. Semiconductor IC with dual groove isolation
JPS6037765A (en) * 1983-08-11 1985-02-27 Nec Corp Semiconductor device and manufacture thereof
JPH0367348B2 (en) * 1983-08-11 1991-10-22 Nippon Electric Co
JPS60113963A (en) * 1983-11-25 1985-06-20 Toshiba Corp Semiconductor memory device
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
US4658283A (en) * 1984-07-25 1987-04-14 Hitachi, Ltd. Semiconductor integrated circuit device having a carrier trapping trench arrangement
JPS61160969A (en) * 1984-12-07 1986-07-21 テキサス　インスツルメンツ　インコ−ポレイテツド Memory cell and manufacture thereof
JPS61228660A (en) * 1985-04-02 1986-10-11 Mitsubishi Electric Corp Manufacture of semiconductor integrated circuit
JPS61276356A (en) * 1985-05-31 1986-12-06 Toshiba Corp Manufacture of semiconductor device
JPH0618248B2 (en) * 1985-05-31 1994-03-09 株式会社東芝 Method for manufacturing semiconductor device
JPS6323351A (en) * 1987-05-22 1988-01-30 Toshiba Corp Manufacture of semiconductor device
JPH0441506B2 (en) * 1987-05-22 1992-07-08 Tokyo Shibaura Electric Co
US5073515A (en) * 1989-09-29 1991-12-17 Siemens Aktiengesellschaft Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode
US5759903A (en) * 1991-08-14 1998-06-02 Siemens Aktiengesellschaft Circuit structure having at least one capacitor and a method for the manufacture thereof
WO2007069292A1 (en) * 2005-12-12 2007-06-21 Fujitsu Limited Semiconductor device and method of manufacturing the same
US7928515B2 (en) 2005-12-12 2011-04-19 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the semiconductor device
JP4946870B2 (en) * 2005-12-12 2012-06-06 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof

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