JPS54105981A - Manufacture of mis-type semiconductor device - Google Patents

Manufacture of mis-type semiconductor device

Info

Publication number
JPS54105981A
JPS54105981A JP1274878A JP1274878A JPS54105981A JP S54105981 A JPS54105981 A JP S54105981A JP 1274878 A JP1274878 A JP 1274878A JP 1274878 A JP1274878 A JP 1274878A JP S54105981 A JPS54105981 A JP S54105981A
Authority
JP
Japan
Prior art keywords
film
layer
window
taper
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1274878A
Other languages
Japanese (ja)
Other versions
JPS6159541B2 (en
Inventor
Susumu Muramoto
Mamoru Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1274878A priority Critical patent/JPS54105981A/en
Publication of JPS54105981A publication Critical patent/JPS54105981A/en
Publication of JPS6159541B2 publication Critical patent/JPS6159541B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To increase the element density and thus to realize a miniature device by coating the thick insulator film on the semiconductor substrate with a large window drilled, forming the conductor layer which is covered with the insulator film to prevent the oxidation within the window with the taper provided at the circumference and then forming the diffusion layer using the taper as the mask.
CONSTITUTION: Thick SiO2 film 22 is coated on P-type Si substrae 21 with large window 23 drilled, and thin SiO2 film 25 is grown within the window through the heat treatment. Then lamination 33 composed of poly-crystal Si layer and Si3N4 film is formed only within window 23, and the taper is formed at the circumference through the oblique etching. Using this taper as the mask, the ion is injected through film 25 to form N-type region 36 and 37. After this, opening 44 and 45 are drilled to film 41 which increased its thickness with film 25 and the SiO2 film grown then, and the Si3N4 film of lamination 33 is removed to expose poly-crystal Si layer 27. Then conductor layer 48 is coated on the entire surface, and the selective etching is applied to leave conductor layer 49 on layer 27 and conductor layer 50 and 51 conducting to layer 49 on region 36 and 37 respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP1274878A 1978-02-07 1978-02-07 Manufacture of mis-type semiconductor device Granted JPS54105981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1274878A JPS54105981A (en) 1978-02-07 1978-02-07 Manufacture of mis-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1274878A JPS54105981A (en) 1978-02-07 1978-02-07 Manufacture of mis-type semiconductor device

Publications (2)

Publication Number Publication Date
JPS54105981A true JPS54105981A (en) 1979-08-20
JPS6159541B2 JPS6159541B2 (en) 1986-12-17

Family

ID=11814035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1274878A Granted JPS54105981A (en) 1978-02-07 1978-02-07 Manufacture of mis-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS54105981A (en)

Also Published As

Publication number Publication date
JPS6159541B2 (en) 1986-12-17

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