JPH0441506B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a semiconductor device with an improved structure of a MOS capacitor and an improved process for forming the MOS capacitor. It relates to a method for manufacturing semiconductor devices.

(Prior Art) In recent years, attempts have been made to reduce the dimensions of elements due to the demand for higher integration of semiconductor integrated circuits. For example, as shown in FIG. 2, a MOS capacitor for storing memory is formed by providing a capacitor electrode on the main surface of a semiconductor substrate 1 via an insulating film 2.
In the MOS dynamic RAM, it is conceivable to reduce the area of the capacitor electrode 3 to increase the degree of integration. However, in a MOS capacitor having such a structure, when the area of the capacitor electrode 3 is reduced, the amount of charge stored in the capacitor decreases, and there is a problem that a margin against noise and the like cannot be secured.

For this reason, it is necessary to reduce the thickness of the insulating film that makes up the MOS capacitor, and to use a Si ₃ N ₄ film with a high dielectric constant instead of the SiO ₂ film that is conventionally used as the insulating film that makes up the MOS capacitor. It is known to use. However, MOS capacitors with such a structure have problems with the withstand voltage and film quality (pinholes, etc.) of the insulating film.
There was a limit to reducing the area of the capacitor electrode.

Furthermore, as another method for reducing the area of a MOS capacitor while maintaining a predetermined capacity, a concave MOS capacitor (or V-type MOS capacitor) described below is known. That is, as shown in FIG. 3, this capacitor has a structure in which a V-shaped recess 4 is formed in the semiconductor substrate 1, and a capacitor electrode 3' is provided in the recess 4 with an insulating film 2' interposed therebetween. In such a concave capacitor, by changing the depth and shape of the concave portion 4, the effective area of the capacitor electrode 3' can be arbitrarily selected, and the withstand voltage of the insulating film,
The film quality can also be improved. However, the concave
In a MOS capacitor, self-alignment between the recess 4 and the capacitor electrode 3' is difficult, and it is necessary to provide an allowance (A) on both sides of the recess 4 in consideration of mask misalignment, which hinders the miniaturization of the MOS capacitor.
In turn, this has become a major problem in increasing the integration density of MOS dynamic RAM.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems, and includes a MOS capacitor with increased capacity and reduced area. M.O.S.
The connection reliability of the lead wiring to the capacitor electrode of the capacitor has been significantly improved, and the dielectric strength between the capacitor electrode and the gate electrode of the transistor has been improved, and the channel length according to the design dimensions can be achieved without taking unnecessary margins. It is an object of the present invention to provide a semiconductor device in which a gate electrode with good cut-off characteristics is formed, and a method for manufacturing such a semiconductor device through simple steps.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device according to the present invention includes: a silicon substrate of one conductivity type; a groove provided in a desired portion of the substrate; and an insulating film formed on the inner surface of the groove. a capacitor electrode made of polycrystalline silicon containing impurities embedded in the groove so that its upper side surface coincides with the inner surface of the insulating film; a MOS capacitor consisting of a wiring drawn out across the top of the groove; a thin oxide film formed on the surface of the silicon substrate; a capacitor electrode formed on the surface of a capacitor electrode made of polycrystalline silicon containing impurities in the groove; a thick oxide film; a gate electrode formed extending from a thin oxide film on the substrate surface to the thick oxide film; an impurity diffusion of a conductivity type opposite to that of the substrate formed on the substrate surface adjacent to the gate electrode; It is characterized by comprising: a layer;

A plurality of grooves are generally provided in the semiconductor substrate. It is also possible to provide grooves with different depths in the semiconductor substrate.

Examples of the insulating film include a SiO ₂ film and a Si ₃ N ₄ film. Such an insulating film needs to be formed thinly on the inner surface and bottom surface of the trench, rather than filling the entire inside of the trench.

Examples of the impurity-containing polycrystalline silicon include phosphorus-doped polycrystalline silicon, arsenic-doped polycrystalline silicon, and the like.

A method for manufacturing a semiconductor device according to the present invention includes: providing a groove in a desired portion of a silicon substrate of one conductivity type; forming an insulating film on the inner surface of the groove; depositing an electrode material made of polycrystalline silicon containing impurities; embedding the electrode material in at least the groove; after covering the region of the electrode material including a part above the groove with a mask material, the mask material and the electrode material on the region other than the groove are removed; By etching until the upper part of the groove is etched, a capacitor electrode whose upper side surface is self-aligned with the inner surface of the insulating film is formed in the groove, and the capacitor electrode is integrally connected to the upper part of the capacitor electrode and is connected to the upper part of the groove from the electrode. Step of fabricating a MOS capacitor by forming a wiring drawn out across the silicon substrate; applying thermal oxidation to form a thin oxide film on the surface of the silicon substrate, and forming a thin oxide film on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove. forming thick oxide films respectively; forming a gate electrode extending from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode; forming the gate electrode on the surface of the substrate adjacent to the gate electrode; The method is characterized by comprising: a step of forming an impurity diffusion layer of a conductivity type opposite to that of the substrate.

Next, a method for manufacturing a semiconductor device according to the present invention will be explained in detail.

First, a mask material, such as a resist pattern or an insulating film pattern, from which a portion where a groove is to be formed is removed is formed on a semiconductor substrate, and then a portion of the substrate exposed from the mask material is selectively etched to a desired depth to form a groove. In this case, if reactive ion beam etching or reactive ion etching is used as the etching means, a groove portion with substantially vertical side surfaces can be formed. However, the groove portion having reversely tapered side surfaces may be formed by other etching means.
One or more grooves may be formed in the element region, and MOS capacitors with different capacitances can be formed by changing the depth of the grooves.

Next, after removing the mask material, an insulating film is formed on the inner surface of the groove. In this case, it is necessary to form a thin insulating film on the side and bottom surfaces of the trench, without filling the entire inside of the trench with an insulating film. Methods for forming such an insulating film include, for example, a method of forming a thermal oxide film by thermal oxidation, and a method of forming a SiO ₂ film or a film by a CVD method.
A method of forming a Si ₃ N ₄ film or the like may be adopted.

Next, an electrode material made of polycrystalline silicon containing impurities is deposited to fill at least the groove. In this step, it is desirable that the electrode material be deposited to a thickness that is at least half the width of the opening of the groove. Continuing,
After covering a region of the electrode material including a portion above the groove with a mask material (for example, a resist pattern), etching is performed until the mask material and the electrode material on the region excluding the groove are removed. A capacitor electrode whose upper side surface is self-aligned with the inner surface of the insulating film is formed in the groove, and wiring is integrally connected to the upper part of the capacitor electrode and drawn out from the electrode across the upper part of the groove. A MOS capacitor is manufactured by forming a MOS capacitor.

Next, thermal oxidation is performed. In this step, since the substrate is made of silicon (single crystal silicon), a thin oxide film is formed on the surface of the substrate, and since the capacitor electrode in the groove is made of polycrystalline silicon containing impurities, a thick oxide film is formed on the surface of the electrode. An oxide film is formed. Subsequently, a gate electrode material is deposited on the entire surface and patterned to form a gate electrode extending from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode. Thereafter, an impurity diffusion layer having a conductivity type opposite to that of the substrate is formed on the surface of the substrate adjacent to the gate electrode by ion implantation, thermal diffusion, etc., thereby manufacturing a semiconductor device.

(Function) According to the semiconductor device according to the present invention, a groove portion provided in a desired portion of a silicon substrate of one conductivity type;
an insulating film formed on the inner surface of the groove; and an impurity-containing polycrystal that is embedded in the groove so that its upper side surface coincides with the inner surface of the insulating film, that is, embedded in the groove in a self-aligned manner. By constructing a MOS capacitor from a capacitor electrode made of silicon and a wiring integrally connected to the upper part of the capacitor electrode and drawn out from the electrode across the upper part of the groove, the capacitor electrode Since the area can be determined by the opening area of the trench, the area occupied by the MOS capacitor in the memory cell can be reduced. Moreover, the above
Since a MOS capacitor has a structure in which a capacitor electrode is embedded in a trench with an insulating film in between, it is possible to increase the capacitance even though the area occupied in a plan view is reduced. As a result, miniaturization and high integration of elements such as memory cells can be achieved. In addition,
By changing the depth of the groove, a MOS capacitor having the desired capacity can be realized.

Furthermore, by integrally connecting the wiring to the upper part of the capacitor electrode, the wiring is connected to the small-area capacitor electrode embedded in the groove in a separate process (usually connected through a contact hole). The connection reliability of the wiring to the capacitor electrode can be significantly improved.

Further, a thin oxide film is formed on the surface of the silicon substrate, a thick oxide film is formed on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove, and the capacitor electrode surface is coated from above the thin oxide film on the substrate surface. By providing the gate electrode extending over the thick oxide film, the dielectric breakdown voltage between the capacitor electrode and the gate electrode can be significantly improved.

Furthermore, by forming the capacitor electrode in the groove in a self-aligned manner, a gate electrode provided extending from a thin oxide film on the surface of the substrate to a thick oxide film on the surface of the capacitor electrode can be formed. It is possible to prevent the channel length (corresponding to the portion on the thin oxide film on the substrate surface) from varying from the designed dimension depending on the positional state of the capacitor electrode, and in particular, to prevent the channel length from becoming shorter than the designed dimension. As a result, it is no longer necessary to provide a margin for adjusting the channel length of the gate electrode to the designed dimension, so that the area occupied by the gate electrode in the memory cell can be reduced, and a highly integrated semiconductor device can be obtained.

Further, according to the method for manufacturing a semiconductor device according to the present invention, a groove is provided in a desired portion of a silicon substrate of one conductivity type, an insulating film is formed on the inner surface of the groove, and an electrode material made of polycrystalline silicon containing impurities is deposited. After embedding the electrode material in at least the groove and covering the electrode material region including a part above the groove with a mask material, the electrode material on the region excluding the mask material and the groove is By etching until it is removed, a capacitor electrode whose upper side surface is self-aligned with the inner surface of the insulating film can be formed in the groove, and the capacitor electrode is integrally connected to the upper part of the capacitor electrode. Wiring can be formed extending from the groove across the upper part of the groove. As a result, it is possible to manufacture a MOS capacitor in which the area of the capacitor electrode occupying a memory cell in plan view can be reduced, the capacity can be increased, and the connection reliability of the wiring to the capacitor electrode is significantly improved.

Furthermore, by forming the capacitor electrode from polycrystalline silicon containing impurities, a thin oxide film is formed on the surface of the silicon substrate in a thermal oxidation process after the formation of the MOS capacitor, and the polycrystalline silicon containing impurities is formed in the groove. A thick oxide film can be formed on the surface of each capacitor electrode. the result,
By forming the gate electrode extending from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode, the oxide film is sufficiently thick between the capacitor electrode and the gate electrode. can be interposed, the dielectric breakdown voltage between them can be significantly improved, and the capacitance between them can be reduced to achieve high-speed operation of the memory cell.

Furthermore, in the step of extending the gate electrode from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode by forming the capacitor electrode in the groove in a self-aligned manner,
The channel length of the gate electrode (corresponding to the portion on the thin oxide film on the surface of the substrate) varies from the design dimension depending on the positional state of the capacitor electrode.
In particular, it is possible to avoid the channel length becoming shorter than the design dimension. As a result, when forming the gate electrode, it is no longer necessary to take a margin for adjusting the channel length to the designed dimension, so the area occupied by the gate electrode in the memory cell can be reduced, and a highly integrated semiconductor device can be manufactured.

(Embodiments of the Invention) Hereinafter, an example in which the present invention is applied to a MOS dynamic RAM will be described in detail with reference to the manufacturing method shown in FIGS. 1a to 1i.

First, as shown in FIG. 1A, a field oxide film 12 for element isolation was formed on a p-type silicon substrate 11 by selective oxidation. Subsequently, a part of the element region of the silicon substrate 11 is etched by photolithography using sputter etching, with a width of 1 μm and a length of 3 μm.
A groove 13 with a depth of 2.5 μm was formed (as shown in FIG. 1B).

Next, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000°C. At this time, a thermal oxide film 14 having a thickness of 300 mm was grown on the entire surface of the silicon substrate 11 including the groove portion 13, as shown in FIG. Next, a 6000 mm thick phosphorus-doped polycrystalline silicon film was deposited using the CVD method. At this time, as shown in Figure d, a phosphorus-doped polycrystalline silicon film 15 was deposited on the silicon substrate 11, and the opening of the groove 13 having a width of 1 μm was filled with the same polycrystalline silicon.

Next, a resist pattern 16 was formed in a region of the phosphorus-doped polycrystalline silicon film 15 including a part of the groove 13 (as shown in FIG. 3E). Subsequently, this resist pattern 16 and the thermal oxide film 14 other than the groove portion 13 are
The entire surface is etched with a hydrofluoric acid-based etching solution until the phosphorus-doped polycrystalline silicon is exposed, and the phosphorus-doped polycrystalline silicon is left in the groove 13 to form a capacitor electrode 17 in the groove 13. connected from the electrode 17 to the groove 13
A wiring 18 was formed extending across a part of the thermal oxide film 14 on the inner surface (as shown in FIG. 1F). At this time, the capacitor electrode 17 is buried in the trench 13 with its upper side surface aligned with the inner surface of the thermal oxide film 14 which is the capacitor insulating film in the trench 13 .

Next, the thermal oxide film 1 is formed on the main surface of the silicon substrate 11 using the capacitor electrode 17 and the wiring 18 as a mask.
An insulating film 19 of the capacitor was formed using a thermal oxide film that was left in the trench 13 by selectively etching away four portions. Subsequently, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000°C. At this time, as shown in FIG. A thick oxide film 21 of about 1200 mm was grown.

Next, a polycrystalline silicon film was deposited and patterned to form a gate electrode 22 (see h in the figure).
(Illustrated). Subsequently, the thermal oxide film 20 is selectively etched using the gate electrode 22 as a mask to form a gate insulating film 23, and then arsenic is etched onto the silicon substrate 11.
n ⁺ diffusion layer 24 which diffuses into the digital line and becomes a digital line.
was formed. Thereafter, a low-temperature oxide film 25 was deposited on the entire surface by the CVD method, a contact hole 26 was opened, and an A wiring 27 was formed to manufacture a MOS dynamic RAM (as shown in the figure i).

The MOS dynamic RAM of the present invention, as shown in FIG. A capacitor electrode 17 embedded so as to match the inner surface of the insulating film 19 and this capacitor electrode 1
The wiring 1 is integrally connected to the upper part of the groove 13 and is drawn out from the electrode 17 across the upper part of the groove 13.
8, a thin oxide film 20 is formed on the surface of the silicon substrate 11, a thick oxide film 21 is formed on the surface of the capacitor electrode 17 made of phosphorus-doped polycrystalline silicon, and a gate electrode 22 is formed. A layer is formed extending from the thin oxide film 20 on the surface of the substrate 11 to the thick oxide film 21 on the surface of the capacitor electrode 17, and is further formed on the surface of the substrate 11 adjacent to the gate electrode 22 with a conductivity type opposite to that of the substrate 12. It has a structure in which a certain n ⁺ diffusion layer 24 is formed. As a result, the area occupied by the capacitor electrode 17 in plan with respect to the silicon substrate 11 can be reduced, so that miniaturization and high integration of memory cell elements can be achieved. Also,
In the MOS capacitor, the groove portion 13 has a width of 1 μm and a depth.
Since the surrounding area of 2.5 μm is 23 μm ² and the thickness of the insulating film 19 is 300 μm, a sufficiently large capacitance of about 27 fF can be obtained. Furthermore, since the wiring 18 is integrally connected to the upper part of the capacitor electrode 17, the connection reliability of the wiring 18 can be significantly improved.

Further, by providing the gate electrode 22 extending from the thin oxide film 20 on the surface of the silicon substrate 11 to the thick oxide film 21 on the surface of the capacitor electrode 17, the gap between the capacitor electrode 17 and the gate electrode 22 is increased. can significantly improve the dielectric strength of the

Further, the capacitor electrode 17 is connected to the groove portion 1.
The channel length of the gate electrode 22 extended from the thin oxide film 20 on the surface of the substrate 11 to the thick oxide film 21 on the surface of the capacitor electrode 17 is (corresponding to the portion on the thin oxide film 20 on the surface of the substrate 11) varies from the designed dimension depending on the positional state of the capacitor electrode 17. In particular, it is possible to avoid the channel length from becoming shorter than the designed dimension. As a result, it is no longer necessary to provide a margin for adjusting the channel length of the gate electrode 22 to the designed dimension, so that the area occupied by the gate electrode in the memory cell can be reduced, and a highly integrated MOS dynamic RAM can be obtained.

On the other hand, according to the method of the present invention, after the resist pattern 16 is formed in the region of the doped polycrystalline silicon film 15 including a part above the groove 13, the thermal oxide film 14 other than the resist pattern 16 and the groove 13 is The entire surface is etched with a hydrofluoric acid-based etching solution until it is exposed, thereby forming a capacitor electrode 17 in the groove 13 whose upper side surface is self-aligned with the inner surface of the thermal oxide film 14 in the groove 13.
By forming the wiring 18 which is integrally connected to the upper part of the electrode 7 and drawn out from the electrode 17 across a part of the thermal oxide film 14, the capacitance can be increased and the area can be reduced as described above. It is possible to easily manufacture a MOS dynamic RAM which is equipped with a downsized MOS capacitor and which has significantly improved connection reliability of the lead wiring to the capacitor electrode of the MOS capacitor.

Further, by forming the capacitor electrode 17 from phosphorus-doped polycrystalline silicon, a thin oxide film 20 is formed on the surface of the silicon substrate 11 in the thermal oxidation process after forming the MOS capacitor, and
A thick oxide film 21 can be formed on the surface of the capacitor electrode 17 made of phosphorus-doped polycrystalline silicon. As a result, the gate electrode 22 is connected to the substrate 11.
By forming the oxide film extending from the thin oxide film 20 on the surface to the thick oxide film 21 on the surface of the capacitor electrode 17, the oxide film is sufficiently thick between the capacitor electrode 17 and the gate electrode 22. 2
1 can be interposed, the dielectric strength between them can be significantly improved, and the capacitance between them can be reduced to achieve high-speed operation of the memory cell.

[Effects of the Invention] As described in detail above, the present invention has a MOS capacitor with increased capacity and reduced area, and also provides reliable connection of the lead wiring to the capacitor electrode of the MOS capacitor. Furthermore, the dielectric strength between the capacitor electrode and the gate electrode of the transistor is improved, and it is possible to form a gate electrode with good cut-off characteristics and a channel length as designed without taking unnecessary margins. Furthermore, it is possible to provide a highly reliable and highly integrated semiconductor device, as well as a method for manufacturing such a semiconductor device through simple steps.

[Brief explanation of drawings]

Fig. 1 a to i are MOS in the embodiment of the present invention.
2 is a sectional view showing the manufacturing process of a dynamic RAM, FIG. 2 is a sectional view showing a conventional MOS capacitor, and FIG. 3 is a sectional view showing a concave MOS capacitor. DESCRIPTION OF SYMBOLS 11...P-type silicon substrate, 12...Field oxide film, 13...Groove, 16...Resist pattern, 17...Capacitor electrode, 18...Outgoing wiring, 19...Capacitor insulating film, 22...Gate Electrode, 23...gate oxide film, 24...n ⁺
Diffusion layer (digital line), 27...wiring.

Claims (1)

[Claims] 1. A silicon substrate of one conductivity type; a groove provided in a desired portion of the substrate, an insulating film formed on the inner surface of the groove, and an upper side surface inside the groove formed on the inner surface of the insulating film. a capacitor electrode made of polycrystalline silicon containing impurities embedded in a manner consistent with the capacitor electrode, and a wiring integrally connected to the upper part of the capacitor electrode and drawn out from the electrode across the upper part of the groove part. MOS capacitor; a thin oxide film formed on the surface of the silicon substrate; a thick oxide film formed on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove; A semiconductor comprising: a gate electrode extending and formed on a thick oxide film on an electrode surface; an impurity diffusion layer of a conductivity type opposite to that of the substrate formed on a surface of the substrate adjacent to the gate electrode; Device. 2. Providing a groove in a desired portion of a silicon substrate of one conductivity type; Forming an insulating film on the inner surface of the groove; Depositing an electrode material made of polycrystalline silicon containing impurities so that the electrode material is at least inside the groove. Filling step: After covering the area of the electrode material including a part above the groove with a mask material, the inside of the groove is etched until the mask material and the electrode material on the area excluding the groove are removed. forming a capacitor electrode whose upper side surface is self-aligned with the inner surface of the insulating film, and forming a wiring integrally connected to the upper part of the capacitor electrode and drawn out from the electrode across the upper part of the groove. a step of forming a thin oxide film on the surface of the silicon substrate by thermal oxidation, and a thick oxide film on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove; forming an electrode extending from a thin oxide film on the surface of the substrate to a thick oxide film on the surface of the capacitor electrode; forming an impurity diffusion layer of a conductivity type opposite to that of the substrate on the surface of the substrate adjacent to the gate electrode; A method of manufacturing a semiconductor device, comprising: forming a semiconductor device.