JPH081931B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an improved structure of a MOS capacitor and a method of manufacturing a semiconductor device having an improved process of forming a MOS capacitor.

[0002]

2. Description of the Related Art In recent years, attempts have been made to reduce the size of devices due to the demand for higher integration of semiconductor integrated circuits. For example, as shown in FIG. 9, the insulating film 2 is formed on the main surface of the semiconductor substrate 1.
It is conceivable to reduce the area of the capacitor electrode 3 and increase the degree of integration in a MOS dynamic RAM in which a MOS capacitor for storing memory is formed by providing a capacitor electrode via the. However, in the MOS capacitor having such a structure, if the area of the capacitor electrode 3 is reduced, the amount of electric charge stored in the capacitor decreases, and there is a problem that a margin for noise and the like cannot be secured.

From the above, (1) the thickness of the insulating film forming the MOS capacitor should be reduced, and (2) M
Si ₃ N, which has a large dielectric constant, is used instead of the SiO ₂ film that has been conventionally used as an insulating film that constitutes an OS capacitor.
It is known to use _four membranes or the like. However, the MOS capacitor having such a structure has problems with respect to the withstand voltage of the insulating film and the film quality (pinhole, etc.), and there is a limit to reducing the area of the capacitor electrode.

A concave MOS capacitor (or V-type MOS capacitor) described below is known as another method for reducing the area of a MOS capacitor while maintaining a predetermined capacity. That is, this capacitor forms a V-shaped recess 4 in the semiconductor substrate 1 as shown in FIG.
In this structure, a capacitor electrode 3'is provided via an insulating film 2 '. In such a concave capacitor, the effective area of the capacitor electrode 3'can be arbitrarily selected by changing the depth and shape of the concave portion 4, and the breakdown voltage of the insulating film,
The film quality can be improved. However, the concave MOS
In a capacitor, it is difficult to form the recess 4 and the capacitor electrode 3'in a self-aligned manner, and it is necessary to provide a margin (A) on both sides of the recess 4 in consideration of mask misalignment.
This has hindered the reduction of the size of the capacitor, and has been a serious problem for the high integration of the MOS dynamic RAM.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a MOS capacitor having an increased capacitance and a reduced area,
Further, the reliability of connection of the lead-out wiring to the capacitor electrode of the MOS capacitor is remarkably improved, and further, the storage device and the impurity diffusion layer can be satisfactorily connected on the groove side of the MOS capacitor, and It is intended to provide a method capable of manufacturing a semiconductor device by a simple process.

[0006]

A semiconductor device according to the present invention is a semiconductor substrate of one conductivity type; a groove portion provided in a desired portion of the substrate, an insulating film formed on an inner surface of the groove portion, and an inside of the groove portion. A capacitor electrode embedded so that an upper side surface thereof coincides with the inner side surface of the insulating film, and a wiring integrally connected to the upper portion of the capacitor electrode and extending from the electrode across the upper portion of the groove. A MOS capacitor; a gate electrode formed on a part of the semiconductor substrate apart from the end of the capacitor electrode except an extension of the wiring via an oxide film; a position between the gate electrode and the capacitor electrode An impurity diffusion layer having a conductivity type opposite to that of the substrate formed on the substrate surface and on the substrate surface adjacent to the gate electrode on a side different from the capacitor electrode side, respectively; Comprising a said impurity diffusion layer and the storage layer of the capacitor
Are connected on the side surface of the groove of the MOS capacitor.
It is characterized in that that.

A plurality of the groove portions are generally provided on the semiconductor substrate. It is also possible to provide the semiconductor substrate with grooves having different depths.

Examples of the insulating film include a SiO ₂ film and a Si ₃ N ₄ film. Such an insulating film needs to be thinly formed on the side surface and the bottom surface of the groove without filling the entire groove.

The material of the capacitor electrode and the wiring integrally connected to it is, for example, polycrystalline silicon,
Examples thereof include polycrystalline silicon doped with impurities such as phosphorus and arsenic, refractory metals such as molybdenum, tungsten, titanium and platinum, refractory metal silicides such as molybdenum silicide, tungsten silicide and platinum silicide. .

A method of manufacturing a semiconductor device according to the present invention is
Providing a groove in a desired portion of the semiconductor substrate; forming an insulating film on the inner surface of the groove; depositing an electrode material and filling at least the groove with an electrode material; After covering the area with a mask material, etching is performed until the electrode material on the area excluding the mask material and the groove is removed, so that the upper side surface in the groove is self-aligned with the inner surface of the insulating film. Forming an electrode and forming a wiring integrally connected to the upper part of the capacitor electrode and extending from the electrode across the upper part of the groove to form a MOS capacitor; a thin oxide film on the surface of the semiconductor substrate. And then forming a gate electrode on the oxide film upper portion apart from the end portion of the capacitor electrode except for the extended portion of the wiring on the semiconductor substrate; An impurity diffusion layer having a conductivity type opposite to that of the substrate is formed on the substrate surface located between the gate electrode and the capacitor electrode and on the substrate surface adjacent to the gate electrode on a side different from the capacitor electrode side. By doing
The capacitance is formed on the side surface of the groove of the MOS capacitor.
A step of connecting the storage layer of the battery and the impurity diffusion layer ;

Next, the method of manufacturing the semiconductor device of the present invention will be described in detail.

First, after forming a mask material, for example, a resist pattern or an insulating film pattern, from which a groove portion is to be formed on a semiconductor substrate, the substrate portion exposed from the mask material is selectively etched to a desired depth to form the groove portion. Form. In this case, if reactive ion beam etching or reactive ion etching is used as the etching means, it is possible to form a groove portion whose side surface is substantially vertical. However, the groove having the reverse tapered side surface may be formed by other etching means. The number of grooves may be one or two or more in the element region, and in particular, MOS capacitors having different capacities can be formed by changing the depth of the grooves.

After removing the mask material, an insulating film is formed on the inner surface of the groove. In this case, it is necessary to form a thin insulating film on the side surface and the bottom surface of the groove without filling the entire inside of the groove with the insulating film. As a method of forming such an insulating film, for example, a method of forming a thermal oxide film by thermal oxidation, a method of forming a SiO ₂ film or a Si ₃ N ₄ film by a CVD method, and the like can be adopted.

Next, an electrode material (for example, polycrystalline silicon, polycrystalline silicon doped with impurities such as phosphorus and arsenic) is deposited to fill at least the groove with the electrode material. In this step, it is desirable that the electrode material is deposited so as to have a thickness that is at least half the width of the opening of the groove. Subsequently, a region of the electrode material including a part on the groove is masked (for example, a resist pattern).
And then etching until the electrode material on the region excluding the mask material and the groove portion is removed to form a capacitor electrode in which the upper side surface is self-aligned with the inner side surface of the insulating film. At the same time, a wiring connected to the upper part of the capacitor electrode and extending from the electrode across the upper part of the groove is formed to manufacture a MOS capacitor.

Next, thermal oxidation is performed to form a thin oxide film on the surface of the substrate. Subsequently, a gate electrode material is deposited on the entire surface and patterned to form a gate electrode on the oxide film portion apart from the end portion of the capacitor electrode except the extended portion of the wiring. Then, the substrate surface located between the gate electrode and the capacitor electrode,
And a semiconductor device is manufactured by performing ion implantation, thermal diffusion, etc. on the surface of the substrate adjacent to the gate electrode on the side different from the capacitor electrode side to form an impurity diffusion layer having a conductivity type opposite to that of the substrate. .

[0016]

According to the semiconductor device of the present invention, the groove portion provided in a desired portion of the semiconductor substrate of one conductivity type, the insulating film formed on the inner surface of the groove portion, and the upper side surface in the groove portion are the insulating film. A capacitor electrode embedded so as to match the inner side surface of the capacitor, that is, embedded in a self-aligned manner in the groove portion excluding an extending portion of a wiring described later, and integrally connected to an upper portion of the capacitor electrode, Since the area of the capacitor electrode can be determined by the opening area of the groove by forming the MOS capacitor from the wiring extending from the electrode across the upper portion of the groove, the area of the capacitor electrode can be occupied in the memory cell of the MOS capacitor in a plane. The area can be reduced. Moreover, since the MOS capacitor has a structure in which the capacitor electrode is embedded in the groove with the insulating film interposed therebetween, the capacitance can be increased even though the area occupied in the plane is reduced. As a result, miniaturization and high integration of elements such as memory cells can be achieved. By changing the depth of the groove, a MOS capacitor having a desired capacitance can be realized.

Further, when the wiring is integrally connected to the upper part of the capacitor electrode to connect the wiring to the capacitor electrode having a small area buried in the groove portion in another step (usually through a contact hole). In comparison, the connection reliability of the wiring with respect to the capacitor electrode can be significantly improved.

Further, by forming the capacitor electrode portion located on the gate electrode side in the groove portion in a self-aligned manner, the storage layer of the capacitor and the impurity diffusion layer are favorably formed on the side surface of the groove portion of the MOS capacitor. Can be connected. That is, when the capacitor electrode is not formed in self-alignment with the groove and extends to the substrate surface on the gate electrode side, the storage layer and the diffusion layer of the MOS capacitor are electrically separated at the extended portion. To be done. As a result, it is necessary to form another diffusion layer for connecting the storage layer and the diffusion layer before forming the capacitor electrode, which hinders an increase in the number of steps and a high degree of integration.

Further, according to the method of the present invention, the highly reliable and highly integrated semiconductor device described above can be manufactured by an extremely simple process.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which the present invention is applied to a MOS dynamic RAM will be described below in detail with the manufacturing method shown in FIGS.

First, as shown in FIG. 1), a field oxide film 12 for element isolation was formed on a p-type silicon substrate 11 by a selective oxidation method. Subsequently, a groove 13 having a width of 1 μm, a length of 3 μm and a depth of 2.5 μm was formed in a part of the element region of the silicon substrate 11 by a photo-etching method using sputter etching (see FIG. 2).

Next, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000.degree. At this time, as shown in FIG. 3, a thermal oxide film 14 having a thickness of 300 Å (hereinafter referred to as A) was grown on the entire surface of the silicon substrate 11 including the groove 13. Subsequently, a phosphorus-doped polycrystalline silicon film having a thickness of 6000 A was deposited by the CVD method. At this time, as shown in FIG. 4, a phosphorus-doped polycrystalline silicon film 15 is formed on the silicon substrate 11.
Was deposited, and the opening of the groove 13 having a width of 1 μm was filled with the same polycrystalline silicon.

Then, a resist pattern 16 was formed in the region of the phosphorus-doped polycrystalline silicon film 15 including a part of the groove portion 13 (shown in FIG. 5). Next, the thermal oxide film 14 excluding the thermal oxide film 14 in the resist pattern 16 and the groove portion 13
Is entirely exposed with a hydrofluoric acid-based etching solution until the exposed portions are exposed to leave phosphorus-doped polycrystalline silicon in the groove 13 to form a capacitor electrode 17, and the capacitor electrode 17 is integrally connected to the upper portion of the capacitor electrode 17. A wiring 18 was formed extending from the electrode 17 across the upper portion of the groove 13 (shown in FIG. 6). At this time, the capacitor electrode 17 is in a state where the upper side surface of the capacitor electrode 17 is flush with the inner side surface of the thermal oxide film 14 in a region other than the extending portion of the wiring 18 and is embedded in the groove portion 13.

Next, after removing the thermal oxide film 14 on the main surface of the silicon substrate 11 by etching, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000.degree. At this time, as shown in FIG. 7, a thickness of 750A is formed on the exposed main surface of the silicon substrate 11.
The thermal oxide film 19 is formed on the exposed surface of the capacitor electrode 17 and the wiring 18 made of phosphorus-doped polycrystalline silicon to a thickness of 12
A thick oxide film 20 of about 00 A was grown on each.

Then, after depositing a polycrystalline silicon film,
A gate electrode 21 was formed on the oxide film 19 apart from the end of the capacitor electrode 17 except for the extension of the wiring 18 by patterning. Subsequently, the exposed portions of the thermal oxide films 19 and 20 exposed by using the gate electrode 21 as a mask are removed by etching, and then arsenic is diffused into the silicon substrate 11 by using the gate electrode 21 as a mask to form the n ⁺ diffusion layer 2
By forming 2 and 23, MOS dynamic RA
M was produced (shown in FIG. 8). In addition, the n ⁺ diffusion layer 2
2 and 23, arsenic ions are removed from the thermal oxide film 1 without etching away the thermal oxide films 19 and 20.
An n ⁺ diffusion layer may be formed by implanting 9 through 9 into the substrate 11.

Therefore, the MOS dynamic R of the present invention
As shown in FIG. 8, the AM has a groove portion 13 formed in a desired portion of the silicon substrate 11, a thermal oxide film 14 (insulating film of a capacitor) formed on the inner surface of the groove portion 13, and the thermal oxide film 14 formed therein. The upper side surface of the thermal oxide film 1 is formed in the groove 13.
4. A MOS comprising a capacitor electrode 17 embedded so as to match the inner surface of 4 and a wiring 18 integrally connected to the upper portion of the capacitor electrode 17 and extending from the electrode 17 across the upper portion of the groove 13. With a capacitor,
The gate electrode 21 is formed on the oxide film 19 on the surface of the silicon substrate 11 away from the end of the capacitor electrode 17.
And the surface of the substrate 11 located between the gate electrode 21 and the capacitor electrode 17, and the gate electrode 21 on a side different from the capacitor electrode 17 side.
N ⁺ diffusion layers 22 and 23 on the surface of the substrate 11 adjacent to
It has a structure in which each is formed.

According to this structure, the area occupied by the capacitor electrode 17 in a plane with respect to the silicon substrate 11 can be reduced, so that the element of the memory cell can be miniaturized,
High integration can be achieved. Further, in the MOS capacitor, the width of the groove 13 is 1 μm, the depth is 2.5 μm, the peripheral area is 23 μm ² , and the thickness of the thermal oxide film 14 is 300 μm.
Since it is A, the capacity can be set to a sufficiently large capacity of about 27 fF. Further, since the wiring 18 is integrally connected to the upper portion of the capacitor electrode 17, the connection reliability of the wiring 18 can be significantly improved.

Further, the capacitor electrode 17 portion located on the gate electrode 21 side is formed in the groove 13 in a self-aligned manner, so that the storage layer of the capacitor and the n ⁺ diffusion are formed on the side surface of the groove 13 of the MOS capacitor. Layer 2
2 can be connected well.

On the other hand, according to the method of the present invention, after forming the resist pattern 16 in the region of the arsenic-doped polycrystalline silicon film 15 including a part on the groove portion 13, the resist pattern 1 is formed.
6 and the entire surface of the thermal oxide film 14 other than the groove 13 are exposed with a hydrofluoric acid-based etching solution, and the upper side surface of the groove 13 is self-aligned with the inner surface of the thermal oxide film 14 of the groove 13. The electrode 17 is formed and is integrally connected to the upper portion of the capacitor electrode 17.
By forming a wiring 18 extending from above to the upper part of the groove portion 13, a MOS capacitor having an increased capacity and a reduced area as described above is provided, and
It is possible to easily manufacture the MOS dynamic RAM in which the connection reliability of the lead wiring to the capacitor electrode of the OS capacitor is remarkably improved.

After depositing a polycrystalline silicon film, patterning is performed to form a gate electrode 21 on the oxide film 19 apart from the end of the capacitor electrode 17 excluding the extending portion of the wiring 18. Using the gate electrode 21 as a mask, arsenic is diffused into the silicon substrate 11 to form the n ⁺ diffusion layer 2
2 and 23 are formed, the storage layer of the capacitor and the n ⁺
The diffusion layer 22 can be satisfactorily connected.

[0031]

As described above in detail, according to the present invention, there is provided a MOS capacitor having an increased capacity and a reduced area, and the connection reliability of the lead wiring to the capacitor electrode of the MOS capacitor. Is dramatically improved, and M
A semiconductor device having high reliability and a high degree of integration, in which the storage layer and the impurity diffusion layer can be satisfactorily connected on the groove side of the OS capacitor, and a method capable of manufacturing such a semiconductor device by a simple process. Can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 9 is a cross-sectional view showing a conventional MOS capacitor.

FIG. 10 is a sectional view showing a concave MOS capacitor.

[Explanation of symbols]

11 ... p-type silicon substrate, 12 ... field oxide film, 1
3 ... Groove part, 16 ... Resist pattern, 17 ... Capacitor electrode, 18 ... Lead wiring, 21 ... Gate electrode, 22, 2
3 ... n ⁺ diffusion layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 27/108

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type; a groove portion provided in a desired portion of the substrate; and an inner surface of the groove portion.
And the insulating film formed on the upper side surface inside the groove.
Capacitor embedded to match the inner surface of the border film
The electrode and the capacitor electrode integrally connected to the top.
From the electrode across the top of the groove
A MOS capacitor comprising a wiring; the cap excluding an extending portion of the wiring on the semiconductor substrate
Formed via an oxide film on the part apart from the end of the electrode
A gate electrode; before being located between the gate electrode and the capacitor electrode
The surface of the substrate and the side different from the side of the capacitor electrode.
Formed on the surface of the substrate adjacent to the gate electrode, respectively.
An impurity diffusion layer having a conductivity type opposite to that of the formed substrate;, The storage layer and the impurity diffusion layer of the capacitor are
Connected at the groove side surface of the MOS capacitor Special
Semiconductor device to collect. 2. A step of providing a groove in a desired portion of a semiconductor substrate; a step of forming an insulating film on the inner surface of the groove; a step of depositing an electrode material and filling at least the groove with an electrode material; After covering a region of the electrode material including a mask material with a mask material, etching is performed until the electrode material on the region excluding the mask material and the groove portion is removed, so that the upper side surface in the groove portion is the inner surface of the insulating film. Forming a self-aligned capacitor electrode, forming a wiring integrally connected to the upper part of the capacitor electrode and extending from the electrode across the upper part of the groove to manufacture a MOS capacitor; the semiconductor substrate After forming a thin oxide film on the surface, a gate electrode is formed on the oxide film upper part apart from the end part of the capacitor electrode except for the extension part of the wiring on the semiconductor substrate. An impurity diffusion of a conductivity type opposite to that of the substrate on the surface of the substrate located between the gate electrode and the capacitor electrode, and on the surface of the substrate adjacent to the gate electrode on a side different from the side of the capacitor electrode. By forming each layer
Wherein the groove side surface of the MOS calibration Pashita Capacity
A step of connecting a storage layer of the semiconductor device and the impurity diffusion layer ;