JPH0441507B2 - - Google Patents
Info
- Publication number
- JPH0441507B2 JPH0441507B2 JP62125604A JP12560487A JPH0441507B2 JP H0441507 B2 JPH0441507 B2 JP H0441507B2 JP 62125604 A JP62125604 A JP 62125604A JP 12560487 A JP12560487 A JP 12560487A JP H0441507 B2 JPH0441507 B2 JP H0441507B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- oxide film
- capacitor
- electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 78
- 239000000758 substrate Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000007772 electrode material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体装置の製造方法に関し、特に
MOSキヤパシタの形成工程を改良した半導体装
置の製造方法に係わる。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device that improves the process of forming a MOS capacitor.
（従来の技術）
近年、半導体集積回路の高集積化の要請から素
子の寸法を縮小させることが試みられている。例
えば第１図に示すように半導体基板１の主面に絶
縁膜２を介してキヤパシタ電極を設けることより
記憶を蓄えるためのMOSキヤパシタを形成した
MOSダイラミツクRAMにおいて、キヤパシタ電
極３の面積を縮小して集積度を高めることが考え
られる。しかしながら、かかる構造のMOSキヤ
パシタではキヤパシタ電極３の面積を小さくする
と、キヤパシタに蓄えられる電荷の量が少なくな
り、ノイズ等に対するマージンがとれなくなる問
題がある。(Prior Art) In recent years, attempts have been made to reduce the dimensions of elements due to the demand for higher integration of semiconductor integrated circuits. For example, as shown in FIG. 1, a MOS capacitor for storing memory is formed by providing a capacitor electrode on the main surface of a semiconductor substrate 1 via an insulating film 2.
In the MOS dynamic RAM, it is conceivable to reduce the area of the capacitor electrode 3 to increase the degree of integration. However, in a MOS capacitor having such a structure, when the area of the capacitor electrode 3 is reduced, the amount of charge stored in the capacitor decreases, and there is a problem that a margin against noise and the like cannot be secured.
このようなことから、MOSキヤパシタを構
成する絶縁膜の厚さを薄くすること、MOSキ
ヤパシタを構成する絶縁膜として従来用いられて
いるSiO2膜の代わりに誘電率の大きいSi3N4膜等
を使用すること、が知られている。しかしなが
ら、かかる構造のMOSキヤパシタでは絶縁膜の
耐圧や膜質（ピンホール等）の点で問題があり、
キヤパシタ電極の面積を縮小するのには限界があ
つた。 For this reason, it is necessary to reduce the thickness of the insulating film that makes up the MOS capacitor, and to use a Si 3 N 4 film with a high dielectric constant instead of the SiO 2 film that is conventionally used as the insulating film that makes up the MOS capacitor. It is known to use. However, MOS capacitors with this structure have problems with the withstand voltage and film quality (pinholes, etc.) of the insulating film.
There was a limit to reducing the area of the capacitor electrode.
また、所定の容量を維持しつつMOSキヤパシ
タの面積を縮小する別の方法として、以下に述べ
る凹形MOSキヤパシタ（又はＶ形MOSキヤパシ
タ）が知られている。即ち、このキヤパシタは第
２図に示すように半導体基板１にＶ型の凹部４を
形成し、この凹部４に絶縁膜２′を介してキヤパ
シタ電極３′を設けてた構造になつている。かか
る凹形キヤパシタは、凹部４の深さや形状を変え
ることによつてキヤパシタ電極３′の実効面積を
任意に選ぶことができると共に、絶縁膜の耐圧、
膜質等も良好にできる。しかしながら、前記凹形
MOSキヤパシタでは凹部４とキヤパシタ電極
３′とのセルフアランイがにずかしく、マスク合
せずれを考慮して凹部４の両側に余裕（Ａ）をと
る必要があり、MOSキヤパシタの縮小化の妨げ
となり、ひいてはMOSダイナミツクRAMの高集
積化にとつて大きな問題となつていた。 Furthermore, as another method for reducing the area of a MOS capacitor while maintaining a predetermined capacity, a concave MOS capacitor (or V-type MOS capacitor) described below is known. That is, as shown in FIG. 2, this capacitor has a structure in which a V-shaped recess 4 is formed in a semiconductor substrate 1, and a capacitor electrode 3' is provided in this recess 4 with an insulating film 2' interposed therebetween. In such a concave capacitor, by changing the depth and shape of the concave portion 4, the effective area of the capacitor electrode 3' can be arbitrarily selected, and the withstand voltage of the insulating film,
The film quality can also be improved. However, the concave
In a MOS capacitor, the self-alignment between the recess 4 and the capacitor electrode 3' is difficult, and it is necessary to provide an allowance (A) on both sides of the recess 4 in consideration of mask misalignment, which hinders the miniaturization of the MOS capacitor. This has become a major problem in increasing the integration density of MOS dynamic RAM.
（発明が解決しようとする問題点）
本発明は、上記従来の問題点を解決するために
なされたもので、メモリセルに平面的に占めるキ
ヤパシタ電極の面積を縮小化すると共に高容量化
が図られたMOSキヤパシタを有し、かつ前記キ
ヤパシタ電極とMOSトランジスタのゲート電極
間の絶縁耐圧を向上し、さらに不必要なマージン
取ることなく設計寸法通りのチヤンネル長を有す
るカツトオフ特性が良好なゲート電極の形成が可
能な半導体装置の製造方法を提供しようとするも
のである。(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems, and it is possible to reduce the area of the capacitor electrode that occupies the memory cell in plan view and to increase the capacitance. A gate electrode having a MOS capacitor with a high cut-off characteristic, which improves the dielectric strength between the capacitor electrode and the gate electrode of the MOS transistor, and has a channel length according to the designed dimensions without taking unnecessary margins. The present invention aims to provide a method for manufacturing a semiconductor device that can be formed.
［発明の構成］
（課題を解決するための手段）
本発明は、一導電型のシリコン基板の所望部分
に溝部を設ける工程と、前記溝部内面に絶縁膜を
形成する工程と、不純物を含む多結晶シリコンか
らなる電極材料を堆積して少なくとも前記溝部内
に前記電極材料を埋め込む工程と、前記溝部を除
く領域上の電極材料が除去されるまでエツチング
して溝部内に電極材料を残存させることによりキ
ヤパシタ電極を有するMOSキヤパシタを形成す
る工程と、熱酸化を施して前記シリコン基板表面
に薄い酸化膜を、前記溝部内の不純物を含む多結
晶シリコンからなるキヤパシタ電極表面に厚い酸
化膜をそれぞれ形成する工程と、ゲート電極を前
記基板表面の薄い酸化膜上から前記キヤパシタ電
極表面の厚い酸化膜上に延出させて形成する工程
と、前記ゲート電極に隣接した前記基板表面に前
記基板と逆導電型の不純物拡散層を形成する工程
とを具備したことを特徴とする半導体装置の製造
方法である。[Structure of the Invention] (Means for Solving the Problems) The present invention includes a step of providing a groove in a desired portion of a silicon substrate of one conductivity type, a step of forming an insulating film on the inner surface of the groove, and a step of forming a multilayer film containing impurities. By depositing an electrode material made of crystalline silicon and embedding the electrode material at least in the groove, and etching until the electrode material on the area other than the groove is removed to leave the electrode material in the groove. A step of forming a MOS capacitor having a capacitor electrode, and performing thermal oxidation to form a thin oxide film on the surface of the silicon substrate and a thick oxide film on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove. a step of forming a gate electrode extending from a thin oxide film on the surface of the substrate to a thick oxide film on the surface of the capacitor electrode; A method of manufacturing a semiconductor device is characterized in that it comprises a step of forming an impurity diffusion layer.
前記溝部は、一般的に前記半導体基板に複数設
けられる。かかる溝部は、例えばマスク材（レジ
ストパターン等）を用いて露出する基板部分を所
望深さ選択的にエツチングする方法により形成さ
れる。この場合、エツチング手段としては反応性
イオンビームエツチング、リアクテイブイオンエ
ツチングを用いれば、側面が略垂直な溝部を形成
することが可能となる。ただし、その他のエツチ
ング手段により逆テーパ状の側面を有する溝部を
形成してもよい。また、異なる深さの溝部を前記
半導体基板に設けることも可能である。 A plurality of grooves are generally provided in the semiconductor substrate. Such a groove is formed, for example, by a method of selectively etching the exposed portion of the substrate to a desired depth using a mask material (resist pattern, etc.). In this case, if reactive ion beam etching or reactive ion etching is used as the etching means, it is possible to form a groove portion with substantially vertical side surfaces. However, the groove portion having reversely tapered side surfaces may be formed by other etching means. It is also possible to provide grooves with different depths in the semiconductor substrate.
前記絶縁膜の形成手段としては、例えば熱酸化
により酸化膜を形成する方法、CVD法により
SiO2膜やSi3N4膜等などを形成する方法を採用し
得る。かかる絶縁膜は、前記溝部内を全て埋め込
まず溝部の内側面及び底面に薄く形成することが
必要である。 As a means for forming the insulating film, for example, a method of forming an oxide film by thermal oxidation, a method of forming an oxide film by a CVD method, etc.
A method of forming a SiO 2 film, a Si 3 N 4 film, etc. can be adopted. Such an insulating film needs to be formed thinly on the inner surface and bottom surface of the trench, rather than filling the entire inside of the trench.
前記不純物を含む多結晶シリコンとしは、例え
ば燐ドープ多結晶シリコン、砒素ドープ多結晶シ
リコン等を挙げることができる。かかる多結晶シ
リコンからなる電極材料の堆積に際しては、前記
溝部の開口部幅の半分以上の厚さとなるように堆
積することが望ましい。 Examples of the impurity-containing polycrystalline silicon include phosphorus-doped polycrystalline silicon, arsenic-doped polycrystalline silicon, and the like. When depositing the electrode material made of polycrystalline silicon, it is desirable that the electrode material be deposited to a thickness that is at least half the width of the opening of the groove.
（作用）
本発明によれば、一導電型のシリコン基板の所
望部分に溝部を設け、前記溝部内面に絶縁膜を形
成し、さらに不純物を含む多結晶シリコンからな
る電極材料を堆積して少なくとも前記溝部内に前
記電極材料を埋め込んだ後、前記溝部を除く領域
上の電極材料が除去されるまでエツチングして溝
部内に電極材料を残存させることによつて、キヤ
パシタ電極を前記溝部内に自己整合的に形成する
ことができる。その結果、前記キヤパシタ電極の
面積は前記溝部の開口面積で決定されるため、形
成されたMOSキヤパシタのメモリセルに平面的
に占める面積を縮小化できる。しかも、形成され
たMOSキヤパシタは溝部内に絶縁膜を挟んでキ
ヤパシタ電極が埋め込まれた構造を有するため、
平面的に占める面積を縮小化されているにもかか
わらず、高容量化できる。(Function) According to the present invention, a groove is provided in a desired portion of a silicon substrate of one conductivity type, an insulating film is formed on the inner surface of the groove, and an electrode material made of polycrystalline silicon containing impurities is deposited. After embedding the electrode material within the groove, the capacitor electrode is self-aligned within the groove by etching until the electrode material on the area excluding the groove is removed, leaving the electrode material within the groove. It can be formed as follows. As a result, since the area of the capacitor electrode is determined by the opening area of the groove, the area occupied by the formed MOS capacitor in the memory cell can be reduced. Moreover, since the formed MOS capacitor has a structure in which the capacitor electrode is embedded in the groove with an insulating film in between,
Although the planar area occupied is reduced, the capacity can be increased.
また、キヤパシタ電極を不純物を含む多結晶シ
リコンにより形成することによつて、MOSキヤ
パシタの形成後の熱酸化処理工程で前記シリコン
基板表面に薄い酸化膜を、前記溝部内の不純物を
含む多結晶シリコンからなるキヤパシタ電極表面
に厚い酸化膜をそれぞれ形成できる。その結果、
ゲート電極を前記基板表面の薄い酸化膜上から前
記キヤパシタ電極表面の厚い酸化膜上に延出させ
て形成することによつて、前記キヤパシタ電極と
前記ゲート電極の間には十分に厚い前記酸化膜を
介在させることができるため、それらの間の絶縁
耐圧を著しく向上できると共に、それらの間の容
量を低減してメモリセルの高速動作を達成するこ
とができる。 Furthermore, by forming the capacitor electrode from polycrystalline silicon containing impurities, a thin oxide film is formed on the surface of the silicon substrate in a thermal oxidation process after the formation of the MOS capacitor, and the polycrystalline silicon containing impurities is formed in the groove. A thick oxide film can be formed on the surface of each capacitor electrode. the result,
By forming the gate electrode extending from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode, the oxide film is sufficiently thick between the capacitor electrode and the gate electrode. can be interposed, the dielectric breakdown voltage between them can be significantly improved, and the capacitance between them can be reduced to achieve high-speed operation of the memory cell.
更に、前記キヤパシタ電極を前記溝部内に自己
整合的に形成することによつて、ゲート電極を前
記基板表面の薄い酸化膜上から前記キヤパシタ電
極表面の厚い酸化膜上に延出させる工程に際し、
前記ゲート電極のチヤンネル長（前記基板表面の
薄い酸化膜上の部分に相当）が前記キヤパシタ電
極の位置状態に依存して設計寸法より変動する、
特に設計寸法よりチヤンネル長が短くなるのを回
避できる。その結果、ゲート電極の形成に際して
チヤンネル長を設計寸法にするためのマージンを
取る必要がなくなるため、メモリセルに占めるゲ
ート電極の面積を縮小でき、高集積度の半導体装
置を製造できる。 Furthermore, in the step of extending the gate electrode from the thin oxide film on the surface of the substrate to the thick oxide film on the surface of the capacitor electrode by forming the capacitor electrode in the groove in a self-aligned manner,
The channel length of the gate electrode (corresponding to the portion on the thin oxide film on the surface of the substrate) varies from the design dimension depending on the positional state of the capacitor electrode.
In particular, it is possible to avoid the channel length becoming shorter than the design dimension. As a result, it is no longer necessary to take a margin for adjusting the channel length to the designed dimension when forming the gate electrode, so the area occupied by the gate electrode in the memory cell can be reduced, and a highly integrated semiconductor device can be manufactured.
（発明の実施例）
以下、本発明をMOSダイナミツクRAMに適用し
た例について第３図ａ〜ｉに示す製造方法を併記
して詳細に説明する。(Embodiments of the Invention) Hereinafter, an example in which the present invention is applied to a MOS dynamic RAM will be described in detail with reference to the manufacturing method shown in FIGS. 3a to 3i.
まず、第３図ａに示すようにｐ型シリコン基板
１１に選択酸化法によつて素子分離のためのフイ
ールド酸化膜１２を形成した。つづいて、スパツ
タエツチングを用いた写真蝕刻法によりシリコン
基板１１の素子領域の一部に幅1μm、長さ3μm、
深さ2.5μmの溝部１３を形成した（同図ｂ図示）。 First, as shown in FIG. 3a, a field oxide film 12 for element isolation was formed on a p-type silicon substrate 11 by selective oxidation. Subsequently, a part of the element region of the silicon substrate 11 is etched by photolithography using sputter etching, with a width of 1 μm and a length of 3 μm.
A groove 13 with a depth of 2.5 μm was formed (as shown in FIG. 1B).
次いで、1000℃のドライ酸素雰囲気中で熱酸化
処理を施した。この時、同図ｃに示すように溝部
１３を含むシリコン基板１１全面に厚さ300〓の
熱酸化膜１４が成長された。つづいて、CVD法
により厚さ6000〓の燐ドープ多結晶シリコン膜を
堆積した。この時、同図ｄに示すようにシリコン
基板１１に燐ドープ多結晶シリコン膜１５が被着
されると共に、幅が1μmの前記溝部１３の開口部
まで同多結晶シリコンで埋め込まれた。 Next, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000°C. At this time, a thermal oxide film 14 having a thickness of 300 mm was grown on the entire surface of the silicon substrate 11 including the groove portion 13, as shown in FIG. Next, a 6000 mm thick phosphorus-doped polycrystalline silicon film was deposited using the CVD method. At this time, as shown in Figure d, a phosphorus-doped polycrystalline silicon film 15 was deposited on the silicon substrate 11, and the opening of the groove 13 having a width of 1 μm was filled with the same polycrystalline silicon.
次いで、燐ドープ多結晶シリコン膜１５を溝部
１３以外の熱酸化膜１４が露出するまで弗酸系の
エツチング液で全面エツチングして溝部１３内に
燐ドープ多結晶シリコンを残置させて溝部１３内
にキヤパシタ電極１６を形成した（同図ｅ図示）。
この時、キヤパシタ電極１６はその上部側面が溝
部１３内のキヤパシタ絶縁膜となる熱酸化膜１４
の内側面と一致して溝部１３内に埋込まれた状態
となつた。つづいて、キヤパシタ電極１６をマス
クとしてシリコン基板１１主面上の熱酸化膜１４
部分を選択的にエツチング除去して溝部１３内に
残置させた熱酸化膜によりキヤパシタの絶縁膜１
７を形成した（同図ｆ図示）。 Next, the entire surface of the phosphorus-doped polycrystalline silicon film 15 is etched using a hydrofluoric acid-based etching solution until the thermal oxide film 14 other than the groove 13 is exposed, leaving the phosphorus-doped polycrystalline silicon in the groove 13. A capacitor electrode 16 was formed (shown in e of the figure).
At this time, the upper side surface of the capacitor electrode 16 forms a thermal oxide film 14 which becomes a capacitor insulating film within the groove 13.
It is now embedded in the groove 13 in line with the inner surface of the groove 13. Next, using the capacitor electrode 16 as a mask, the thermal oxide film 14 on the main surface of the silicon substrate 11 is
The insulation film 1 of the capacitor is formed by selectively etching away the thermal oxide film left in the groove 13.
7 (shown in f of the same figure).
次いで、1000℃のドライ酸素雰囲気で熱酸化処
理を施した。この時、同図ｇに示すように露出す
るシリコン基板１１主面上に厚さ750〓の熱酸化
膜１８が、燐ドープ多結晶シリコンからなるキヤ
パシタ電極１６には厚さ1200〓程度の厚い酸化膜
１９が夫々成長された。つづいて、多結晶シリコ
ン膜を堆積した後、パターニングしてゲート電極
２０を形成した（同図ｈ図示）。ひきつづき、ゲ
ート電極２０をマスクとして熱酸化膜１８を選択
エツチングしてゲート絶縁膜２１を形成した後、
砒素をシリコン基板１１に拡散してデジツトライ
ンとなるn+拡散層２２を形成した。その後、全
面にCVD法により低温酸化膜２３を堆積し、コ
ンタクトホール２４を開孔した後、Ａ配線２５
を形成してMOSダイナミツクRAMを製造した
（同図ｉ図示）。 Next, thermal oxidation treatment was performed in a dry oxygen atmosphere at 1000°C. At this time, as shown in FIG. A film 19 was grown respectively. Subsequently, a polycrystalline silicon film was deposited and patterned to form a gate electrode 20 (as shown in h of the figure). Subsequently, after selectively etching the thermal oxide film 18 using the gate electrode 20 as a mask to form a gate insulating film 21,
Arsenic was diffused into the silicon substrate 11 to form an n + diffusion layer 22 that would become a digital line. After that, a low-temperature oxide film 23 is deposited on the entire surface by CVD method, a contact hole 24 is opened, and then the A wiring 25
A MOS dynamic RAM was manufactured by forming a MOS dynamic RAM (shown in Figure i).
しかして、本発明によればｐ型シリコン基板１
１に溝部１３を設け、前記溝部１３内面に熱酸化
膜１４を形成し、さらに燐ドープ多結晶シリコン
膜１５を堆積した後、前記溝部１３を除く領域
（前記基板１１上の熱酸化膜１４）が露出するま
でエツチングして溝部１３内に多結晶シリコンを
残存させることによつて、キヤパシタ電極１６を
前記溝部１３内に自己整合的に形成することがで
きる。その結果、前記キヤパシタ電極１６の面積
は前記溝部１３の開口面積で決定されるため、形
成されたMOSキヤパシタのメモリセルに平面的
に占める面積を縮小化できる。しかも、形成され
たMOSキヤパシタは溝部１３内に絶縁膜１７を
挟んでキヤパシタ電極１６が埋め込まれた構造を
有するため、平面的に占める面積を縮小化されて
いるにもかかわらず、高容量化できる。具体的に
は、前記MOSキヤパシタは前記溝部１３の幅が
1μm、深さが2.5μmで、その周囲の面積が23μm2
となり、かつ熱酸化膜の厚さが300〓であるから、
約27fFと十分大きな容量を有する。 According to the present invention, the p-type silicon substrate 1
1, a thermal oxide film 14 is formed on the inner surface of the groove 13, and a phosphorus-doped polycrystalline silicon film 15 is further deposited. By etching until the polycrystalline silicon is exposed and leaving the polycrystalline silicon in the groove 13, the capacitor electrode 16 can be formed in the groove 13 in a self-aligned manner. As a result, the area of the capacitor electrode 16 is determined by the opening area of the groove 13, so that the area occupied by the formed MOS capacitor in the memory cell can be reduced. Moreover, since the formed MOS capacitor has a structure in which the capacitor electrode 16 is embedded in the groove 13 with the insulating film 17 interposed therebetween, the capacitance can be increased even though the area occupied in a plan view is reduced. . Specifically, in the MOS capacitor, the width of the groove portion 13 is
1μm, depth 2.5μm, surrounding area 23μm 2
And since the thickness of the thermal oxide film is 300〓,
It has a sufficiently large capacitance of approximately 27fF.
また、キヤパシタ電極１６を燐ドープ多結晶シ
リコンにより形成することによつて、MOSキヤ
パシタの形成後の熱酸化処理工程で前記シリコン
基板１１表面に薄い酸化膜１８を、前記溝部１３
内の燐ドープ多結晶シリコンからなるキヤパシタ
電極１６表面の厚い酸化膜１９をそれぞれ形成で
きる。その結果、ゲート電極２０を前記基板１１
表面の薄い酸化膜１８上から前記キヤパシタ電極
１６表面の厚い酸化膜１９上に延出させて形成す
ることによつて、前記キヤパシタ電極１６と前記
ゲート電極２０の間には十分に厚い前記酸化膜１
９を介在させることができるため、それらの間の
絶縁耐圧を著しく向上できると共に、それらの間
の容量を低減してメモリセルの高速動作を達成す
ることができる。 Furthermore, by forming the capacitor electrode 16 from phosphorous-doped polycrystalline silicon, a thin oxide film 18 is formed on the surface of the silicon substrate 11 in the thermal oxidation process after the formation of the MOS capacitor.
A thick oxide film 19 can be formed on the surface of the capacitor electrode 16 made of phosphorus-doped polycrystalline silicon. As a result, the gate electrode 20 is connected to the substrate 11.
By forming the oxide film extending from the thin oxide film 18 on the surface to the thick oxide film 19 on the surface of the capacitor electrode 16, the oxide film is sufficiently thick between the capacitor electrode 16 and the gate electrode 20. 1
9 can be interposed, the dielectric breakdown voltage between them can be significantly improved, and the capacitance between them can be reduced to achieve high-speed operation of the memory cell.
更に、前記キヤパシタ電極１６を前記溝部１３
内に自己整合的に形成することによつて、ゲート
電極２０を前記基板１１表面の薄い酸化膜１８上
から前記キヤパシタ電極１６表面の厚い酸化膜１
９上に延出させる工程に際し、前記ゲート電極２
０のチヤンネル長（前記基板１１表面の薄い酸化
膜１８上の部分に相当）が前記キヤパシタ電極１
６の位置状態に依存して設計寸法より変動する、
特に設計寸法よりチヤンネル長が短くなるのを回
避できる。その結果、ゲート電極２０の形成に際
してチヤンネル長を設計寸法にするためのマージ
ンを取る必要がなくなるため、メモリセルに占め
るゲート電極２０の面積を縮小でき、高集積度の
MOSダイナミツクRAMを製造できる。 Further, the capacitor electrode 16 is inserted into the groove portion 13.
By forming the gate electrode 20 in a self-aligned manner within the substrate 11, the gate electrode 20 is formed from the thin oxide film 18 on the surface of the substrate 11 to the thick oxide film 1 on the surface of the capacitor electrode 16.
In the process of extending the gate electrode 2 onto the
A channel length of 0 (corresponding to the portion on the thin oxide film 18 on the surface of the substrate 11) is the capacitor electrode 1.
The design dimensions vary depending on the position state of 6.
In particular, it is possible to avoid the channel length becoming shorter than the design dimension. As a result, when forming the gate electrode 20, there is no need to take a margin for adjusting the channel length to the design dimension, so the area occupied by the gate electrode 20 in the memory cell can be reduced, and the area of the gate electrode 20 can be reduced.
MOS dynamic RAM can be manufactured.
なお、上記実施例ではキヤパシタ電極１６上面
が熱酸化前において基板１１主面と同じレベルと
なるように形成したが、第４図に示すように溝部
１３内に上面がシリコン基板１１の主面より下が
るようにキヤパシタ電極１６′を設けてもよい。 In the above embodiment, the upper surface of the capacitor electrode 16 was formed to be at the same level as the main surface of the substrate 11 before thermal oxidation, but as shown in FIG. The capacitor electrode 16' may be provided downwardly.
上記実施例では、溝部１３をシリコン基板１１
の主面に対して略垂直に近い側面を有する形状と
したが、第５図に示すように側面が逆テーパ状の
溝部１３′を設け、該溝部１３′内にキヤパシタ電
極１６′を形成してもよい。但し、この場合には
溝部１３′内に空洞２６ができる。 In the above embodiment, the groove portion 13 is formed on the silicon substrate 11.
As shown in FIG. 5, a groove 13' with a reversely tapered side surface is provided, and a capacitor electrode 16' is formed in the groove 13'. It's okay. However, in this case, a cavity 26 is created within the groove portion 13'.
上記実施例では、フイールド酸化膜１２により
囲まれたシリコン基板１１の島領域（素子領域）
にMOSキヤパシタを１つ設けた構造にしたが、
第６図に示すように深さの異なる溝部１３ａ，１
３ｂをフイールド酸化膜１２で囲まれたシリコン
基板１１の素子領域に設け、これら溝部１３ａ，
１３ｂ内に薄い絶縁膜１４を形成し、該絶縁膜１
４が形成された各溝部１３ａ，１３ｂ内にキヤパ
シタ電極１６ａ，１６ｂを埋め込んで容量の異な
る２つのMOSキヤパシタを形成するようにして
もよい。 In the above embodiment, the island region (device region) of the silicon substrate 11 surrounded by the field oxide film 12
The structure has one MOS capacitor installed in the
Grooves 13a, 1 with different depths as shown in FIG.
3b is provided in the element region of the silicon substrate 11 surrounded by the field oxide film 12, and these grooves 13a,
A thin insulating film 14 is formed in the insulating film 13b.
Two MOS capacitors having different capacitances may be formed by embedding capacitor electrodes 16a and 16b in the grooves 13a and 13b in which the capacitors 4 are formed.
［発明の効果］
以上詳述したように、本発明によればメモリセ
ルに平面的に占めるキヤパシタ電極の面積を縮小
化できると共に高容量化が図られたMOSキヤパ
シタを有し、かつ前記キヤパシタ電極とトランジ
スタのゲート電極間の絶縁耐圧を向上し、さらに
不必要なマージン取ることなく設計寸法通りのチ
ヤンネル長を有するカツトオフ特性が良好なゲー
ト電極を形成でき、ひいては高信頼性、高集積度
の半導体装置の製造方法を提供できる。[Effects of the Invention] As described in detail above, according to the present invention, the area of the capacitor electrode that occupies a memory cell in plan view can be reduced, and the MOS capacitor has a high capacity, and the capacitor electrode In addition, it is possible to improve the dielectric strength between the gate electrode of the transistor and the gate electrode of the transistor, and also to form a gate electrode with good cut-off characteristics and a channel length according to the design dimension without taking unnecessary margins, resulting in highly reliable and highly integrated semiconductors. A method for manufacturing the device can be provided.
第１図は従来のMOSキヤパシタを示す断面図、
第２図は凹形MOSキヤパシタを示す断面図、第
３図ａ〜ｉは本発明の実施例におけるMOSダイ
ナミツクRAMを得るための製造工程を示す断面
図、第４図〜第６図は夫々本発明の他の実施例を
示す断面図である。
１１……ｐ型シリコン基板、１２……フイール
ド酸化膜、１３，１３′，１３ａ，１３ｂ……溝
部、１６，１６′，１６′……キヤパシタ電極、１
７……キヤパシタの絶縁膜、２０……ゲート電
極、２１……ゲート酸化膜、２２……n+拡散層
（デジツトライン）、２５……配線。
Figure 1 is a cross-sectional view of a conventional MOS capacitor.
FIG. 2 is a sectional view showing a concave MOS capacitor, FIGS. FIG. 7 is a sectional view showing another embodiment of the invention. 11...P-type silicon substrate, 12...Field oxide film, 13, 13', 13a, 13b...Groove portion, 16, 16', 16'...Capacitor electrode, 1
7... Capacitor insulating film, 20... Gate electrode, 21... Gate oxide film, 22... n + diffusion layer (digital line), 25... Wiring.
Claims (1)
設ける工程と、 前記溝部内面に絶縁膜を形成する工程と、 不純物を含む多結晶シリコンからなる電極材料
を堆積して少なくとも前記溝部内に前記電極材料
を埋め込む工程と、 前記溝部を除く領域上の電極材料が除去される
までエツチングして溝部内に電極材料を残存させ
ることによりキヤパシタ電極を有するMOSキヤ
パシタを形成する工程と、 熱酸化を施して前記シリコン基板表面に薄い酸
化膜を、前記溝部内の不純物を含む多結晶シリコ
ンからなるキヤパシタ電極表面に厚い酸化膜をそ
れぞれ形成する工程と、 ゲート電極を前記基板表面の薄い酸化膜上から
前記キヤパシタ電極表面の厚い酸化膜上に延出さ
せて形成する工程と、 前記ゲート電極に隣接した前記基板表面に前記
基板と逆導電型の不純物拡散層を形成する工程と
を具備したことを特徴とする半導体装置の製造方
法。[Claims] 1. A step of providing a groove in a desired portion of a silicon substrate of one conductivity type, a step of forming an insulating film on the inner surface of the groove, and depositing an electrode material made of polycrystalline silicon containing impurities. a step of embedding the electrode material in the groove; and a step of forming a MOS capacitor having a capacitor electrode by etching until the electrode material on a region other than the groove is removed and leaving the electrode material in the groove. , forming a thin oxide film on the surface of the silicon substrate by thermal oxidation and a thick oxide film on the surface of the capacitor electrode made of polycrystalline silicon containing impurities in the groove; and forming a gate electrode on the thin oxide film on the surface of the substrate. forming an impurity diffusion layer extending from the oxide film onto a thick oxide film on the surface of the capacitor electrode; and forming an impurity diffusion layer of a conductivity type opposite to that of the substrate on the surface of the substrate adjacent to the gate electrode. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125604A JPS6323352A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125604A JPS6323352A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15897879A Division JPS5681968A (en) | 1979-12-07 | 1979-12-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6323352A JPS6323352A (en) | 1988-01-30 |
| JPH0441507B2 true JPH0441507B2 (en) | 1992-07-08 |
Family
ID=14914236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62125604A Granted JPS6323352A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6323352A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376686A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
| JPS5394191A (en) * | 1977-01-28 | 1978-08-17 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-05-22 JP JP62125604A patent/JPS6323352A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376686A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
| JPS5394191A (en) * | 1977-01-28 | 1978-08-17 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6323352A (en) | 1988-01-30 |
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