JPS5339868A - Packaging method of semiconductor device - Google Patents

Packaging method of semiconductor device

Info

Publication number
JPS5339868A
JPS5339868A JP11365076A JP11365076A JPS5339868A JP S5339868 A JPS5339868 A JP S5339868A JP 11365076 A JP11365076 A JP 11365076A JP 11365076 A JP11365076 A JP 11365076A JP S5339868 A JPS5339868 A JP S5339868A
Authority
JP
Japan
Prior art keywords
semiconductor device
packaging method
protrusions
positions
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11365076A
Other languages
Japanese (ja)
Other versions
JPS5946101B2 (en
Inventor
Ikuo Tomita
Eiichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP51113650A priority Critical patent/JPS5946101B2/en
Publication of JPS5339868A publication Critical patent/JPS5339868A/en
Publication of JPS5946101B2 publication Critical patent/JPS5946101B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To improve packaging yield by positively aligning the positions of the electrode patterns of elements and the protrusions of lead fingers and performing bonding simultaneously.
COPYRIGHT: (C)1978,JPO&Japio
JP51113650A 1976-09-24 1976-09-24 Mounting method for semiconductor devices Expired JPS5946101B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51113650A JPS5946101B2 (en) 1976-09-24 1976-09-24 Mounting method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51113650A JPS5946101B2 (en) 1976-09-24 1976-09-24 Mounting method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5339868A true JPS5339868A (en) 1978-04-12
JPS5946101B2 JPS5946101B2 (en) 1984-11-10

Family

ID=14617631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51113650A Expired JPS5946101B2 (en) 1976-09-24 1976-09-24 Mounting method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5946101B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152147A (en) * 1981-03-16 1982-09-20 Matsushita Electric Ind Co Ltd Formation of metal projection on metal lead

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152147A (en) * 1981-03-16 1982-09-20 Matsushita Electric Ind Co Ltd Formation of metal projection on metal lead

Also Published As

Publication number Publication date
JPS5946101B2 (en) 1984-11-10

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