JPS52134340A - Data transfer synchronous digital logical circuit - Google Patents

Data transfer synchronous digital logical circuit

Info

Publication number
JPS52134340A
JPS52134340A JP4749677A JP4749677A JPS52134340A JP S52134340 A JPS52134340 A JP S52134340A JP 4749677 A JP4749677 A JP 4749677A JP 4749677 A JP4749677 A JP 4749677A JP S52134340 A JPS52134340 A JP S52134340A
Authority
JP
Japan
Prior art keywords
data transfer
logical circuit
synchronous digital
digital logical
transfer synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4749677A
Other languages
English (en)
Inventor
Kurea Hetsupuwaasu Edowaado
Jieroomu Miinzu Rotsudoniii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPS52134340A publication Critical patent/JPS52134340A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Shift Register Type Memory (AREA)
  • Communication Control (AREA)
JP4749677A 1976-05-03 1977-04-26 Data transfer synchronous digital logical circuit Pending JPS52134340A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/682,822 US4070630A (en) 1976-05-03 1976-05-03 Data transfer synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS52134340A true JPS52134340A (en) 1977-11-10

Family

ID=24741298

Family Applications (2)

Application Number Title Priority Date Filing Date
JP4749677A Pending JPS52134340A (en) 1976-05-03 1977-04-26 Data transfer synchronous digital logical circuit
JP1981054650U Pending JPS57227U (ja) 1976-05-03 1981-04-17

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP1981054650U Pending JPS57227U (ja) 1976-05-03 1981-04-17

Country Status (6)

Country Link
US (1) US4070630A (ja)
JP (2) JPS52134340A (ja)
DE (1) DE2719531C3 (ja)
FR (1) FR2350646A1 (ja)
GB (1) GB1579626A (ja)
HK (1) HK31981A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224349A (ja) * 1985-07-24 1987-02-02 Nec Corp デ−タ信号送受信処理装置
JPH0191959U (ja) * 1987-12-11 1989-06-16
JPH0713926A (ja) * 1992-06-13 1995-01-17 Internatl Business Mach Corp <Ibm> バッファ制御回路及びその操作方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
JPS5368912A (en) * 1976-12-02 1978-06-19 Casio Comput Co Ltd Initial value set system
US4238834A (en) * 1978-03-06 1980-12-09 International Business Machines Corporation Apparatus for coordinating real time transfer of data from a processor to a magnetic media device
DE2834128C2 (de) * 1978-08-03 1983-12-15 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum Verarbeiten zeitlich undefiniert an der Schnittstelle digitaler, autonom arbeitender Funktionseinheiten eintreffender Eingangssignale
JPS5537641A (en) * 1978-09-08 1980-03-15 Fujitsu Ltd Synchronization system for doubled processor
US4307385A (en) * 1978-11-22 1981-12-22 Sue Ann Evans Noise monitoring apparatus
US4409680A (en) * 1981-08-27 1983-10-11 Ncr Corporation High speed write control for synchronous registers
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
DE3213345C2 (de) * 1982-04-08 1984-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen
US4596026A (en) * 1983-05-09 1986-06-17 Raytheon Company Asynchronous data clock generator
US5179688A (en) * 1987-06-30 1993-01-12 Tandem Computers Incorporated Queue system with uninterrupted transfer of data through intermediate locations to selected queue location
US4879718A (en) * 1987-11-30 1989-11-07 Tandem Computers Incorporated Scan data path coupling
GB2228848A (en) * 1988-12-08 1990-09-05 Plessey Co Plc A data synchronisation arrangement
GB2262415B (en) * 1991-12-13 1995-08-16 Digital Equipment Int Handshake synchronization system
US5388241A (en) * 1992-03-10 1995-02-07 Northrop Grumman Corporation Asynchronous circuit for 2-cycle to 4-cycle handshake conversion
US5548790A (en) * 1993-02-10 1996-08-20 Capital Equipment Corporation High speed IEEE 488 bus data transfer system
DE4407948C2 (de) * 1994-03-09 1996-07-18 Walter Dr Mehnert Schnittstelle
US5905766A (en) * 1996-03-29 1999-05-18 Fore Systems, Inc. Synchronizer, method and system for transferring data
KR100223026B1 (ko) * 1996-10-17 1999-10-01 정선종 동기화 회로

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US333753A (en) * 1886-01-05 Bilge-water ejector
JPS49123538A (ja) * 1973-03-30 1974-11-26

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1369507A (fr) * 1963-07-03 1964-08-14 Europ Pour Le Traitement De L Perfectionnements aux mémoires intermédiaires utilisables en liaison avec un calculateur numérique
GB1139592A (en) * 1965-08-10 1969-01-08 Mullard Ltd Improvements in or relating to buffer information stores
US3560639A (en) * 1966-10-03 1971-02-02 Xerox Corp Cascade run length encoding technique
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register
JPS4940036A (ja) * 1972-08-16 1974-04-15
JPS49122940A (ja) * 1973-03-26 1974-11-25
US3972034A (en) * 1975-05-12 1976-07-27 Fairchild Camera And Instrument Corporation Universal first-in first-out memory device
US3980820A (en) * 1975-06-17 1976-09-14 Fmc Corporation Clock phasing circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US333753A (en) * 1886-01-05 Bilge-water ejector
JPS49123538A (ja) * 1973-03-30 1974-11-26

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224349A (ja) * 1985-07-24 1987-02-02 Nec Corp デ−タ信号送受信処理装置
JPH0191959U (ja) * 1987-12-11 1989-06-16
JPH0713926A (ja) * 1992-06-13 1995-01-17 Internatl Business Mach Corp <Ibm> バッファ制御回路及びその操作方法

Also Published As

Publication number Publication date
US4070630A (en) 1978-01-24
DE2719531C3 (de) 1981-06-11
DE2719531B2 (de) 1980-08-14
FR2350646A1 (fr) 1977-12-02
DE2719531A1 (de) 1977-11-10
GB1579626A (en) 1980-11-19
JPS57227U (ja) 1982-01-05
HK31981A (en) 1981-07-17
FR2350646B1 (ja) 1980-09-19

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