GB1139592A - Improvements in or relating to buffer information stores - Google Patents

Abstract

1,139,592. Buffer information store. MULLARD Ltd. 20 June, 1966 [10 Aug., 1965], No. 34189/65. Heading G4C. A buffer information store includes a regenerative delay line having input means for feeding data sequentially to said delay line when the line is free to accept data, output means for passing data from the line to a converter when the converter is free to accept data, in which the data is in the form of multi-bit words or characters having a control signal for each word or character indicating that a meaningful word or character is present, the input means responding to the control signal so that it only feeds data to the delay line of the end of a sequence of meaningful words or characters and the output means responding to the first signal of the sequence so that it only extracts the information in an order starting with the first word or character in the line. In operation data is passed in parallel from a computer to a shift register 23. When input 6 on a control unit detects the absence of a control signal in the circulating loop of data then the data in register 23 is shifted and passed via AND gate 24 into the ultrasonic delay line 27. When a control signal is detected a Buffer Busy signal is sent to the computer. When data is to be extracted shift signals are sent to register 30 and gate 29 is inhibited so that the data passes into register 30 from where it can be extracted in parallel and zeros are written into the space formerly occupied by the said data. Each computer circulation or lap 'N' can hold for instance 14 characters of eight bits and a control bit (Fig. 2, not shown), and a dead spacer period. A clock bit source of pulses is triggered by the first control signal which thus commences each lap, and triggers a Dead Time Marker signal. Because fluctuations in voltage supply may vary the time at which the Dead Time pulse becomes zero an Extension Marker pulse is used to extend the clock bit pulses into dead time. To write data into the store (Fig. 4) assume five characters are present. On lap N-1 Character Ready pulse is sent to the Control Unit. This causes signal in line 13 to transfer data to register 23 but a Buffer Busy signal inhibits the shift signal. On lap N each character bit is examined and a binary value 0 causes a signal to appear in line 15 to open gate 24 and simultaneously a shift pulse is applied on line 14, transfer of data being terminated when the content of register 23 is zero. To Read out (Fig. 5) in lap N-1 a busy signal is initially present but at the end of the dead time marker is absent. Interrogation at this time causes a pulse on line 18 to reset register 30. On the following lap gate 29 is inhibited and shift pulses are fed to register 30 at the end of one character gate 29 is again enabled. The dead time marker on the following period now fires at the commencement of character 2. Amplifier 28 can be arranged to feed data into one of two parallel channels, one containing a one character register and the other a continuation of the wire of the loop. When a character is to be eliminated a switch which is such that all characters pass through the register is changed over when a character to be eliminated is in the register so that all the other characters pass through the other channel and close up the gap otherwise formed.