GB1144327A - Buffer arrangements - Google Patents

Abstract

1,144,327. Data storage device. WESTERN ELECTRIC CO. Inc. 3 May, 1966 [7 May, 1965], No. 19417/66. Heading G4C. A digital electric buffer arrangement comprises a register (100, Fig. 1, not shown) including a plurality of storage locations (100 1 -100 11 ) each for storing a multidigit information word, means for enabling application of information words to successive ones of said locations at a constant word rate and at a constant digit rate, and means for abstracting information words from said locations at a variable word rate and at a constant relatively high digit rate in an out-of-phase relationship with respect to the application of words to said locations. Information signals are passed to a set of AND gates (Fig. 2, not shown) equal in number to the number of storage locations, one of which is enabled by a ring counter to supply a word to only one location. As described a word comprises four digits and the digits are shifted along the storage location by signals from a shift control (Fig. 3, not shown) at a rate of 600 digits per second. The stored words are shifted out at a higher rate (2400 digits per sec.) to gates (112) enabled by an Out Ring Counter (Fig. 4, not shown), the word being also read back and stored until a new word is entered. Normally the words are read out at the same rate that they are read in. The second line of Fig. 5 shows the shift signals, four per word and the constant rate of supply of input words. The third line shows the constant stepping signals to the input ring counter. The higher frequency shift signals for the output signals are shown in the fourth line, and the stepping signals to the out ring counter in the fifth line. Under normal conditions when data is being entered into stage 8 for instance, towards the end of the entry the read out counter is stepped to stage 8. A coincidence unit detects that both counters read 8 and emits a pulse A. At time t12 a request for retransmission of data is received. The output ring counter is at 9 and steps 6 places to 4 followed by a normal step to 5. Since the input counter is now at 10 no coincidence occurs and the output changes to a fast mode of 200 words per second instead of the normal 150 words per second as words 5 to 9 are re-read. The fast rate then continues until a coincidence pulse C is detected when both counters reach word 3 and the read-out reverts to the slow mode.