GB2229067A - Retiming buffer for connecting binary data channels - Google Patents

Abstract

Input data is written into an addressable-read addressable-write cyclical memory in accord with an input clock 16 and read from the memory in accord with an output clock 24. The output reading starts a predetermined number of input clock cycles behind the input writing. Concurrent reading and writing from the same cell indicates that data is completed or the clocks are too fast out of synchronism. This is determined by equality detector 30 and signalled to state machine 32 which controls the operation of the circuiting on lines 40 and 42. <IMAGE>

Description

RETIMING BUFFER This invention relates to a retiming buffer designed to connect a pair of binary data channels having independent input and output clocks having frequencies designed to be equal but which may differ in practice due to fluctuations or other unwanted discrepanciies in one or both of the clocks due to phase differences and short term timing variations and other causes.

A common use will be the connection of data supplied along a sub channel clocked by its sub channel clock to a main channel clocked by a main channel clock. The invention is not however so limited.

Prior retiming buffers known to applicant are based on a FIFO (first in first out) register. Incoming data, subject to the incoming data clock is stored in a register and shifted from one storage location to the next during incoming data transmission. With such design a high speed reference clock is required to ensure that writes to and reads from the buffer do not occur at the same time.

According to one aspect of the invention a retiming buffer comprises an addressable latch of n stages, a cyclically operable input counter adapted to cyclically sequentially address said n stages, an input data clock adapted to control said input counter and the recording of data in said latch stages, an addressable selector for reading a selected one of said n stages, a cyclically operable output counter adapted to cause said selector to cyclically sequentially read said n stages, means adapted to provide the output of said selector as serial binary data, an output data clock adapted to control said output counter and the reading of data from said latch stages, means for starting said input clock from a predetermined datum, and means, responsive to said input counter reaching a count intermediate between 1 and n for starting said output clock from said predetermined datum.

According to a second aspect of the invention a retiming buffer comprises an addressable memory device of n cells, said device having a serial data input to write on a selected cell of said memory device, an input counter adapted to cyclically sequentially address said n cells, a selector connectable to read a selected cell of said memory device, an output counter adapted to cause said selector to cyclically sequentially address said n cells, means responsive to a supply of serial data to the device and input data clock signals to the input counter to sequentially write said input data in said memory device cells, means responsive to output data clock signals to cause said selector to read serial binary data sequentially from said memory cells, and means responsive to the initial operation of said input counter from a datum cell over a predetermined number of cells less than n for initiating operation of said means responsive to said output clock signal by reading from said datum cell.

According to a third aspect of the invention a retiming buffer comprises an addressable-write, addressable-read memory device having n cells, means responsive to a supply of serial input binary data and an input clock signal for writing said data on cells of said device in a sequence, commencing with a datum cell, in steps determined by said input clock, means responsive to the writing of a selected cell less than n cells in said sequence after said datum cell, for causing the start of reading of said cells, and means responsive to said start and an output clock for reading said data from cells in a device, commencing with said datum cell, in steps determined by said output clock.

In accord with this invention data remains in its initial storage location until after it has been read. For this reason there is no need to avoid simultaneous reads and writes and no high speed reference clock is required.

The following advantages may accrue: The novel retiming buffer is capable of higher speed operation than prior designs because a yet higher reference clock is not required; A small number of inputs and outputs is required for easy interfacing with other circuit blocks.

The buffer is unlikely to cause radio frequency interference because high speed reference clocks are not used.

The buffer may comprise an addressable-write addressable-read memory having n cells. Input means may be provided responsive to the receipt of serial binary data for writing said data cyclically sequentially on said memory cells, starting with a datum cell in steps determined by an input data clock. Output means may be provided, responsive to the writing on a datum cell less than n cells past the datum cell in said sequence, for reading from said cells, cyclically in said sequence, starting with the datum cell in steps determined by an output data clock. Thus as long as the input means and output means are not concurrently reading and writing on the same cell the serial data will be transferred from a channel connected to the input means to a channel connected to the output means even though there are variations in phase and frequency of the input and output data clocks.

The limit of frequency difference which may be tolerated is set by the difference in either sense which will cause the concurrent reading and writing from the same cell. Should such concurrent reading and writing take place then either (a) the input data is complete, or (b) there has been an over or under run of the input frequency relative to the output beyond the design limits of the device.

For equal tolerance of an input clock running faster or slower than the output clock the output means will start reading from the datum cell when the input means has, in its first sequence reached the n/2 cell. (n will usually be even but if not one of the two cells nearest to n/2 will approximate n/2) Preferably means are provided to detect concurrent reading and writing from the same cell to indicate that data is completed or the clocks are too fast out of synchronism.

The invention preferably comprises a memory device of n-cells, means for cyclically writing input binary data in said cells in accord with the clocking of an input data clock, means for cyclically reading binary data from said cells in accord with the clocking of an output data clock means for initiating operation of said reading means at a datum cell when said writing means has advanced a predetermined number of cells from said data cell.

Usually, with the device of the previous paragraph the variations of one clock relative to the other may, with equal probability, be in either sense and thus the reading will be initiated at datum after the write sequence is half-way through the cells that is approximately n/2 stages cells from datum.

Preferably the novel circuitry, as described in the two preceding paragraphs, is provided with means for determining when the write and read operations are being performed on the same cell. Should this occur the limit of overrun or underrun of the input clock relative to the output has been reached and the detection is used to cause deactivation of the buffer and there will conventionally be provided an indication of the condition.

In a preferred form of the invention so far described a multiple cell memory device, such as an addressable latch has its cell cyclically addressed by an n stage input counter which cyclically addresses the cells and is clocked by the input data clock which synchronously writes the input data bits in the latch cells. A selector is provided to cyclically read the latch cells and the selector is controlled by an n stage output counter clocked in accord with the output data clock. Means are provided for initiating operation of the output counter from a datum cell when the input counter is a predetermined number of stages (usually n/2) in advance of the datum cell. If the output counter reaches the same count as the input counter the data has all been transmitted or there has been maximum over or under run means will be provided for disabling the device.

In drawings which illustrate a preferred embodiment of the invention: Figure 1 shows a circuit in accord with the invention.

In the drawing serial binary input data is provided along line 10 to an 8-bit addressable latch 12. Writing of the input data bits on sequential stages of the latch 12 is controlled by the 8 stage, 3-bit input address counter 14.

The input data clock is connected along line 16 to increment the input counter 14 on the input clock's rising edge and the writing of data in the latch 12 occurs on the same rising edge under control of the input data clock to the Enable terminal of the latch. Propagation delays in the counter mean that the switch of addresses occurs just after the writing on the cell address.

The 1-of-8 selector 18 is connected to sequentially read onto line 20 the data in the latch 12 cells. The selector addresses latch cells as controlled by the 8-bit output address counter 22 which is clocked by the output data clock signal along line 24. The data on line 20 is received in output latch 26 and transmitted serially on output line 28 under control of the output data clock signal from line 24.

Equality detector 30 is connected to receive the outputs of the input and output counters and provide a signal to the state machine 32.

The state machine 32 is connected to control the operation of the circuiting. A START BUFFER signal along line 34 supplied by associated circuitry, not shown, goes from high to low state to initiate operation of the buffer and from low to high state to halt its operation. It is connected to receive on line 36 a signal when the equality detector finds equal counts on the input and output counters 14 and 22.

Equal counts indicates either that the input data and input data clock have ceased so that the output selector has reached the latch cell where the last data bit was written or that the frequency difference between the input and output clocks has caused concurrent writing on and reading from the same latch cell due to overrun or underrun of the input clock relative to the outer. The state machine 32 is adapted to signal on BUFFER EMPTY line 42 input address counter 14.

The state machine 32 is adapted to signal along BUFFER BEGIN line 40 to output counter 22 and output latch 26.

The logical design of the state machine 32 is as follows: (in this application 'high' is equivalent to 'Mark' and 'low' is equivalent to 'Space')

Transition State BUFFER EMPTY BUFFER BEGIN cause LINE LINE Idle High High START BUFFER High to Low Ir * Start Input Low High Address Counter Input address - - ! Counter I Start Output Low Low Address Counter Output Address 4 Counter=Input Address Counter Idle High High L START BUFFER Low to High Idle High High *state change (High, High) to (Low, High) is asynchronous (output condition (High, Low) is illegal and will cause unconditional transition to state (High, High)) The following criteria have been used with the specific circuiting shown in the specific embodiment.

Inputs: 1) Input Data - line 10 i) Logical One equals Mark 'or high' ii) Logical Zero equals Space 'or low' iii) Clamped by means exterior to the circuit to Mark when there is no subchannel activity 2) Input Data Clock - Line 16 i) Data transitions occur on the clock signal's falling edge ii) Data is written into the buffer on the clock signal's rising edge iii) Clamped by means exterior to the circuit to Logical Zero when there is no subchannel activity (Although the counter 14 is clocked in the input clock signal's rising edge, propagation delays in the counter caused the write address of the latch cell to change after data has been written at the former address) 3) Output Data Clock - Line 24 i) Data transitions occur on the clock signals falling edge ii) Data is read from the buffer on the clock signal's falling edge iii) Is constant running regardless of subchannel activity (Although the counter 22 is clocked on the output clock signal's falling edge, propagation delays in the counter cause the read address of the selector to change after data has been read at the former cell) 4) Start Buffer i) A Logical Zero indicates subchannel activity ii) A Logical One indicates no subchannel activity iii) Is used to clamp Input Data and Input Data Clock as described above Outputs: 1) Output data - Line 26 i) Logical One equals Mark or 'high' ii) Logical Zero equals Space or 'low' iii) Clamped (through signal on line 40) to Mark when there is no subchannel activity 2) Buffer Empty - Line 42 i) Switches from Logical One to Logical Zero when Start Buffer changes from One to Zero ii) Switches from Zero to One once the buffer has stopped at the end of subchannel activity 3) Buffer Begin - Line 40 i) Switches from Logical One to Logical Zero when the buffer's output stage is enabled ii) Switches from Zero to One once the buffer has stopped at the end of subchannel activity.

Without sub-channel activity on line 10 START BUFFER line carries Logical One and clamps Input Data line 10 to Logical One and clamps input Clock line 16 to Logical Zero this being Idle State.

BUFFER EMPTY signal then goes to Logical Zero enabling input address counter 14 and removing the clamping on lines 10 and 16.

Thereafter arrival of input data clock signals and input data cause recording of data on 8-bit addressable latch 12 as follows. Input counter 14 is activated by the input data clock on line 16 to address sequential latch cells.

When input address equals '4' a signal on line 33 to state Machine 32 causes BUFFER BEGIN signal to enable output counter 22 and output latch 26. Output Address Counter counts upward to provide cyclically sequential outputs from the cells of the 8-bit addressable latch to output latch 26 to provide data from output latch along output data line 20 to the main channel 28. The process will continue until count in 3-bit equality detector 30 is equal. Equality will occur.

a) In the normal course because due to completion of the data transmission input data clock signal has ceased to advance the input address counter 14.

b) Because the input data clock signal has overrun or underrun the output data clock by four clock cycles indicating that input data clock has overrun or underrun output data clock by four (input) clock pulses.

Equality of output and input address counters cause both BUFFER EMPTY and BUFFER BEGIN lines 42 and 40 to go to Logical One. BUFFER EMPTY to One Resets Input Address Counter 14 to 0. BUFFER BEGIN going to One resets 3-bit output counter 22 to 0 and disables output latch.

Instead of latch 12 another addressable-input, addressable-output memory device may be used which has the read and write speed to accept the input and output data clock signals.

The addressable input addressable output memory device may have any number, i.e. 'n', cells instead of eight.

Most applications will allow for equal overrun or underrun of input to output clock periods so that the output counter will read the datum cell (here the 0 cell) when the input counter is writing on the n/2 cell (cell 4 in the preferred embodiment). However if the overrun is expected to be greater or smaller than the underrun the output counter may be started when the input counter is writing or a cell after or before the n/2 cell.

Although the specific embodiment shows signalling between a sub and a main channel the device may be used for signalling from main to sub channel and between any channels where two independent clocks have similar design frequencies.

Claims (10)

1. Retiming buffer comprising an addressable latch of n stages, a cyclically operable input counter adapted to cyclically sequentially address said n stages, an input data clock adapted to control said input counter and the recording of data in said latch stages, an addressable selector for reading a selected one of said n stages, a cyclially operable output counter adapted to cause said selector to cyclically sequentially read said n stages, means adapted to provide the output of said selector as serial binary data, an output data clock adapted to control said output counter and the reading of data from said latch stages, means for starting said input clock from a predetermined datum, and means, responsive to said input counter reaching a count intermediate between 1 and n for starting said output clock from said predetermined datum.

2. Retiming buffer as claimed in claim 1 including means for disabling said buffer if the count in the input counter equals the count in the output counter.

3. Retiming buffer as claimed in claim 1 or 2 where said intermediate count is substantially n/2.

4. Retiming buffer comprising an addressable memory device of n cells, said device having a serial data input to write on a selected cell of said memory device, an input counter adapted to cyclically sequentially address said n cells, a selector connectable to read a selected cell of said memory device, an output counter adapted to cause said selector to cyclically sequentially address said n cells means responsive to a supply of serial data to the device and input data clock signals to the input counter to sequentially write said input data in said memory device cells, means responsive to output data clock signals to cause said selector to read serial binary data sequentially from said memory cells, and means responsive to the initial operation of said input counter from a datum cell over a predetermined number of cells less than n for initiating operation of said means responsive to said output clock signal by reading from said datum cell.

5. Retiming buffer as claimed in claim 4 including means for disabling said buffer if the count on the input counter eequals the count on the output buffer.

6. Retiming buffer as claimed in claim 4 or 5 wherein said predetermined number of cells is approximately n/2.

7. Retiming buffer comprising an addressable-write, addressable-read memory device having n cells, means responsive to a supply of serial input binary data and an input clock signal for writing said data on cells of said device in a sequence, commencing with a datum cell, in steps determined by said input clock, means responsive to the writing of a selected cell less than n cells in said sequence after said datum cell, for causing the start of reading of said cells, and means responsive to said start and an output clock for reading said data from cells in a device, commencing with said datum cell, in steps determined by said output clock.

8. Retiming buffer as claimed in claim 7 including means for disabling said buffer if reading and writing are concurrently occurring at the same cell.

9. Retiming buffer as claimed in claim 7 or 8 wherein said selected cell is approximately n/2 cells after said datum cell in said sequence.

10. Retiming buffer substantially as described with reference to the drawing.