RU1835546C - Data-exchange adapter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to interface different-speed data processing and transmission devices with the simultaneous receipt of write and read clock pulses. The device contains counters, switches, buffer memory, elements NOT, two combinational adders, two elements OR NOT. an AND element, code matching blocks, a register (buffer memory management), and an OR element. The operation of the device consists in organizing the exchange of information between the source and the receiver, while changing the dimension of the buffer memory makes it possible to control the transmission rate of information from the source to the receiver when information is recorded faster than reading. 1 ill.

Description

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The invention relates to the field of automation and computer technology, can be used to interface different-speed data processing and transmission devices with the simultaneous receipt of read and write signals.

The purpose of the invention is to expand the functionality of the device by controlling the dimension of the buffer memory used in the exchange of information, which allows you to affect the speed of information exchange.

The drawing shows a diagram of the device.

The device comprises a source 1 and a receiver 2 of information, switches for inputting 3 and outputting 4 information, registers 5 of buffer memory 6, counters 7 of record and 8 of reading, matching blocks of codes 9 and 10.

register 11, a group of elements NOT 12, combiners 13 and 16, elements OR NOT 14 and 17. element AND 15, element OR 18. input 19 of receiver 2 and input 20 of source 1.

The device operates as follows.

Before the process of transmitting information, source 1 sends a signal A request for reception to the input 1.9 of receiver 2. which, when ready for operation, issues a signal Ready to receive at input 20 of source 1. After that, the information source 1, proceeding from the data on the amount of buffer memory required for information exchange, enters into the register 11 a code corresponding to the number of registers 5. used during the exchange through the device settings input. Moreover, initially on the first synchronizing

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the input of the device is issued a write clock, which is fed to the clock input of the counter 7. An address code is generated in the write counter 7, which is sent to the address inputs of the information input switch 3, which connects the information input of the device to the corresponding register 5 of the buffer memory 6, Source: 1 provides information into the next register 5. When the next sync pulse is issued in case the codes match in the counter 7 of the record, the first block 9 of the code coincidence is triggered by the register 11, the signal from which resets the counter 7 of the record. The next information code is recorded in the zero register 5 of the buffer memory 6, which limits the number of registers used in the exchange of information.

If there is information in the buffer memory 6, a read clock is issued to the second synchronizing input of the device, which is assigned to the clock input of the counter 8. In the read counter 8, an address code is generated, which goes to the address inputs of the information output switch 4, which connects the corresponding buffer memory register 5 tyb to the information output of the device. The receiver 2 receives information from the next register 5. When the next clock is issued, if the codes in the read counter 8 and the register 11 coincide, the second code matching block 10 is activated, the signal from which the read counter 8 resets. The next information code is read from the zero register 5 of the buffer memory 6, which limits the number of registers used in exchanging information.

Since the recording and reading of information in the buffer memory occurs at different speeds, it is necessary to record the moments of the complete reading of the information that the buffer memory is full. To determine these moments, the address codes from the write counter 7 through the inverters 12 and from the read counter 8 are supplied to the inputs of the combiner adder 13. A code is generated at the outputs of the adder 13, which reflects the number of registers 5 of the buffer memory 6 that store unread information.

In the case when the reading of information is faster than writing, the time of the complete reading of information from the buffer memory is determined by a single code at the output of the adder 13. This code generates a read lock signal at the output of element L 15, which is transmitted to the information receiver 2. The signal will be saved until information is recorded in at least one register.

In the case when the recording of information is faster than reading, the moment of full filling of the buffer memory is determined in two ways. Firstly, it is possible that the address code on the write counter 7 is one less than the address code on the read counter 8.

This state corresponds to the zero code at the output of the adder 13. This code generates a write-lock signal at the output of the first element OR-14, which is transmitted through the OR element 18 to the information source 1. The signal will be stored until the information is at least one register was read 5. Secondly, in connection with an arbitrary number of registers 5 used in transmission, buffer memory 6 may have a situation where the address code on the write counter 7 corresponds to the maximum number used in the buffer memory 6 istra 5, and address code to the read counter 8 nu5 left. This state of the counters corresponds to the zero code at the output of the second combination adder 16, since the inverse address code of the write counter 7 is supplied to its inputs of the first term.

0, and the code from register 11 to the inputs of the second term. This code generates a write lock signal at the output of the second OR-NOT 17 element, which is transmitted through the OR element 18 to source 1.

5 claims

An interface device comprising a buffer memory, read and write counters, information input and output switches, a group of elements NOT, the first

0 combinational adder, the first element OR NOT and the element AND, moreover, the information input of the input switch information is the information input of the device, and the outputs are connected to

5 inputs of the buffer memory, the outputs of which are connected to the information inputs of the information output switch, the output of which is the information output of the device, the first synchronizing

The input of which is the clock input of the write counter, and its outputs are connected to the address inputs of the information input switch and the inputs of the elements NOT, the outputs of which are connected to the inputs of the first sent first combiner, the second clock input of the device is the clock input of the read counter, and its outputs connected to the address inputs of the information output switch and the inputs of the second term

the first combination adder, the outputs of which are connected to the inputs of the first OR-NOT element and the AND element, the output of which is the readiness output of a device readout, characterized in that, in order to expand the scope of the device, a register, first and second code matching blocks are inserted into it , a second combiner, a second OR-NOT element and an OR element, the device setup input being connected to a group of register inputs, the output of which is connected to the first groups of inputs of the First and second matching blocks dow and inputs of the first term of the second combination adder, the inputs of the second term of which are connected

with the outputs of the first combination adder, the outputs of the second combination adder are connected to the inputs of the second element OR NOT. whose output

connected to the first input of the OR element, the second input of which is connected to the output of the first OR-NOT element, the output of the OR element is the write ready output of the device, the outputs of the write counter

connected to the second group of inputs of the first block matching codes, the output of which is connected to the reset input of the write counter, the outputs of the read counter are connected to the second group of inputs of the second

a code matching block whose output is connected to a reset counter input of a read counter.