JPS49122940A - - Google Patents

Info

Publication number
JPS49122940A
JPS49122940A JP48033608A JP3360873A JPS49122940A JP S49122940 A JPS49122940 A JP S49122940A JP 48033608 A JP48033608 A JP 48033608A JP 3360873 A JP3360873 A JP 3360873A JP S49122940 A JPS49122940 A JP S49122940A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP48033608A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP48033608A priority Critical patent/JPS49122940A/ja
Priority to US453861A priority patent/US3916323A/en
Priority to CA195,878A priority patent/CA1013478A/en
Publication of JPS49122940A publication Critical patent/JPS49122940A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Shift Register Type Memory (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
JP48033608A 1973-03-26 1973-03-26 Pending JPS49122940A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP48033608A JPS49122940A (ja) 1973-03-26 1973-03-26
US453861A US3916323A (en) 1973-03-26 1974-03-22 Information storage and transfer system
CA195,878A CA1013478A (en) 1973-03-26 1974-03-25 Information storage and transfer system using shift registers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48033608A JPS49122940A (ja) 1973-03-26 1973-03-26

Publications (1)

Publication Number Publication Date
JPS49122940A true JPS49122940A (ja) 1974-11-25

Family

ID=12391164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48033608A Pending JPS49122940A (ja) 1973-03-26 1973-03-26

Country Status (3)

Country Link
US (1) US3916323A (ja)
JP (1) JPS49122940A (ja)
CA (1) CA1013478A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379337A (en) * 1976-12-23 1978-07-13 Matsushita Electric Ind Co Ltd Serial-parallel converter
JPS54527A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Control circuit for terminal unit
JPH02118827A (ja) * 1988-10-28 1990-05-07 Nec Corp バッファ回路

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033260A (en) * 1975-07-29 1977-07-05 Veb Polygraph Leipzig Kombinat Fur Polygraphische Maschinen Und Ausrustungen Control system for multi-color rotary printing machines, especially for alternate one-side and two-side printing
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
US4109243A (en) * 1976-04-26 1978-08-22 American Optical Corporation Data sequence display system and time-compression system therefor
US4070630A (en) * 1976-05-03 1978-01-24 Motorola Inc. Data transfer synchronizing circuit
US4313159A (en) * 1979-02-21 1982-01-26 Massachusetts Institute Of Technology Data storage and access apparatus
US4374428A (en) * 1979-11-05 1983-02-15 Rca Corporation Expandable FIFO system
DE3728782A1 (de) * 1987-08-28 1989-03-09 Thomson Brandt Gmbh Serielle schnittstelle
US4850000A (en) * 1987-11-05 1989-07-18 Dallas Semiconductor Corporation Gated shift register
US4879718A (en) * 1987-11-30 1989-11-07 Tandem Computers Incorporated Scan data path coupling
US5107462A (en) * 1989-02-03 1992-04-21 Digital Equipment Corporation Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3200264A (en) * 1962-05-03 1965-08-10 Martin Marietta Corp Random selector
US3708690A (en) * 1971-02-22 1973-01-02 Mos Technology Inc Shift register
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379337A (en) * 1976-12-23 1978-07-13 Matsushita Electric Ind Co Ltd Serial-parallel converter
JPS54527A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Control circuit for terminal unit
JPH02118827A (ja) * 1988-10-28 1990-05-07 Nec Corp バッファ回路

Also Published As

Publication number Publication date
US3916323A (en) 1975-10-28
CA1013478A (en) 1977-07-05

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