JPS51134570A - Semiconductor circuit unit package manufacturing process - Google Patents

Semiconductor circuit unit package manufacturing process

Info

Publication number
JPS51134570A
JPS51134570A JP50058724A JP5872475A JPS51134570A JP S51134570 A JPS51134570 A JP S51134570A JP 50058724 A JP50058724 A JP 50058724A JP 5872475 A JP5872475 A JP 5872475A JP S51134570 A JPS51134570 A JP S51134570A
Authority
JP
Japan
Prior art keywords
circuit unit
unit package
manufacturing process
semiconductor circuit
package manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50058724A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5430875B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Norio Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50058724A priority Critical patent/JPS51134570A/ja
Publication of JPS51134570A publication Critical patent/JPS51134570A/ja
Publication of JPS5430875B2 publication Critical patent/JPS5430875B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP50058724A 1975-05-19 1975-05-19 Semiconductor circuit unit package manufacturing process Granted JPS51134570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50058724A JPS51134570A (en) 1975-05-19 1975-05-19 Semiconductor circuit unit package manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50058724A JPS51134570A (en) 1975-05-19 1975-05-19 Semiconductor circuit unit package manufacturing process

Publications (2)

Publication Number Publication Date
JPS51134570A true JPS51134570A (en) 1976-11-22
JPS5430875B2 JPS5430875B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1979-10-03

Family

ID=13092438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50058724A Granted JPS51134570A (en) 1975-05-19 1975-05-19 Semiconductor circuit unit package manufacturing process

Country Status (1)

Country Link
JP (1) JPS51134570A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPS5430875B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1979-10-03

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