JPS51139778A - Electronic circuit apparatus - Google Patents

Electronic circuit apparatus

Info

Publication number
JPS51139778A
JPS51139778A JP50063905A JP6390575A JPS51139778A JP S51139778 A JPS51139778 A JP S51139778A JP 50063905 A JP50063905 A JP 50063905A JP 6390575 A JP6390575 A JP 6390575A JP S51139778 A JPS51139778 A JP S51139778A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit apparatus
dual
leads
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50063905A
Other languages
Japanese (ja)
Other versions
JPS5810857B2 (en
Inventor
Yasuo Ochiai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP50063905A priority Critical patent/JPS5810857B2/en
Publication of JPS51139778A publication Critical patent/JPS51139778A/en
Publication of JPS5810857B2 publication Critical patent/JPS5810857B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A ceramic package used for a electronic apparatus such as integrated circuit of dual in-line type, wherein a large number of leads can be effectively mounted as the number of elements increases.
COPYRIGHT: (C)1976,JPO&Japio
JP50063905A 1975-05-28 1975-05-28 Denshi Kairosouchi Expired JPS5810857B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50063905A JPS5810857B2 (en) 1975-05-28 1975-05-28 Denshi Kairosouchi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50063905A JPS5810857B2 (en) 1975-05-28 1975-05-28 Denshi Kairosouchi

Publications (2)

Publication Number Publication Date
JPS51139778A true JPS51139778A (en) 1976-12-02
JPS5810857B2 JPS5810857B2 (en) 1983-02-28

Family

ID=13242794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50063905A Expired JPS5810857B2 (en) 1975-05-28 1975-05-28 Denshi Kairosouchi

Country Status (1)

Country Link
JP (1) JPS5810857B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501564A (en) * 1982-08-10 1984-08-30 ダウテイ・エレクトロニク・コンポーネンツ・リミテツド electric circuit unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121966A (en) * 1973-03-30 1974-11-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121966A (en) * 1973-03-30 1974-11-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501564A (en) * 1982-08-10 1984-08-30 ダウテイ・エレクトロニク・コンポーネンツ・リミテツド electric circuit unit

Also Published As

Publication number Publication date
JPS5810857B2 (en) 1983-02-28

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