JPH1167978A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1167978A JPH1167978A JP9229694A JP22969497A JPH1167978A JP H1167978 A JPH1167978 A JP H1167978A JP 9229694 A JP9229694 A JP 9229694A JP 22969497 A JP22969497 A JP 22969497A JP H1167978 A JPH1167978 A JP H1167978A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- sealing resin
- lead frame
- package
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に係
り、特にその外形とパッケージの構成に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a package structure.
【０００２】[0002]
【従来の技術】従来より、半導体素子におけるパッケー
ジの構成に関する技術として数種のものが知られてい
る。図３〜図５は従来の半導体装置の構成を説明するた
めの断面図であり、各図において、１は半導体素子、２
はリードフレーム４のダイパッド、そしてダイパッド２
は接着剤３によって半導体素子１と接着される。５はリ
ードフレーム４におけるインナーリード部４aと半導体
素子１とを接続するワイヤー、６は半導体素子１，リー
ドフレーム４，ワイヤー５を全体的に覆うパッケージと
しての封止用樹脂であって、４bはリードフレーム４を
外部に導出する部位であるアウターリード(外部端子)部
である。2. Description of the Related Art Heretofore, there have been known several kinds of techniques relating to the structure of a package in a semiconductor device. 3 to 5 are cross-sectional views illustrating the configuration of a conventional semiconductor device. In each of the drawings, reference numeral 1 denotes a semiconductor element;
Is the die pad of lead frame 4 and die pad 2
Is bonded to the semiconductor element 1 by the adhesive 3. Reference numeral 5 denotes a wire for connecting the inner lead portion 4a of the lead frame 4 to the semiconductor element 1, reference numeral 6 denotes a sealing resin as a package that entirely covers the semiconductor element 1, the lead frame 4, and the wire 5, and reference numeral 4b denotes a resin. It is an outer lead (external terminal) portion that leads the lead frame 4 to the outside.
【０００３】そして、図３に示す半導体装置おいては、
通常のＱＦＰ(Quad Flad L-LeadedPackage)やＳＯＰ(Sm
all Outline L-Leaded Package)のごとく、アウターリ
ード部４bは封止用樹脂６の側面から引き出され、アウ
ターリード部４bの端部が曲げ加工されて、その端面が
封止用樹脂６の底面よりも少し下面に位置するように設
けられている。In the semiconductor device shown in FIG.
Normal QFP (Quad Flad L-Leaded Package) or SOP (Sm
As in all Outline L-Leaded Package), the outer lead portion 4b is pulled out from the side surface of the sealing resin 6, the end portion of the outer lead portion 4b is bent, and the end surface is formed from the bottom surface of the sealing resin 6. Is also provided slightly below.
【０００４】図４に示す半導体装置おいては、インナー
リード部４aを少し下に曲げて、封止用樹脂６の底面に
おける端部にアウターリード部４bを露出するようにし
ている。[0004] In the semiconductor device shown in FIG. 4, the inner lead portion 4 a is bent slightly downward so that the outer lead portion 4 b is exposed at the end of the bottom surface of the sealing resin 6.
【０００５】図５に示す半導体装置おいては、封止用樹
脂６の底面にダイパッド２の裏面と、アウターリード部
4bを含むリードフレーム４の底面全体を露出するように
している。In the semiconductor device shown in FIG. 5, the back surface of the die pad 2 and the outer lead portion
The entire bottom surface of the lead frame 4 including the lead frame 4b is exposed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記の
ような従来の半導体装置のパッケージ、すなわち封止用
樹脂６の構造においては、下記のような問題があった。However, the conventional semiconductor device package as described above, that is, the structure of the sealing resin 6, has the following problems.
【０００７】すなわち、図３に示す半導体装置では、パ
ッケージサイズが大きくなるという問題があり、また、
図４に示す半導体装置では、インナーリード部４aを曲
げる必要があり、さらに本装置をプリント基板に半田付
けする際に、パッケージ底面が平坦な面であるため、余
分な半田の逃げ場がなく、ショート不良の原因となって
いた。さらに、図５においては、小型化には適している
が前記と同様に半田の逃げ場がないことと、ダイパット
裏面も露出しているためダイパット側面からの水分が入
りやすく耐湿性に問題があった。That is, the semiconductor device shown in FIG. 3 has a problem that the package size becomes large.
In the semiconductor device shown in FIG. 4, it is necessary to bend the inner lead portion 4a, and when soldering this device to a printed circuit board, since the bottom surface of the package is a flat surface, there is no escape area for extra solder, and there is no short circuit. It was the cause of the failure. Further, in FIG. 5, there is no escape for solder as described above, which is suitable for miniaturization, and since the back surface of the die pad is also exposed, there is a problem in that moisture from the side surface of the die pad easily enters and moisture resistance is high. .
【０００８】そして上記の問題は、近年において、集積
度を増す半導体集積回路にあって、より重要な問題とな
り、また実装信頼性の向上が要望される中でその解決が
強く望まれている。The above-mentioned problem has become more important in recent years in semiconductor integrated circuits with an increasing degree of integration, and there is a strong demand for an improvement in mounting reliability while demands for improvement in mounting reliability are increasing.
【０００９】本発明は、前記従来の問題を解決するもの
であり、パッケージが小型化し、耐湿性に優れ、しかも
実装上の信頼性が向上する半導体装置を提供することを
目的とする。An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device in which a package is reduced in size, excellent in moisture resistance and improved in mounting reliability.
【００１０】[0010]
【課題を解決するための手段】前記目的を達成するた
め、本発明は、封止用樹脂の底面を突起させて、封止用
樹脂の底面とリードフレームにおけるアウターリード部
分とに段差を設け、封止用樹脂の底面においてアウター
リード部分の底面のみを露出させたものであり、この構
成によって、封止用樹脂によるパッケージの小型化が図
れ、アウターリード部分の底面のみを露出させたことに
よって耐湿性が向上し、しかも封止用樹脂の突起を利用
することにより、プリント基板への実装上の信頼性を向
上させることができる半導体装置を提供することが可能
になる。In order to achieve the above object, the present invention provides a method in which a bottom surface of a sealing resin is projected to provide a step between the bottom surface of the sealing resin and an outer lead portion of a lead frame. Only the bottom surface of the outer lead portion is exposed on the bottom surface of the sealing resin. With this configuration, the size of the package can be reduced by using the sealing resin. By using the projections of the sealing resin, the semiconductor device can be provided with improved reliability and reliability in mounting on a printed circuit board.
【００１１】[0011]
【発明の実施の形態】本発明の請求項１記載の発明は、
リードフレームのダイパッド上に半導体素子を接着剤に
よって固定し、半導体素子をリードフレームのインナー
リード部分にワイヤーによって接続して、全体を封止用
樹脂によって覆ってなる半導体装置であって、前記封止
用樹脂の底面を突起させて、封止用樹脂の底面と前記リ
ードフレームのアウターリード部分とに段差を設け、前
記封止用樹脂の底面において前記アウターリード部分の
底面のみを露出させたことを特徴とし、この構成によっ
て、封止用樹脂によるパッケージを小型化することがで
き、しかもダイパッドとインナーリード部分がパッケー
ジによって覆われるため、当該部材の防湿性が向上し、
さらにプリント基板への半田付けもアウターリード部分
とパッケージ間に段差が存在するためショート不良にな
りにくく、実装時にその段差部分の突起を位置基準など
に使用することによって、実装の整合性が高まる。BEST MODE FOR CARRYING OUT THE INVENTION
A semiconductor device comprising: fixing a semiconductor element on a die pad of a lead frame by an adhesive; connecting the semiconductor element to an inner lead portion of the lead frame by a wire; and covering the whole with a sealing resin. Projecting the bottom surface of the sealing resin, providing a step between the bottom surface of the sealing resin and the outer lead portion of the lead frame, and exposing only the bottom surface of the outer lead portion on the bottom surface of the sealing resin. Characteristically, with this configuration, the package made of the sealing resin can be miniaturized, and the die pad and the inner lead portion are covered by the package, so that the moisture resistance of the member is improved,
Further, soldering to a printed circuit board is unlikely to cause a short circuit failure due to the presence of a step between the outer lead portion and the package, and the mounting consistency is improved by using the projection of the step portion as a position reference during mounting.
【００１２】以下、本発明の実施形態を図面を用いて詳
細に説明する。なお、図３〜図５に基づいて説明した部
材に対応する部材には同一符号を付して詳しい説明は省
略する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Members corresponding to those described with reference to FIGS. 3 to 5 are denoted by the same reference numerals, and detailed description is omitted.
【００１３】図１は本発明の一実施形態を説明するため
の半導体装置の断面図であり、具体例として、3.5mm×
3.5mmの半導体素子１を、銀ペーストの接着剤３によっ
て、4.0mm×4.0mmのリードフレーム４のダイパッド２に
接着する。そして直径25μmの金線からなるワイヤー５
を用いて半導体素子１とリードフレーム４のインナーリ
ード４aとを接続する。その後、エポキシ系樹脂などの
封止用樹脂６によって装置全体のパッケージを形成する
ためトランスファ成型を行う。FIG. 1 is a cross-sectional view of a semiconductor device for explaining one embodiment of the present invention.
A 3.5 mm semiconductor element 1 is bonded to a 4.0 mm × 4.0 mm lead frame 4 die pad 2 by a silver paste adhesive 3. And a wire 5 consisting of a gold wire with a diameter of 25 μm
Is used to connect the semiconductor element 1 to the inner lead 4a of the lead frame 4. Thereafter, transfer molding is performed to form a package of the entire device using a sealing resin 6 such as an epoxy resin.
【００１４】このとき、封止用樹脂６の底面の略中央に
突起部10が形成されるようにする。その本例では突起部
10を幅5.5mm×長さ5.5mm，高さ0.2mmと設定した。突起
部10の両側におけるリードフレーム４のアウターリード
４bの底面における露出長さＳは封止用樹脂６の端面か
ら0.65mmとなった。そして、封止用樹脂６の端面よりは
み出したアウターリード４bを金型にて切断することに
よって、図１に示すような半導体装置が得られる。At this time, the projection 10 is formed substantially at the center of the bottom surface of the sealing resin 6. In this example, the protrusion
10 was set to 5.5 mm wide x 5.5 mm long and 0.2 mm high. The exposed length S on the bottom surface of the outer lead 4b of the lead frame 4 on both sides of the protrusion 10 was 0.65 mm from the end surface of the sealing resin 6. Then, the outer lead 4b protruding from the end face of the sealing resin 6 is cut by a mold, whereby the semiconductor device as shown in FIG. 1 is obtained.
【００１５】なお、リードフレーム４のインナーリード
４aとアウターリード４bに対する外装メッキとしてパラ
ジウムメッキなどを施すが、これに限定されず、例えば
インナーリード４aには銀メッキを施し、アウターリー
ド４bには半田メッキを行ったものを用いてもよい。The inner lead 4a and the outer lead 4b of the lead frame 4 are plated with palladium as an exterior plating, but are not limited thereto. For example, the inner lead 4a is plated with silver and the outer lead 4b is soldered. Plated material may be used.
【００１６】図２は図１に示す半導体装置をプリント基
板に実装したときの状態を説明するための断面図であ
り、20はプリント基板、21はプリント基板20に設けられ
た凹部、22はプリント基板20の表面に設けられた電極、
23は半田ペーストである。FIG. 2 is a cross-sectional view for explaining a state in which the semiconductor device shown in FIG. 1 is mounted on a printed circuit board. Reference numeral 20 denotes a printed circuit board; 21, a concave portion provided on the printed circuit board 20; An electrode provided on the surface of the substrate 20,
23 is a solder paste.
【００１７】プリント基板20において、図１に示す半導
体装置における突起部10が、プリント基板20の上面に当
たらないように、幅6.0mm，長さ6.0mm，深さ0.22mmの凹
部21を予め設け、そのプリント基板20の電極22に半田ペ
ースト23をスクリーン印刷によって塗布する。そして図
１に示す半導体装置を位置合わせをしてプリント基板20
に搭載する。しかる後、エアーリフローによって半田付
けを行い、半導体装置のアウターリード４bとプリント
基板20の電極22とを電気的に接続かつ固定させることに
よって実装が完了する。On the printed circuit board 20, a recess 21 having a width of 6.0 mm, a length of 6.0 mm and a depth of 0.22 mm is provided in advance so that the projection 10 in the semiconductor device shown in FIG. Then, a solder paste 23 is applied to the electrodes 22 of the printed circuit board 20 by screen printing. Then, the semiconductor device shown in FIG.
To be mounted on. Thereafter, soldering is performed by air reflow, and the outer leads 4b of the semiconductor device and the electrodes 22 of the printed circuit board 20 are electrically connected and fixed to complete the mounting.
【００１８】[0018]
【発明の効果】以上説明したように、本発明に係わる半
導体装置によれば、パッケージが小型化できるととも
に、ダイパッドおよびインナーリードの先端が樹脂で覆
われるため耐湿性を十分に確保することができる。As described above, according to the semiconductor device of the present invention, the package can be reduced in size, and the tip of the die pad and the inner lead is covered with the resin, so that sufficient moisture resistance can be ensured. .
【００１９】また、実装時のプリント基板における半田
付けもアウターリードとパッケージ間には突起部による
段差があるため、ショート不良になりにくく、さらに凹
部を持つプリント基板との組み合わせによって、整合性
の良い実装が可能になるなどの実用的な効果が大であ
る。In addition, soldering on the printed circuit board at the time of mounting has a step due to the projection between the outer lead and the package, so that a short circuit is unlikely to occur. Practical effects such as mounting are possible.
【図１】本発明の一実施形態を説明するための半導体装
置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device for describing an embodiment of the present invention.
【図２】図１に示す半導体装置をプリント基板に実装し
たときの状態を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining a state when the semiconductor device shown in FIG. 1 is mounted on a printed circuit board.
【図３】従来の半導体装置の構成を説明するための断面
図である。FIG. 3 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
【図４】従来の半導体装置の構成を説明するための断面
図である。FIG. 4 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
【図５】従来の半導体装置の構成を説明するための断面
図である。FIG. 5 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
１…半導体素子、 ２…ダイパッド、 ３…接着剤、
４…リードフレーム、４a…インナーリード、 ４b…ア
ウターリード、 ５…ワイヤー、 ６…封止用樹脂、
10…封止用樹脂の突起部、 20…プリント基板、 21…
プリント基板の凹部、 22…電極、 23…半田ペース
ト。1 ... semiconductor element, 2 ... die pad, 3 ... adhesive,
4: Lead frame, 4a: inner lead, 4b: outer lead, 5: wire, 6: resin for sealing,
10 ... protrusion of sealing resin, 20 ... printed circuit board, 21 ...
Concave part of printed circuit board, 22 ... electrode, 23 ... solder paste.
Claims (1)
素子を接着剤によって固定し、半導体素子をリードフレ
ームのインナーリード部分にワイヤーによって接続し
て、全体を封止用樹脂によって覆ってなる半導体装置で
あって、前記封止用樹脂の底面を突起させて、封止用樹
脂の底面と前記リードフレームのアウターリード部分と
に段差を設け、前記封止用樹脂の底面において前記アウ
ターリード部分の底面のみを露出させたことを特徴とす
る半導体装置。1. A semiconductor device comprising a semiconductor element fixed on a die pad of a lead frame by an adhesive, the semiconductor element connected to an inner lead portion of the lead frame by a wire, and the whole covered with a sealing resin. By projecting the bottom surface of the sealing resin, a step is provided between the bottom surface of the sealing resin and the outer lead portion of the lead frame, and only the bottom surface of the outer lead portion is formed on the bottom surface of the sealing resin. A semiconductor device characterized by being exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9229694A JPH1167978A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9229694A JPH1167978A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1167978A true JPH1167978A (en) | 1999-03-09 |
Family
ID=16896252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9229694A Pending JPH1167978A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1167978A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753599B2 (en) | 2001-02-12 | 2004-06-22 | Samsung Electronics Co., Ltd. | Semiconductor package and mounting structure on substrate thereof and stack structure thereof |
| JP2015056540A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
-
1997
- 1997-08-26 JP JP9229694A patent/JPH1167978A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753599B2 (en) | 2001-02-12 | 2004-06-22 | Samsung Electronics Co., Ltd. | Semiconductor package and mounting structure on substrate thereof and stack structure thereof |
| JP2015056540A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |