JP2001257304A - Semiconductor device and method of mounting the same - Google Patents

Semiconductor device and method of mounting the same

Info

Publication number
JP2001257304A
JP2001257304A JP2000066526A JP2000066526A JP2001257304A JP 2001257304 A JP2001257304 A JP 2001257304A JP 2000066526 A JP2000066526 A JP 2000066526A JP 2000066526 A JP2000066526 A JP 2000066526A JP 2001257304 A JP2001257304 A JP 2001257304A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
lead portion
mounting
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000066526A
Other languages
Japanese (ja)
Inventor
Katsuki Uchiumi
勝喜 内海
Toru Nomura
徹 野村
Shigeji Oida
成志 老田
Masaji Funakoshi
正司 舩越
Noboru Tani
昇 谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000066526A priority Critical patent/JP2001257304A/en
Publication of JP2001257304A publication Critical patent/JP2001257304A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the problem in which when bonding a mount substrate and lead sections planarly disposed on a bottom face of a semiconductor device through soldering, sufficient mounting strength cannot be achieved since there are only a few bonding points. SOLUTION: A recessed part 9 is formed on a side face of each lead section 2 of QFN. When bonding the lead sections 2 on the substrate using solder or the like to mount them on the substrate, a bond enters not only the bottom face and side face of the lead sections 2 but also the recessed part 9, which increases the number of bonding points. Besides increase in bonding points, the bond has an anchoring effect against the recessed part 9, so that the mounting strength can be increased markedly and an influence due to stresses applied in some conditions in which the semiconductor device is used can be eliminated, thereby the reliability of a secondary mounting can be increased.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は底面に面配置された
リード部等の電極端子がプリント基板上に接合材を用い
て実装するに適した半導体装置およびその実装方法に関
するものであり、特にその基板実装において、実装強度
を向上させ、二次実装の信頼性を向上させることができ
る半導体装置およびその実装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which electrode terminals such as leads arranged on the bottom surface are suitable for mounting on a printed circuit board using a bonding material, and a mounting method thereof. The present invention relates to a semiconductor device capable of improving the mounting strength and improving the reliability of secondary mounting in board mounting, and a method for mounting the same.

【0002】[0002]

【従来の技術】従来、配線が形成されたプリント基板上
に対して半導体装置を実装する方法として、半導体装置
の底面に配置されたリード部をハンダを接合材として用
いて実装していた。
2. Description of the Related Art Conventionally, as a method of mounting a semiconductor device on a printed circuit board on which wiring has been formed, a lead portion disposed on the bottom surface of the semiconductor device has been mounted using solder as a bonding material.

【0003】以下、従来の半導体装置およびその実装方
法について、図面を参照しながら説明する。
Hereinafter, a conventional semiconductor device and a mounting method thereof will be described with reference to the drawings.

【0004】まず図5、図6は従来のプリント基板に実
装される半導体装置を示す図であり、図5(a)は平面
図、図5(b)は側面図、図5(c)は底面図である。
図6(a)は内部構成を示した平面透視図、図6(b)
は図6(a)のA−A1箇所の断面図である。
FIGS. 5 and 6 show a conventional semiconductor device mounted on a printed circuit board. FIG. 5A is a plan view, FIG. 5B is a side view, and FIG. It is a bottom view.
FIG. 6A is a perspective plan view showing the internal configuration, and FIG.
FIG. 7 is a cross-sectional view taken along the line AA1 in FIG.

【0005】従来の基板実装される半導体装置は、図5
に示すように、パッケージを構成する封止樹脂1の底面
と側面にリード部2が配列され、封止樹脂1の端部に吊
りリード部3の末端部が露出した構造を有している。具
体的には図6に示すように、半導体素子4と、その半導
体素子4を支持したダイパッド部5と、ダイパッド部5
をその先端部で支持した吊りリード部3と、ダイパッド
部5に先端部が配置されたリード部2と、そのリード部
2と半導体素子4とを電気的に接続した金属細線6と、
吊りリード部3の末端部およびリード部2の一側面と底
面とを露出させ、半導体素子4、ダイパッド部5、金属
細線6の外囲を封止した封止樹脂1とよりなる半導体装
置である。なお、図6において、半導体素子4は破線で
示している。
A conventional semiconductor device mounted on a substrate is shown in FIG.
As shown in FIG. 1, the leads 2 are arranged on the bottom and side surfaces of the sealing resin 1 constituting the package, and the end of the suspension lead 3 is exposed at the end of the sealing resin 1. Specifically, as shown in FIG. 6, a semiconductor element 4, a die pad portion 5 supporting the semiconductor element 4, and a die pad portion 5
, A lead portion 2 having a tip portion disposed on a die pad portion 5, a thin metal wire 6 electrically connecting the lead portion 2 and the semiconductor element 4,
A semiconductor device comprising a sealing resin 1 in which a terminal portion of a suspension lead portion 3 and one side surface and a bottom surface of a lead portion 2 are exposed, and a semiconductor element 4, a die pad portion 5, and a thin metal wire 6 are sealed. . In FIG. 6, the semiconductor element 4 is shown by a broken line.

【0006】以上のように構成された従来の半導体装置
をプリント基板等の実装基板に実装するには、図7の実
装構造を示す断面図に示すように、半導体装置のリード
部2の底面および側面と実装基板7の電極、配線等の接
続箇所とをハンダ8を用いて実装するものである。
In order to mount the conventional semiconductor device configured as described above on a mounting board such as a printed board, as shown in a cross-sectional view showing a mounting structure of FIG. The side surface and the connection portions of the mounting board 7 such as electrodes and wiring are mounted using solder 8.

【0007】つまり従来の半導体装置の実装において
は、半導体装置の底面に配列されたリード部2の底面と
側面と実装基板7とをハンダ8で接合するというもので
あり、リード部2の底面、側面で実装するものであっ
た。
In other words, in the conventional mounting of the semiconductor device, the bottom and side surfaces of the lead portions 2 arranged on the bottom surface of the semiconductor device and the mounting substrate 7 are joined with the solder 8. It was implemented on the side.

【0008】[0008]

【発明が解決しようとする課題】しかしながら従来の半
導体装置では、リード部の底面、側面で実装するもので
あり、基板実装において実装強度が十分でない場合があ
り、より接合強度を向上させた実装構造が必要であっ
た。すなわち従来は半導体装置の底面に面配置されたリ
ード部の底面および露出した一側面と実装基板とをハン
ダにより接合しているものであり、接合箇所が少ないた
め実装強度が不十分であるという課題があった。特に基
板実装後の使用状態によっては、応力が印加される場合
があり、そのような過酷な使用状況では従来の実装構造
では対応できない恐れがあった。
However, the conventional semiconductor device is mounted on the bottom and side surfaces of the lead portion, and the mounting strength may not be sufficient for mounting on a substrate. Was needed. That is, conventionally, the bottom surface and one exposed side surface of the lead portion arranged on the bottom surface of the semiconductor device are joined to the mounting board by soldering, and the mounting strength is insufficient because the number of joints is small. was there. Particularly, stress may be applied depending on the use state after mounting on the board, and there is a possibility that the conventional mounting structure cannot cope with such severe use conditions.

【0009】またQFP(Quad Flat Pac
kage)等の半導体装置のように、リード部がパッケ
ージ本体から突出している場合は、基板実装時にリード
部の底面と各側面とをハンダ等の接合材により接合で
き、接合箇所が確保でき、相当の実装強度を得ることが
できるが、前記したリード部が面配置されたような最近
のQFN(Quad Flat Non−leaded
Package)では実装強度の向上が要望されてい
た。またQFN型の半導体装置のリード部の幅は概ね2
00[μm]であり、微少な幅であるため、実装強度を
向上させる必要がある。
Further, QFP (Quad Flat Pac)
In the case where the lead portion protrudes from the package body as in the case of a semiconductor device such as a semiconductor device such as a semiconductor device, the bottom surface and each side surface of the lead portion can be joined with a joining material such as solder at the time of mounting on a substrate, so that a joining portion can be secured. However, recent QFNs (Quad Flat Non-leaded) in which the above-described leads are arranged on the surface can be obtained.
(Package) demanded an improvement in mounting strength. The width of the lead portion of the QFN type semiconductor device is approximately 2
Since it is 00 [μm] and the width is very small, it is necessary to improve the mounting strength.

【0010】本発明は前記従来の半導体装置の実装構造
での課題を解決するとともに、最近のQFN型の半導体
装置において、飛躍的に実装強度を向上させ、使用状況
による影響を解消し、二次実装の信頼性を向上させるこ
とができる半導体装置およびその実装方法を提供するも
のである。
The present invention solves the above-mentioned problems in the conventional mounting structure of a semiconductor device, and in a recent QFN type semiconductor device, dramatically improves the mounting strength and eliminates the influence of the use situation, An object of the present invention is to provide a semiconductor device capable of improving the reliability of mounting and a mounting method thereof.

【0011】[0011]

【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置は、底面に電気的接続用の
リード部の底面が配列され、側面に前記リード部の外方
の一側面が配列された半導体装置であって、リード部の
前記一側面が凹部を有し、前記凹部を構成する凸部が前
記リード部表面に形成されたメッキ層による凸部である
半導体装置である。
In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention is arranged such that a bottom surface of a lead portion for electrical connection is arranged on a bottom surface, and one side of the lead portion outside the lead portion is arranged on a side surface. A semiconductor device in which side surfaces are arranged, wherein the one side surface of the lead portion has a concave portion, and the convex portion forming the concave portion is a convex portion formed by a plating layer formed on the surface of the lead portion. .

【0012】また、本発明の半導体装置は、半導体素子
と、前記半導体素子を支持したダイパッド部と、前記ダ
イパッド部をその先端部で支持した吊りリード部と、前
記ダイパッド部に先端部が配置されたリード部と、前記
リード部と前記半導体素子とを電気的に接続した接続手
段と、少なくとも前記リード部の一側面と底面とを露出
させ、前記半導体素子、前記ダイパッド部、前記接続手
段の外囲を封止した封止樹脂とよりなる半導体装置であ
って、前記リード部の側面が凹部を有し、前記凹部を構
成する凸部が前記リード部表面に形成されたメッキ層に
よる凸部である半導体装置である。
Further, in the semiconductor device according to the present invention, a semiconductor element, a die pad portion supporting the semiconductor element, a suspension lead portion supporting the die pad portion at a distal end thereof, and a distal end disposed at the die pad portion are provided. A connecting portion electrically connecting the lead portion and the semiconductor element, and exposing at least one side surface and a bottom surface of the lead portion to the outside of the semiconductor device, the die pad portion, and the connecting means. A semiconductor device comprising a sealing resin sealing an enclosure, wherein a side surface of the lead portion has a concave portion, and a convex portion forming the concave portion is a convex portion formed by a plating layer formed on a surface of the lead portion. A certain semiconductor device.

【0013】具体的には、リード部の表面に形成された
メッキ層は、パラジウム層を有した積層メッキ層である
半導体装置である。
More specifically, the plating device formed on the surface of the lead portion is a semiconductor device that is a laminated plating layer having a palladium layer.

【0014】また、リード部の側面の凹部は、20[μ
m]〜40[μm]である半導体装置である。
The recess on the side surface of the lead portion has a size of 20 μm.
m] to 40 [μm].

【0015】また本発明の半導体装置の実装方法は、半
導体素子と、前記半導体素子を支持したダイパッド部
と、前記ダイパッド部をその先端部で支持した吊りリー
ド部と、前記ダイパッド部に先端部が配置されたリード
部と、前記リード部と前記半導体素子とを電気的に接続
した接続手段と、少なくとも前記リード部の外方の一側
面と底面とを露出させ、前記半導体素子、前記ダイパッ
ド部、前記接続手段の外囲を封止した封止樹脂とよりな
り、リード部の外方の一側面が凹部を有し、前記凹部を
構成する凸部が前記リード部表面に形成されたメッキ層
による凸部である半導体装置の実装方法であって、実装
基板に対して前記半導体装置の少なくとも前記リード部
の一側面と底面とを接合材で実装するとともに、前記リ
ード部の前記凹部に接合材を入り込ませて、前記リード
部の底面、側面および側面の内側で接合する半導体装置
の実装方法である。
Further, in the method of mounting a semiconductor device according to the present invention, there is provided a semiconductor device, a die pad portion supporting the semiconductor element, a suspension lead portion supporting the die pad portion at a tip end thereof, and a tip end portion provided at the die pad portion. The arranged lead portion, connection means for electrically connecting the lead portion and the semiconductor element, and exposing at least one outer side surface and bottom surface of the lead portion, the semiconductor element, the die pad portion, It is made of a sealing resin that seals the outer periphery of the connecting means, and one side surface outside the lead portion has a concave portion, and the convex portion forming the concave portion is formed by a plating layer formed on the surface of the lead portion. A method of mounting a semiconductor device which is a convex portion, wherein at least one side surface and a bottom surface of the lead portion of the semiconductor device are mounted on a mounting substrate with a bonding material, and the semiconductor device is mounted on the concave portion of the lead portion. By entering the mixed material, the bottom surface of the lead portion, a mounting method of a semiconductor device to be bonded on the inside of the side surface and the side surface.

【0016】前記構成の通り、リード部の外方の一側面
が凹部を有しているので、半導体装置の底面に配置され
たリード部の露出した底面部と外方の一側面とを接合材
により実装基板に接合して実装する構造に加えて、外方
の一側面の凹部にも接合材が入り込むので、接合箇所が
増加するため、飛躍的に実装強度を向上させ、使用状況
により印加される応力による影響を解消し、二次実装の
信頼性を向上させることができるものである。
As described above, since the outer side surface of the lead portion has the concave portion, the exposed bottom portion of the lead portion and the outer side surface disposed on the bottom surface of the semiconductor device are joined to each other by a bonding material. In addition to the structure that is joined to the mounting board and mounted, the joining material also enters the recess on one side of the outside, so the number of joints increases, so the mounting strength is dramatically improved and it is applied depending on the usage situation This eliminates the influence of the stresses and improves the reliability of the secondary mounting.

【0017】[0017]

【発明の実施の形態】以下、本発明の半導体装置および
その実装方法の一実施形態について、図面を参照しなが
ら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a method for mounting the same will be described below with reference to the drawings.

【0018】まず図1、図2は本実施形態におけるプリ
ント基板に実装される半導体装置を示す図であり、図1
(a)は平面図、図1(b)は底面図である。図2
(a)は内部構成を示した平面透視図、図2(b)は図
2(a)のB−B1箇所の断面図である。
FIGS. 1 and 2 show a semiconductor device mounted on a printed circuit board according to this embodiment.
1A is a plan view, and FIG. 1B is a bottom view. FIG.
2A is a perspective plan view showing the internal configuration, and FIG. 2B is a cross-sectional view taken along a line BB1 in FIG. 2A.

【0019】本実施形態の基板実装される半導体装置
は、図1に示すように、パッケージを構成する封止樹脂
1の底面の端部にリード部2がその底面と外方の一側面
を露出して配列され、封止樹脂1の各角部の端部には吊
りリード部3の末端部が露出した構造を有している。
As shown in FIG. 1, in the semiconductor device mounted on a substrate according to the present embodiment, a lead portion 2 exposes the bottom surface and one outer side surface at the end of the bottom surface of a sealing resin 1 constituting a package. The end of each of the corners of the sealing resin 1 has a structure in which the end of the suspension lead 3 is exposed.

【0020】具体的には図2に示すように、半導体素子
4と、その半導体素子4を支持したダイパッド部5と、
ダイパッド部5をその先端部で支持した吊りリード部3
と、ダイパッド部5に先端部が配置されたリード部2
と、そのリード部2と半導体素子4とを電気的に接続し
た金属細線6と、少なくとも吊りリード部3の末端部お
よびリード部2の一側面と底面とを露出させ、半導体素
子4、ダイパッド部5、金属細線6の外囲を封止した封
止樹脂1とよりなるQFN型の半導体装置である。また
吊りリード部3は段差部(折り曲げ部)を有し、ダイパ
ッド部5がリード部2に対してアップセットされた構造
を有しているものである。したがってダイパッド部5の
底面領域にはアップセット分の厚みで封止樹脂1が存在
しているものである。また、リード部2、吊りリード部
3の底面は、50[μm]程度の僅かな突出量で封止樹
脂1の面から突出して露出しているものである。なお、
図2において、半導体素子4は破線で示している。
More specifically, as shown in FIG. 2, a semiconductor element 4 and a die pad 5 supporting the semiconductor element 4 are provided.
Suspended lead 3 supporting die pad 5 at its tip
And a lead portion 2 having a tip portion disposed on a die pad portion 5.
And a thin metal wire 6 electrically connecting the lead portion 2 and the semiconductor element 4, and at least an end portion of the suspension lead portion 3 and one side surface and a bottom surface of the lead portion 2 are exposed, and the semiconductor element 4 and the die pad portion are exposed. 5, a QFN-type semiconductor device comprising a sealing resin 1 sealing the outer periphery of the fine metal wire 6. Further, the suspension lead portion 3 has a step portion (bent portion), and has a structure in which the die pad portion 5 is set up with respect to the lead portion 2. Therefore, the sealing resin 1 is present in the bottom region of the die pad portion 5 in a thickness corresponding to the upset. Further, the bottom surfaces of the lead portion 2 and the suspension lead portion 3 are projected and exposed from the surface of the sealing resin 1 by a slight protrusion amount of about 50 [μm]. In addition,
In FIG. 2, the semiconductor element 4 is indicated by a broken line.

【0021】そして本実施形態の半導体装置は、図3に
示すように、リード部2のパッケージ外に露出した側面
が凹部9を有しているものである。図3(a)は半導体
装置の側面図であり、図3(b)は図3(a)の円内の
拡大した斜視側面図である。図示するように、本実施形
態の半導体装置のリード部2は、その露出した側面に凹
部9を有し、凹部9の深さは20[μm]〜40[μ
m]であり、本実施形態では30[μm]としている。
As shown in FIG. 3, the semiconductor device of the present embodiment has a recess 9 on the side of the lead 2 exposed outside the package. FIG. 3A is a side view of the semiconductor device, and FIG. 3B is an enlarged perspective side view in a circle of FIG. 3A. As shown, the lead portion 2 of the semiconductor device of the present embodiment has a concave portion 9 on the exposed side surface, and the depth of the concave portion 9 is 20 [μm] to 40 [μ].
m], and is 30 [μm] in the present embodiment.

【0022】本実施形態の半導体装置は、リード部2の
側面には凹部9が形成されているので、基板実装の際、
ハンダ等の接合材を用いて接合する際、リード部2の底
面と側面に加えて、凹部9にも接合材が入り込むので、
接合箇所の増加とともに、凹部に対する接合材のアンカ
ー効果により、飛躍的に実装強度を向上させ、使用状況
により印加される応力による影響を解消し、二次実装の
信頼性を向上させることができるものである。
In the semiconductor device according to the present embodiment, since the concave portion 9 is formed on the side surface of the lead portion 2, when the substrate is mounted,
When bonding using a bonding material such as solder, the bonding material enters the recess 9 in addition to the bottom and side surfaces of the lead portion 2.
With an increase in the number of joints, the anchoring effect of the joining material on the concave part dramatically improves the mounting strength, eliminates the effects of stress applied depending on the usage conditions, and improves the reliability of secondary mounting It is.

【0023】リード部2の側面に対して凹部9を形成す
る方法としては、半導体装置を形成した後に、エッチン
グ溶液として硫酸系溶液を用い、そのエッチング液にリ
ード部2を浸漬し、リード部2の側面の内部をエッチン
グしてリード部2を構成しているリード基材を部分的に
除去することにより可能である。エッチング液に浸漬す
る条件としては、リード基材の材質、形成する凹部の深
さにより設定する。また凹部9の形状は、本実施形態で
はコの字状の箱形の凹部としているが、U字状、V字状
の凹部でもよく、エッチング条件の調整により可能であ
る。
As a method of forming the concave portion 9 on the side surface of the lead portion 2, after forming a semiconductor device, a sulfuric acid-based solution is used as an etching solution, and the lead portion 2 is immersed in the etching solution. This can be achieved by etching the inside of the side surface of the lead portion to partially remove the lead base material constituting the lead portion 2. Conditions for immersion in the etching solution are set according to the material of the lead base material and the depth of the concave portion to be formed. In the present embodiment, the shape of the concave portion 9 is a U-shaped box-shaped concave portion. However, the concave portion 9 may be a U-shaped or V-shaped concave portion, and can be adjusted by adjusting etching conditions.

【0024】また本実施形態の半導体装置は、リードフ
レームの基材として銅(Cu)材を用い、そのCu材に
対して、第1層としてニッケル(Ni)、第2層として
パラジウム(Pd)、第3層(最上層)として極薄厚の
金(Au)がメッキされて積層メッキされているもので
ある。そのため、エッチング液にリード部2を浸漬した
場合には、エッチングレートの違いにより、エッチング
液と直接に接触するリード基材(Cu)がエッチングさ
れることにより、エッチングレートの違いが作用し、リ
ード部2の側面に凹部9が形成されるものである。した
がって凹部9を構成する周辺部、すなわち凸部は、概ね
リード部2の表面にメッキされた積層メッキの層であ
り、メッキ層がエッチングされずに残存するため、凹部
9を形成するものである。
In the semiconductor device of this embodiment, a copper (Cu) material is used as a base material of a lead frame, and nickel (Ni) is used as a first layer and palladium (Pd) is used as a second layer. And a third layer (uppermost layer) plated with ultra-thin gold (Au) and laminated and plated. Therefore, when the lead portion 2 is immersed in the etching solution, the lead material (Cu) that is in direct contact with the etching solution is etched due to the difference in etching rate, and the difference in etching rate acts. The recess 9 is formed on the side surface of the portion 2. Therefore, the peripheral portion constituting the concave portion 9, that is, the convex portion is a layer of the multilayer plating generally plated on the surface of the lead portion 2, and the concave portion 9 is formed since the plated layer remains without being etched. .

【0025】そしてリードフレームとして、基材に銅
(Cu)材を用い、そのCu材に対して、第1層として
ニッケル(Ni)、第2層としてパラジウム(Pd)、
第3層(最上層)として極薄厚の金(Au)がメッキさ
れて積層メッキが形成されたものを用いた場合、エッチ
ング液としては硫酸系溶液が好適である。
As a lead frame, a copper (Cu) material is used as a base material, and nickel (Ni) as a first layer, palladium (Pd) as a second layer,
When the third layer (uppermost layer) is formed by plating ultra-thin gold (Au) to form a multilayer plating, a sulfuric acid-based solution is preferable as the etchant.

【0026】なお、リード部2の側面(端面)は製造時
の製品分離工程で、切断により積層メッキ層とともにC
u基材が露出している。そのため、リード部2の側面で
エッチングレートの違いが生じるものである。
The side surface (end surface) of the lead portion 2 is cut along with the laminated plating layer by cutting in a product separation process during manufacturing.
u substrate is exposed. Therefore, a difference in etching rate occurs on the side surface of the lead portion 2.

【0027】以上のように構成された半導体装置をプリ
ント基板等の実装基板に実装するには、図4の実装構造
を示す断面図に示すように、半導体装置底面のリード部
2の底面および外方の一側面と実装基板7の電極、配線
等の接続箇所とを接合材のハンダ8を用いて実装するも
のである。さらに本実施形態ではリード部2の側面の凹
部、すなわちリード部2の側面内側と実装基板7の電
極、配線等の接続箇所とをハンダ8を用いて実装するも
のである。
In order to mount the semiconductor device configured as described above on a mounting board such as a printed circuit board, as shown in a cross-sectional view showing the mounting structure in FIG. One side surface and a connection portion of an electrode, a wiring, etc. of the mounting substrate 7 are mounted using solder 8 of a bonding material. Further, in the present embodiment, the concave portion on the side surface of the lead portion 2, that is, the inside of the side surface of the lead portion 2 and the connection portion of the mounting substrate 7 such as the electrodes and wiring are mounted using the solder 8.

【0028】本実施形態では、半導体装置の底面に配置
されたリード部2の露出した底面部と外方の一側面とを
ハンダ8により実装基板に接合して実装する構造に加え
て、リード部2の側面の凹部、すなわちリード部2の側
面内側と実装基板とを接合して実装する構造であるた
め、接合箇所が増加するため、飛躍的に実装強度を向上
させ、使用状況により印加される応力による影響を解消
し、二次実装の信頼性を向上させることができるもので
ある。
In the present embodiment, in addition to the structure in which the exposed bottom surface of the lead portion 2 disposed on the bottom surface of the semiconductor device and one outer side surface are joined to a mounting board by solder 8 and mounted, the lead portion is mounted. 2, that is, a structure in which the inside of the side surface of the lead portion 2 and the mounting substrate are joined and mounted, so that the number of joints increases, so that the mounting strength is dramatically improved and applied depending on the usage conditions. The effect of the stress can be eliminated and the reliability of the secondary mounting can be improved.

【0029】基板実装の方法としては、半導体装置を実
装基板に実装するに際し、半導体装置のリード部3の一
側面と底面とを接合材であるハンダ8で実装するととも
に、露出したリード部2の凹部をもハンダ8で実装する
ものであり、ハンダリフロー工程で一括で接合するもの
である。
When mounting the semiconductor device on a mounting board, one side and bottom surface of the lead portion 3 of the semiconductor device are mounted with solder 8 as a bonding material, and the exposed lead portion 2 is mounted. The recesses are also mounted with solder 8, and are joined together in a solder reflow process.

【0030】以上、本実施形態では、底面にリード部が
その底面と外方の一側面とを露出して配列されたQFN
型の半導体装置を例として説明したが、SON(Sma
llOutline Non−leaded Pack
age)型の半導体装置であっても同様の実装強度向上
の効果がある。またダイパッド部が底面に露出したタイ
プの半導体装置であっても同様の実装強度向上の効果が
ある。つまり、半導体装置の底面と側面とにリード部が
露出したタイプの半導体装置であれば、リード部の底面
および側面と基板との接合に加えて、リード部の側面に
設けられた凹部に対しても、ハンダ等の接合材を入り込
ませて接合させることができるので、実装強度を向上さ
せることができる。特に近年の小型化した携帯電話に半
導体装置を搭載した際にはその使用状況が過酷となり、
実装基板に撓み等による応力が印加され、接合部分に応
力が印加されても、その影響を解消し、二次実装の信頼
性を向上させることができるものである。
As described above, in this embodiment, the QFN in which the lead portions are arranged on the bottom surface so that the bottom surface and one outer side surface are exposed.
Although the semiconductor device of the SON (Sma) type has been described as an example,
llOutline Non-leaded Pack
An age-type semiconductor device has the same effect of improving the mounting strength. Also, a semiconductor device of the type in which the die pad portion is exposed on the bottom surface has the same effect of improving the mounting strength. That is, in the case of a semiconductor device in which the lead portion is exposed on the bottom surface and the side surface of the semiconductor device, in addition to the bonding between the substrate and the bottom surface and the side surface of the lead portion, the concave portion provided on the side surface of the lead portion is formed. Also, since the bonding material such as solder can be inserted and bonded, the mounting strength can be improved. In particular, when semiconductor devices are mounted on miniaturized mobile phones in recent years, their usage becomes severe,
Even if stress due to bending or the like is applied to the mounting substrate and stress is applied to the joint, the effect can be eliminated and the reliability of the secondary mounting can be improved.

【0031】[0031]

【発明の効果】本発明の半導体装置の実装構造および半
導体装置の実装方法は、半導体装置の底面に配置された
リード部の露出した底面部と外方の一側面とをハンダに
より実装基板に接合して実装する構造に加えて、リード
部の側面の凹部、すなわちリード部の側面内側と実装基
板の電極、配線等の接続箇所とをハンダを用いて実装基
板に接合して実装する構造であるため、接合箇所が増加
するため、飛躍的に実装強度を向上させ、使用状況によ
り印加される応力による影響を解消し、二次実装の信頼
性を向上させることができるものである。
According to the semiconductor device mounting structure and the semiconductor device mounting method of the present invention, the exposed bottom surface of the lead portion disposed on the bottom surface of the semiconductor device and one outer side surface are joined to the mounting substrate by soldering. In addition to the structure to be mounted and mounted, the concave portion on the side surface of the lead portion, that is, the inside of the side surface of the lead portion and the connection portions such as electrodes and wiring of the mounting substrate are joined to the mounting substrate using solder and mounted. Therefore, the number of joints increases, so that the mounting strength can be dramatically improved, the influence of the stress applied depending on the use condition can be eliminated, and the reliability of the secondary mounting can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の基板実装される半導体装
置を示す図
FIG. 1 is a diagram showing a semiconductor device mounted on a board according to an embodiment of the present invention;

【図2】本発明の一実施形態の基板実装される半導体装
置を示す図
FIG. 2 is a diagram showing a semiconductor device mounted on a board according to an embodiment of the present invention;

【図3】本発明の一実施形態の基板実装される半導体装
置を示す図
FIG. 3 is a diagram showing a semiconductor device mounted on a board according to an embodiment of the present invention;

【図4】本発明の一実施形態の半導体装置の実装方法を
示す図
FIG. 4 is a diagram showing a mounting method of the semiconductor device according to one embodiment of the present invention;

【図5】従来の基板実装される半導体装置を示す図FIG. 5 is a diagram showing a conventional semiconductor device mounted on a substrate.

【図6】従来の基板実装される半導体装置を示す図FIG. 6 is a diagram showing a conventional semiconductor device mounted on a substrate.

【図7】従来の半導体装置の実装方法を示す図FIG. 7 is a diagram showing a conventional semiconductor device mounting method.

【符号の説明】[Explanation of symbols]

1 封止樹脂 2 リード部 3 吊りリード部 4 半導体素子 5 ダイパッド部 6 金属細線 7 実装基板 8 ハンダ 9 凹部 DESCRIPTION OF SYMBOLS 1 Sealing resin 2 Lead part 3 Suspended lead part 4 Semiconductor element 5 Die pad part 6 Fine metal wire 7 Mounting substrate 8 Solder 9 Depression

───────────────────────────────────────────────────── フロントページの続き (72)発明者 老田 成志 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 舩越 正司 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 谷 昇 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 Fターム(参考) 5F067 AA13 AB03 AB04 BC07 BD05 BD10 DC17 DC19 EA04  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Narishi Ota 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Masashi Funakoshi 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics (72) Inventor Noboru Tani 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F067 AA13 AB03 AB04 BC07 BD05 BD10 DC17 DC19 EA04

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 底面に電気的接続用のリード部の底面が
配列され、側面に前記リード部の外方の一側面が配列さ
れた半導体装置であって、リード部の前記一側面が凹部
を有し、前記凹部を構成する凸部が前記リード部表面に
形成されたメッキ層による凸部であることを特徴とする
半導体装置。
1. A semiconductor device in which a bottom surface of a lead portion for electrical connection is arranged on a bottom surface and an outer side surface of the lead portion is arranged on a side surface, wherein the one side surface of the lead portion has a recess. The semiconductor device according to claim 1, wherein the convex portion forming the concave portion is a convex portion formed by a plating layer formed on the surface of the lead portion.
【請求項2】 半導体素子と、前記半導体素子を支持し
たダイパッド部と、前記ダイパッド部をその先端部で支
持した吊りリード部と、前記ダイパッド部に先端部が配
置されたリード部と、前記リード部と前記半導体素子と
を電気的に接続した接続手段と、少なくとも前記リード
部の一側面と底面とを露出させ、前記半導体素子、前記
ダイパッド部、前記接続手段の外囲を封止した封止樹脂
とよりなる半導体装置であって、前記リード部の側面が
凹部を有し、前記凹部を構成する凸部が前記リード部表
面に形成されたメッキ層による凸部であることを特徴と
する半導体装置。
2. A semiconductor device, a die pad portion supporting the semiconductor device, a suspension lead portion supporting the die pad portion at a distal end thereof, a lead portion having a distal end portion disposed on the die pad portion, and the lead. Connecting means for electrically connecting the semiconductor device and the semiconductor element, and at least one side surface and bottom surface of the lead portion being exposed, and sealing the semiconductor element, the die pad portion, and the outer periphery of the connecting means. A semiconductor device comprising a resin, wherein a side surface of the lead portion has a concave portion, and the convex portion forming the concave portion is a convex portion formed by a plating layer formed on a surface of the lead portion. apparatus.
【請求項3】 リード部の表面に形成されたメッキ層
は、パラジウム層を有した積層メッキ層であることを特
徴とする請求項1または請求項2に記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the plating layer formed on the surface of the lead portion is a laminated plating layer having a palladium layer.
【請求項4】 リード部の側面の凹部は、20[μm]
〜40[μm]であることを特徴とする請求項1または
請求項2に記載の半導体装置。
4. The concave portion on the side surface of the lead portion has a size of 20 [μm].
3. The semiconductor device according to claim 1, wherein the thickness of the semiconductor device is about 40 μm.
【請求項5】 半導体素子と、前記半導体素子を支持し
たダイパッド部と、前記ダイパッド部をその先端部で支
持した吊りリード部と、前記ダイパッド部に先端部が配
置されたリード部と、前記リード部と前記半導体素子と
を電気的に接続した接続手段と、少なくとも前記リード
部の外方の一側面と底面とを露出させ、前記半導体素
子、前記ダイパッド部、前記接続手段の外囲を封止した
封止樹脂とよりなり、リード部の外方の一側面が凹部を
有し、前記凹部を構成する凸部が前記リード部表面に形
成されたメッキ層による凸部である半導体装置の実装方
法であって、実装基板に対して前記半導体装置の少なく
とも前記リード部の一側面と底面とを接合材で実装する
とともに、前記リード部の前記凹部に接合材を入り込ま
せて、前記リード部の底面、側面および側面の内側で接
合することを特徴とする半導体装置の実装方法。
5. A semiconductor device, a die pad portion supporting the semiconductor device, a suspension lead portion supporting the die pad portion at a tip end thereof, a lead portion having a tip end portion arranged on the die pad portion, and the lead Connecting means for electrically connecting the semiconductor element to the semiconductor element, and exposing at least one outer side surface and bottom surface of the lead part, and sealing the outer periphery of the semiconductor element, the die pad part, and the connecting means. A method for mounting a semiconductor device, comprising: a sealing resin formed on the outer surface of a lead portion having a concave portion, and the convex portion forming the concave portion being a convex portion formed by a plating layer formed on the surface of the lead portion. And mounting at least one side surface and a bottom surface of the lead portion of the semiconductor device to a mounting board with a bonding material, and letting a bonding material enter the recess of the lead portion, A method of mounting a semiconductor device, comprising: bonding at a bottom surface, a side surface, and inside a side surface.
JP2000066526A 2000-03-10 2000-03-10 Semiconductor device and method of mounting the same Pending JP2001257304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2001257304A true JP2001257304A (en) 2001-09-21

Family

ID=18585878

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Publication number Priority date Publication date Assignee Title
JP2005079372A (en) * 2003-09-01 2005-03-24 Nec Electronics Corp Resin-sealed semiconductor device and its manufacturing method
US8115299B2 (en) 2007-02-27 2012-02-14 Rohm Co., Ltd. Semiconductor device, lead frame and method of manufacturing semiconductor device
CN104470248A (en) * 2014-12-12 2015-03-25 上海斐讯数据通信技术有限公司 Steel mesh optimizing method
JP2019121698A (en) * 2018-01-09 2019-07-22 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device
US10930574B2 (en) 2018-05-01 2021-02-23 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US11404375B2 (en) 2019-09-26 2022-08-02 Rohm Co., Ltd. Terminal configuration and semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079372A (en) * 2003-09-01 2005-03-24 Nec Electronics Corp Resin-sealed semiconductor device and its manufacturing method
US7166919B2 (en) 2003-09-01 2007-01-23 Nec Electronics Corporation Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
US7655506B2 (en) 2003-09-01 2010-02-02 Nec Electronics Corporation Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
US8115299B2 (en) 2007-02-27 2012-02-14 Rohm Co., Ltd. Semiconductor device, lead frame and method of manufacturing semiconductor device
CN104470248A (en) * 2014-12-12 2015-03-25 上海斐讯数据通信技术有限公司 Steel mesh optimizing method
JP2019121698A (en) * 2018-01-09 2019-07-22 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device
JP7037368B2 (en) 2018-01-09 2022-03-16 ローム株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
US10930574B2 (en) 2018-05-01 2021-02-23 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US11404375B2 (en) 2019-09-26 2022-08-02 Rohm Co., Ltd. Terminal configuration and semiconductor device
US11705399B2 (en) 2019-09-26 2023-07-18 Rohm Co., Ltd. Terminal configuration and semiconductor device

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