JPH11509043A - 少なくとも２つの互いに絶縁されたデバイスを有する集積回路装置およびその製造方法 - Google Patents

少なくとも２つの互いに絶縁されたデバイスを有する集積回路装置およびその製造方法

Info

Publication number
JPH11509043A
JPH11509043A JP9505399A JP50539997A JPH11509043A JP H11509043 A JPH11509043 A JP H11509043A JP 9505399 A JP9505399 A JP 9505399A JP 50539997 A JP50539997 A JP 50539997A JP H11509043 A JPH11509043 A JP H11509043A
Authority
JP
Japan
Prior art keywords
trench
main surface
etching
insulating structure
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP9505399A
Other languages
English (en)
Japanese (ja)
Inventor
ラウ、フランク
クラウチユナイダー、ウオルフガング
エンゲルハルト、マンフレート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH11509043A publication Critical patent/JPH11509043A/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP9505399A 1995-07-10 1996-06-24 少なくとも２つの互いに絶縁されたデバイスを有する集積回路装置およびその製造方法 Ceased JPH11509043A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19525072.9 1995-07-10
DE19525072A DE19525072C2 (de) 1995-07-10 1995-07-10 Integrierte Schaltungsanordnung, bei der ein erstes Bauelement an einer Hauptfläche eines Halbleitersubstrats und ein zweites Bauelement am Grabenboden angeordnet sind, und Verfahren zu deren Herstellung
PCT/DE1996/001109 WO1997003463A1 (de) 1995-07-10 1996-06-24 Integrierte schaltungsanordnung mit mindestens zwei gegeneinander isolierten bauelementen und verfahren zu deren herstellung

Publications (1)

Publication Number Publication Date
JPH11509043A true JPH11509043A (ja) 1999-08-03

Family

ID=7766444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9505399A Ceased JPH11509043A (ja) 1995-07-10 1996-06-24 少なくとも２つの互いに絶縁されたデバイスを有する集積回路装置およびその製造方法

Country Status (9)

Country Link
US (1) US5990536A (enExample)
EP (1) EP0838089B1 (enExample)
JP (1) JPH11509043A (enExample)
KR (1) KR100418849B1 (enExample)
CN (1) CN1093983C (enExample)
AR (1) AR002791A1 (enExample)
DE (2) DE19525072C2 (enExample)
IN (1) IN189112B (enExample)
WO (1) WO1997003463A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218720B1 (en) * 1998-10-21 2001-04-17 Advanced Micro Devices, Inc. Semiconductor topography employing a nitrogenated shallow trench isolation structure
US7071043B2 (en) * 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134445A (ja) * 1982-02-05 1983-08-10 Seiko Epson Corp 半導体装置の製造方法
JPS58169934A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 半導体集積回路装置
JPS61135151A (ja) * 1984-12-05 1986-06-23 Mitsubishi Electric Corp 半導体記憶装置
US5176789A (en) * 1985-09-21 1993-01-05 Semiconductor Energy Laboratory Co., Ltd. Method for depositing material on depressions
JPS6378573A (ja) * 1986-09-22 1988-04-08 Hitachi Ltd 半導体装置
US4835584A (en) * 1986-11-27 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Trench transistor
DE3809218C2 (de) * 1987-03-20 1994-09-01 Mitsubishi Electric Corp Halbleitereinrichtung mit einem Graben und Verfahren zum Herstellen einer solchen Halbleitereinrichtung
JPH0620108B2 (ja) * 1987-03-23 1994-03-16 三菱電機株式会社 半導体装置の製造方法
US4977436A (en) * 1988-07-25 1990-12-11 Motorola, Inc. High density DRAM
JPH04151850A (ja) * 1990-10-15 1992-05-25 Nec Corp 溝絶縁分離型半導体集積回路の製造方法
FR2672731A1 (fr) * 1991-02-07 1992-08-14 France Telecom Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant.
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
EP0540262A2 (en) * 1991-10-31 1993-05-05 STMicroelectronics, Inc. Trench isolation region
JPH0637275A (ja) * 1992-07-13 1994-02-10 Toshiba Corp 半導体記憶装置及びその製造方法
US5512517A (en) * 1995-04-25 1996-04-30 International Business Machines Corporation Self-aligned gate sidewall spacer in a corrugated FET and method of making same

Also Published As

Publication number Publication date
DE59607729D1 (de) 2001-10-25
KR100418849B1 (ko) 2004-04-21
WO1997003463A1 (de) 1997-01-30
IN189112B (enExample) 2002-12-21
EP0838089A1 (de) 1998-04-29
KR19990014889A (ko) 1999-02-25
EP0838089B1 (de) 2001-09-19
US5990536A (en) 1999-11-23
AR002791A1 (es) 1998-04-29
DE19525072C2 (de) 2002-06-27
CN1190490A (zh) 1998-08-12
DE19525072A1 (de) 1997-01-16
CN1093983C (zh) 2002-11-06

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