JPH11354640A - 集積回路を製造するプロセスおよび集積回路 - Google Patents

集積回路を製造するプロセスおよび集積回路

Info

Publication number
JPH11354640A
JPH11354640A JP11135255A JP13525599A JPH11354640A JP H11354640 A JPH11354640 A JP H11354640A JP 11135255 A JP11135255 A JP 11135255A JP 13525599 A JP13525599 A JP 13525599A JP H11354640 A JPH11354640 A JP H11354640A
Authority
JP
Japan
Prior art keywords
dielectric layer
layer
integrated circuit
layers
adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11135255A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11354640A5 (enExample
Inventor
Philippe Gayet
フィリップ・ガイェット
Eric Granger
エリック・グランガー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of JPH11354640A publication Critical patent/JPH11354640A/ja
Publication of JPH11354640A5 publication Critical patent/JPH11354640A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP11135255A 1998-05-27 1999-05-17 集積回路を製造するプロセスおよび集積回路 Withdrawn JPH11354640A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9806687 1998-05-27
FR9806687A FR2779274B1 (fr) 1998-05-27 1998-05-27 Circuit integre avec couche d'arret et procede de fabrication associe

Publications (2)

Publication Number Publication Date
JPH11354640A true JPH11354640A (ja) 1999-12-24
JPH11354640A5 JPH11354640A5 (enExample) 2006-06-22

Family

ID=9526773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11135255A Withdrawn JPH11354640A (ja) 1998-05-27 1999-05-17 集積回路を製造するプロセスおよび集積回路

Country Status (4)

Country Link
US (2) US6355552B1 (enExample)
EP (1) EP0961318A1 (enExample)
JP (1) JPH11354640A (enExample)
FR (1) FR2779274B1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977224B2 (en) * 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
US7008872B2 (en) * 2002-05-03 2006-03-07 Intel Corporation Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
KR20040061817A (ko) * 2002-12-31 2004-07-07 주식회사 하이닉스반도체 반도체소자의 금속배선 형성방법
US7087104B2 (en) 2003-06-26 2006-08-08 Intel Corporation Preparation of electroless deposition solutions
US7767578B2 (en) * 2007-01-11 2010-08-03 United Microelectronics Corp. Damascene interconnection structure and dual damascene process thereof
JP5837754B2 (ja) * 2011-03-23 2015-12-24 Ｄｏｗａメタルテック株式会社 金属−セラミックス接合基板およびその製造方法
JP5923334B2 (ja) * 2012-02-22 2016-05-24 ルネサスエレクトロニクス株式会社 半導体装置
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US10862610B1 (en) 2019-11-11 2020-12-08 X Development Llc Multi-channel integrated photonic wavelength demultiplexer
US11187854B2 (en) * 2019-11-15 2021-11-30 X Development Llc Two-channel integrated photonic wavelength demultiplexer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5110712A (en) * 1987-06-12 1992-05-05 Hewlett-Packard Company Incorporation of dielectric layers in a semiconductor
US5321211A (en) * 1992-04-30 1994-06-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit via structure
JP2934353B2 (ja) * 1992-06-24 1999-08-16 三菱電機株式会社 半導体装置およびその製造方法
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5244837A (en) * 1993-03-19 1993-09-14 Micron Semiconductor, Inc. Semiconductor electrical interconnection methods
US5817574A (en) * 1993-12-29 1998-10-06 Intel Corporation Method of forming a high surface area interconnection structure
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
JPH08241924A (ja) * 1995-03-06 1996-09-17 Sony Corp 接続孔を有する半導体装置及びその製造方法
US5834845A (en) * 1995-09-21 1998-11-10 Advanced Micro Devices, Inc. Interconnect scheme for integrated circuits
JPH10242271A (ja) * 1997-02-28 1998-09-11 Sony Corp 半導体装置及びその製造方法
US5935868A (en) * 1997-03-31 1999-08-10 Intel Corporation Interconnect structure and method to achieve unlanded vias for low dielectric constant materials
US5891799A (en) * 1997-08-18 1999-04-06 Industrial Technology Research Institute Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
US6020255A (en) * 1998-07-13 2000-02-01 Taiwan Semiconductor Manufacturing Company Dual damascene interconnect process with borderless contact
US6048787A (en) * 1998-09-08 2000-04-11 Winbond Electronics Corp. Borderless contacts for dual-damascene interconnect process

Also Published As

Publication number Publication date
FR2779274B1 (fr) 2000-08-18
FR2779274A1 (fr) 1999-12-03
US6762497B2 (en) 2004-07-13
US6355552B1 (en) 2002-03-12
US20020079589A1 (en) 2002-06-27
EP0961318A1 (fr) 1999-12-01

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