JPH1131704A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH1131704A
JPH1131704A JP18502397A JP18502397A JPH1131704A JP H1131704 A JPH1131704 A JP H1131704A JP 18502397 A JP18502397 A JP 18502397A JP 18502397 A JP18502397 A JP 18502397A JP H1131704 A JPH1131704 A JP H1131704A
Authority
JP
Japan
Prior art keywords
sealing resin
base substrate
groove
semiconductor device
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18502397A
Other languages
Japanese (ja)
Inventor
Tsutomu Goto
務 後藤
Yoshiharu Harada
嘉治 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP18502397A priority Critical patent/JPH1131704A/en
Publication of JPH1131704A publication Critical patent/JPH1131704A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To simply and inexpensively manufacture a semiconductor device whose surface made of sealing resin is flat. SOLUTION: Sealing resin 4 is applied to the entire face of the part of a base substrate 1 on which a bare chip 2 is mounted, the thickness is made almost uniform through the surface tension, and then the sealing resin 4 is heated and hardened. Then, the base substrate 1 is divided into each unit block 1b along a V groove 1a formed at the base substrate 1, so that a semiconductor device can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路の
ベアチップが搭載されたパッケージ用ベース基板を樹脂
により封止してなる半導体装置の製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device in which a package base substrate on which a bare chip of a semiconductor integrated circuit is mounted is sealed with a resin.

【0002】[0002]

【発明が解決しようとする課題】半導体装置の製造方法
の従来技術としては、ベアチップが単位区画毎に搭載さ
れた多数個取りされるパッケージ用ベース基板に対し
て、ディスペンサを用いて当該単位区画毎に樹脂を塗布
するポッティング法がある。このポッティング法では、
ベース基板の単位区画面積が比較的小さいため、塗布し
た樹脂の表面が平坦になる部分が殆どなく略凸状になっ
てしまう。このことから、樹脂が塗布されたベース基板
を分割して完成した半導体装置を回路基板に表面実装す
る際に、実装装置の真空吸着ノズルによる吸着性が良く
ないという問題があった。
As a prior art of a method of manufacturing a semiconductor device, there is known a method of manufacturing a semiconductor device. There is a potting method in which a resin is applied to the surface. In this potting method,
Since the unit partition area of the base substrate is relatively small, the surface of the applied resin hardly has a flat portion, and the resin has a substantially convex shape. For this reason, when the semiconductor device completed by dividing the base substrate coated with the resin is surface-mounted on the circuit board, there has been a problem that the suction performance of the vacuum suction nozzle of the mounting device is not good.

【0003】斯様な問題を解決するため、ベアチップが
搭載されたベース基板を型の中に入れた状態で樹脂を圧
入することにより、単位区画毎に樹脂を平坦にコーティ
ングするモールド成型法が用いられるようになった。し
かし、このモールド成型法では型の作成に非常にコスト
が掛り、加えて、工程も複雑になるという問題があっ
た。
In order to solve such a problem, a molding method is used in which a resin is press-fitted in a state in which a base substrate on which a bare chip is mounted is put in a mold, so that the resin is coated flat in each unit section. Is now available. However, in this molding method, there is a problem that the production of the mold is very costly, and in addition, the process becomes complicated.

【0004】また、特開昭58−135号公報には、半
導体チップ上に形成されるメモリセルなどの領域を、自
然界に存在するα線から保護するために樹脂モールド下
においてシリコーン膜により保護する場合にそのシリコ
ーン膜の表面を平坦にすることを目的として、塗布した
シリコーン膜が硬化する以前に、別部材の絶縁性樹脂薄
膜をシリコーン膜の表面に載せることにより当該目的を
達成したものが開示されている。
Japanese Patent Application Laid-Open No. 58-135 discloses that a region such as a memory cell formed on a semiconductor chip is protected by a silicone film under a resin mold in order to protect α-rays existing in nature. In order to make the surface of the silicone film flat in such a case, before the applied silicone film is cured, a material which achieves the purpose by disposing an insulating resin thin film of another member on the surface of the silicone film is disclosed. Have been.

【0005】この特開昭58−135号公報に開示され
た技術は、そのまま封止樹脂の形成について適用できる
と思われるが、やはり、別部材を使用することによって
コストアップや工程の増加という問題は解決されずに課
題として存在する。
Although the technique disclosed in Japanese Patent Application Laid-Open No. 58-135 seems to be applicable to the formation of a sealing resin as it is, the use of a separate member also increases the cost and the number of steps. Exists as an issue without being solved.

【0006】本発明は上記事情に鑑みてなされたもので
あり、その目的は、簡単且つ低価格で封止樹脂の表面を
平坦に製造可能な半導体装置の製造方法を提供すること
にある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device which can easily and inexpensively manufacture a flat surface of a sealing resin.

【0007】[0007]

【課題を解決するための手段】請求項1記載の半導体装
置の製造方法によれば、半導体集積回路のベアチップが
搭載されたパッケージ用のベース基板の搭載面全体に亘
って封止樹脂を塗布すると、表面張力の作用によって、
その封止樹脂の塗布厚さ寸法は略均一となるので、封止
樹脂を硬化させた後、ベース基板に形成されている分割
溝部に沿って分割された各半導体装置の封止樹脂表面は
平坦に形成される。従って、モールド成型法や特開昭5
8−135号公報に開示された技術のように高価な型や
別部材を用いずとも、例えば、真空吸着を行うノズルを
有する実装装置によって回路基板にマウントとする場合
には、そのノズルによる吸着性が良好となる半導体装置
を簡単且つ低価格に製造することができる。
According to a method of manufacturing a semiconductor device according to the present invention, a sealing resin is applied over the entire mounting surface of a package base substrate on which a bare chip of a semiconductor integrated circuit is mounted. , By the action of surface tension,
Since the thickness of the applied sealing resin becomes substantially uniform, the surface of the sealing resin of each semiconductor device divided along the dividing groove formed in the base substrate after the sealing resin is cured is flat. Formed. Therefore, the molding method and
For example, when mounting on a circuit board by a mounting apparatus having a nozzle for performing vacuum suction without using an expensive mold or another member as in the technique disclosed in Japanese Patent Application Laid-Open No. 8-135, suction by the nozzle is used. A semiconductor device having good performance can be manufactured easily and at low cost.

【0008】請求項2記載の半導体装置の製造方法によ
れば、半導体集積回路のベアチップが搭載されたパッケ
ージ用のベース基板に熱硬化性の封止樹脂がベアチップ
の搭載面全体に亘って塗布された後半硬化された状態
で、ベース基板に形成されている分割溝部に対応する位
置の封止樹脂表面に治具が押当てられて補助分割溝部が
形成される。従って、封止樹脂表面に補助分割溝部を形
成することによって、ベース基板を単位区画毎に分割す
る工程をより容易に行うことができる。
According to the method of manufacturing a semiconductor device of the present invention, a thermosetting sealing resin is applied to the entire package mounting substrate on which the bare chip of the semiconductor integrated circuit is mounted. In the hardened state in the latter half, the jig is pressed against the surface of the sealing resin at a position corresponding to the divisional groove formed on the base substrate to form an auxiliary divisional groove. Therefore, by forming the auxiliary division grooves on the surface of the sealing resin, the step of dividing the base substrate into unit sections can be performed more easily.

【0009】請求項3記載の半導体装置の製造方法によ
れば、補助分割溝部形成用の治具が加熱されているの
で、封止樹脂の硬化が促進されて、硬化に要する時間を
短縮することができる。
According to the method of manufacturing a semiconductor device of the present invention, since the jig for forming the auxiliary dividing groove is heated, the curing of the sealing resin is accelerated, and the time required for the curing is shortened. Can be.

【0010】請求項4記載の半導体装置の製造方法によ
れば、封止樹脂表面に形成される補助分割溝部の深さ
が、塗布した封止樹脂の厚さ寸法と略等しくなるので、
ベース基板を単位区画毎に分割する工程を一層容易に行
うことができる。
According to the method of manufacturing a semiconductor device of the present invention, the depth of the auxiliary dividing groove formed on the surface of the sealing resin is substantially equal to the thickness of the applied sealing resin.
The step of dividing the base substrate into unit sections can be performed more easily.

【0011】請求項5記載の半導体装置の製造方法によ
れば、封止樹脂表面に形成される補助分割溝部の形状
が、単位区画毎の封止樹脂の分割端部が湾曲形状となる
ように形成されるので、封止樹脂の体積は分割端部に近
付くほど、分割端部が直線的な形状のものに比べて小さ
くなる。
According to the method of manufacturing a semiconductor device of the present invention, the shape of the auxiliary dividing groove formed on the sealing resin surface is such that the dividing end of the sealing resin for each unit section has a curved shape. Since the sealing resin is formed, the volume of the sealing resin becomes smaller as approaching the divided end, as compared with the case where the divided end has a linear shape.

【0012】従って、温度変化時における分割端部近傍
の封止樹脂の熱膨張、或いは熱収縮に伴う応力を低減し
得て、分割端部における封止樹脂とベース基板との接合
面近傍において作用する熱応力を抑制することができる
ので、前記接合面で封止樹脂とベース基板との剥離が生
じるのを防止することができ、半導体装置の歩留まりを
向上させることができる。
Therefore, it is possible to reduce the thermal expansion or thermal shrinkage of the sealing resin near the divided end when the temperature changes, and to reduce the stress near the joint surface between the sealing resin and the base substrate at the divided end. Therefore, it is possible to prevent the sealing resin from peeling off from the base substrate at the bonding surface, and to improve the yield of the semiconductor device.

【0013】[0013]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(第1実施例)以下、本発明の第1実施例について、図
1乃至図3を参照して説明する。図3は、ベース基板に
半導体集積回路のベアチップ及びその他の部品が搭載さ
れた状態を示す平面図である。ベース基板1は、厚さ
0.5mmのガラスエポキシまたはアルミナなどからな
り、基板寸法は縦40mm×横55mm程度である。こ
のベース基板1は、一例として6個取りであり、カッタ
ーなどで形成された分割用のV溝(分割溝部)1aによ
って、6個の単位区画1bに区切られている。その各単
位区画1bの寸法は、各15mm平方となっている。
(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a plan view showing a state in which a bare chip and other components of a semiconductor integrated circuit are mounted on a base substrate. The base substrate 1 is made of, for example, glass epoxy or alumina having a thickness of 0.5 mm, and the substrate dimensions are about 40 mm long × 55 mm wide. The base substrate 1 has six pieces as an example, and is divided into six unit sections 1b by a dividing V-groove (divided groove portion) 1a formed by a cutter or the like. The size of each unit section 1b is 15 mm square.

【0014】そして、6個の単位区画1bは2列×3列
に配置されており、ベース基板1の周辺は、後述するよ
うに各単位区画1bに分割する際に押さえとして使用さ
れる5mm幅の耳部1cが形成されている。各単位区画
1b上には、ベアチップ2,及び抵抗やコンデンサなど
のチップ部品3が搭載されている。ベアチップ2は、そ
の表面に半導体集積回路が形成されており、ベース基板
1上に形成されている配線パターンにボンディングワイ
ヤ2aによって接続されている。
The six unit sections 1b are arranged in 2 × 3 rows, and the periphery of the base substrate 1 has a width of 5 mm which is used as a holder when dividing into each unit section 1b as described later. Are formed. On each unit section 1b, a bare chip 2, and chip components 3 such as resistors and capacitors are mounted. The bare chip 2 has a semiconductor integrated circuit formed on its surface, and is connected to a wiring pattern formed on the base substrate 1 by bonding wires 2a.

【0015】図1は、図3に示すベース基板1の部品面
(ベアチップ2等の搭載面)に、封止樹脂4をディスペ
ンス法により塗布した状態を示す断面図である。封止樹
脂4は、熱硬化性のエポキシ樹脂からなり、ベース基板
1の部品面の全体に亘って厚さ寸法が1.0mm程度と
なるように塗布されている。
FIG. 1 is a cross-sectional view showing a state where a sealing resin 4 is applied by a dispense method to a component surface (a mounting surface of the bare chip 2 and the like) of the base substrate 1 shown in FIG. The sealing resin 4 is made of a thermosetting epoxy resin, and is applied so as to have a thickness of about 1.0 mm over the entire component surface of the base substrate 1.

【0016】即ち、封止樹脂4をベース基板1の部品面
の全体に亘って塗布すると、その塗布厚さ寸法は、封止
樹脂4の表面張力の作用によって略均一となる。また、
ベース基板1の表裏に形成されているV溝1aの深さ寸
法は、ベース基板1の厚さ寸法の1/3程度である。
That is, when the sealing resin 4 is applied over the entire component surface of the base substrate 1, the thickness of the applied resin becomes substantially uniform due to the effect of the surface tension of the sealing resin 4. Also,
The depth dimension of the V-groove 1 a formed on the front and back of the base substrate 1 is about 1 / of the thickness dimension of the base substrate 1.

【0017】封止樹脂4が塗布されたベース基板1は、
加熱炉などに搬入されて、封止樹脂4を硬化させるため
に加熱が行われる。その加熱条件としては、例えば、1
50度で4時間程度である。封止樹脂4が硬化される
と、ベース基板1は、V溝1aに沿って各単位区画1b
毎に分割されて、図2に示すように個別の半導体装置5
が形成される。尚、分割の方式は、要はV溝1aを分割
の中心として応力をかければ良く、人手を用いたり、或
いは、治具や専用の装置を用いても良い。
The base substrate 1 to which the sealing resin 4 has been applied is
It is carried into a heating furnace or the like and heated to cure the sealing resin 4. As the heating conditions, for example, 1
It is about 4 hours at 50 degrees. When the sealing resin 4 is cured, the base substrate 1 is moved along the V-groove 1a into each unit section 1b.
Each semiconductor device 5 is divided as shown in FIG.
Is formed. In addition, the method of division may be such that a stress is applied with the V-groove 1a as the center of division, and may be manually applied, or a jig or a dedicated device may be used.

【0018】以上のように本実施例によれば、ベアチッ
プ2が搭載されたベース基板1の部品面の全体に亘って
封止樹脂4を塗布することにより、表面張力の作用でそ
の塗布厚さ寸法が略均一となるようにし、封止樹脂4を
硬化させた後、ベース基板1に形成されているV溝1a
に沿ってベース基板1を各単位区画1bに分割するよう
にした。
As described above, according to the present embodiment, the sealing resin 4 is applied over the entire component surface of the base substrate 1 on which the bare chip 2 is mounted, so that the thickness of the applied resin is increased by the action of surface tension. After the dimensions are made substantially uniform and the sealing resin 4 is cured, the V-groove 1a formed in the base substrate 1 is formed.
The base substrate 1 is divided into the unit sections 1b along the line.

【0019】従って、分割された各半導体装置5の封止
樹脂4の表面は平坦に形成されるので、半導体装置5
を、真空吸着を行うノズルを有する実装装置によって回
路基板にマウントとする場合には、そのノズルにおける
吸着性が良好となり、モールド成型法や特開昭58−1
35号公報に開示された技術のように高価な型や別部材
を用いずとも、斯様に吸着性が良好な半導体装置5を簡
単且つ低価格に製造することができる。
Therefore, the surface of the sealing resin 4 of each divided semiconductor device 5 is formed flat, so that the semiconductor device 5
Is mounted on a circuit board by a mounting device having a nozzle for performing vacuum suction, the suction property of the nozzle is improved, and the molding method and
The semiconductor device 5 having such good adsorbability can be easily and inexpensively manufactured without using an expensive mold or another member as in the technique disclosed in Japanese Patent Publication No. 35-35.

【0020】(第2実施例)図4乃至図6は本発明の第
2実施例を示すものであり、第1実施例と同一部分には
同一符号を付して説明を省略し、以下異なる部分につい
てのみ説明する。第2実施例においては、図1に示すよ
うにベース基板1に封止樹脂4を塗布した状態で、その
封止樹脂4が半硬化状態となるように加熱を行う。ここ
で言う“半硬化状態”とは、封止樹脂4が完全に硬化す
る以前の状態をいう。
(Second Embodiment) FIGS. 4 to 6 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Only the parts will be described. In the second embodiment, while the sealing resin 4 is applied to the base substrate 1 as shown in FIG. 1, heating is performed so that the sealing resin 4 is in a semi-cured state. Here, the “semi-cured state” refers to a state before the sealing resin 4 is completely cured.

【0021】例えば、第1実施例では、封止樹脂4を1
50度で4時間程度加熱することによって完全に硬化さ
せたが、第2実施例では、封止樹脂4を100度で5分
加熱することによって半硬化状態にする。
For example, in the first embodiment, the sealing resin 4 is
Although it was completely cured by heating at 50 degrees for about 4 hours, in the second embodiment, the sealing resin 4 is heated to 100 degrees for 5 minutes to be in a semi-cured state.

【0022】次に、半硬化状態にある封止樹脂4の表面
に対して、図4に示すように、治具6を上方から押当て
ることによって、封止樹脂4の表面にも補助V溝(補助
分割溝部)4aを形成する。図5は、治具6の上下を反
転してその刃先の形状を部分的に示す斜視図である。こ
の図5において、治具6は、断面が三角形状の刃先が、
ベース基板1上に形成されているV溝1aの位置に合わ
せて15mmピッチとなるように格子状に組合わされた
構成となっている。
Next, as shown in FIG. 4, the jig 6 is pressed from above onto the surface of the sealing resin 4 in a semi-cured state, so that the auxiliary V-groove is also formed on the surface of the sealing resin 4. (Auxiliary division groove) 4a is formed. FIG. 5 is a perspective view in which the jig 6 is turned upside down to partially show the shape of the cutting edge. In FIG. 5, the jig 6 has a triangular cutting edge.
The configuration is such that they are combined in a grid pattern so as to have a pitch of 15 mm in accordance with the position of the V groove 1a formed on the base substrate 1.

【0023】斯様な治具6を封止樹脂4の表面に押当て
ることにより、基板1上のV溝1aの位置に応じた補助
V溝4aを封止樹脂4の表面に一括で形成する。補助V
溝4aの深さ寸法は、例えば0.3mm程度とする。そ
の後は、第1実施例と同様に、封止樹脂4を150度で
4時間程度(或いは、半硬化させた分だけ割り引いた加
熱条件で)加熱することにより完全に硬化させてから、
V溝1a及び補助V溝4aに沿って各単位区画1bに分
割して半導体装置5を製造する。
By pressing such a jig 6 against the surface of the sealing resin 4, auxiliary V-grooves 4 a corresponding to the positions of the V-grooves 1 a on the substrate 1 are collectively formed on the surface of the sealing resin 4. . Auxiliary V
The depth dimension of the groove 4a is, for example, about 0.3 mm. After that, similarly to the first embodiment, the sealing resin 4 is completely cured by heating at 150 ° C. for about 4 hours (or under a heating condition obtained by discounting a half-cured amount).
The semiconductor device 5 is manufactured by being divided into the unit sections 1b along the V-groove 1a and the auxiliary V-groove 4a.

【0024】以上のように第2実施例によれば、ベース
基板1の部品面全体に亘って封止樹脂4を塗布してその
封止樹脂4を半硬化させた状態で、ベース基板1に形成
されているV溝1aに対応する位置の封止樹脂4表面に
治具6を押当てることにより、封止樹脂4表面に補助V
溝4aを一括で形成した。従って、V溝1a及び補助V
溝4aに沿って、ベース基板1をより容易に各単位区画
1bに分割することができる。
As described above, according to the second embodiment, the sealing resin 4 is applied over the entire component surface of the base substrate 1 and the sealing resin 4 is semi-cured. By pressing the jig 6 against the surface of the sealing resin 4 at a position corresponding to the formed V-groove 1a, the auxiliary V
The groove 4a was formed at once. Therefore, the V groove 1a and the auxiliary V
The base substrate 1 can be more easily divided into the unit sections 1b along the grooves 4a.

【0025】また、第2実施例においては、図6に示す
ように、補助V溝(補助分割溝部)4a′の深さ寸法
を、封止樹脂4の厚さ寸法と略等しくなるように設定し
ても良い。斯様に補助V溝4a′を形成すれば、ベース
基板1を一層容易に各単位区画1bに分割することがで
きる。
In the second embodiment, as shown in FIG. 6, the depth of the auxiliary V-groove (auxiliary divided groove) 4a 'is set to be substantially equal to the thickness of the sealing resin 4. You may. By forming the auxiliary V-groove 4a 'in this manner, the base substrate 1 can be more easily divided into the unit sections 1b.

【0026】(第3実施例)図7乃至図9は本発明の第
3実施例を示すものであり、第2実施例と同一部分には
同一符号を付して説明を省略し、以下異なる部分につい
てのみ説明する。第3実施例においては、治具7を用い
て第2実施例と同様に、封止樹脂4表面に補助溝(補助
分割溝部)4bを一括で形成するが、その補助溝4bの
形状が補助V溝4aとは異なっている。即ち、図8に示
すように、治具7の刃先の形状は三角形状ではなく、図
8においては下方に行く程拡がるように湾曲した(所謂
Rの付いた)形状となっている。
(Third Embodiment) FIGS. 7 to 9 show a third embodiment of the present invention. The same parts as those of the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. Only the parts will be described. In the third embodiment, an auxiliary groove (auxiliary divided groove portion) 4b is collectively formed on the surface of the sealing resin 4 by using the jig 7 as in the second embodiment, but the shape of the auxiliary groove 4b is auxiliary. It is different from the V groove 4a. That is, as shown in FIG. 8, the shape of the cutting edge of the jig 7 is not triangular, but in FIG. 8, it has a curved shape (with a so-called R) that expands downward.

【0027】斯様な刃先の形状を有する治具7によっ
て、封止樹脂4表面に形成された補助溝4bの形状によ
り、図7に示すように、各単位区画1bの封止樹脂4の
分割端部4cの形状も湾曲したものとなっている。分割
端部4cを斯様な形状とすることによって、以下のよう
な作用効果を生じる。
The jig 7 having such a cutting edge shape divides the sealing resin 4 of each unit section 1b according to the shape of the auxiliary groove 4b formed on the surface of the sealing resin 4 as shown in FIG. The shape of the end 4c is also curved. By forming the divided end portion 4c in such a shape, the following operation and effect can be obtained.

【0028】即ち、図7においては、分割端部4cが湾
曲形状となることにより、第2実施例のように分割端部
の形状が直線的なものに比して、封止樹脂4の体積は分
割端部4cに近付くほど小さくなる。従って、温度変化
時における分割端部4c近傍の封止樹脂4の熱膨張、或
いは熱収縮に伴う応力が低減されて、分割端部4cにお
ける封止樹脂4とベース基板1との接合面8近傍におい
て作用する熱応力が抑制されるので、前記接合面8で封
止樹脂4とベース基板1との剥離が生じるのを防止する
ことができる。
That is, in FIG. 7, since the divided end 4c has a curved shape, the volume of the sealing resin 4 is smaller than that of the second embodiment in which the shape of the divided end is linear. Becomes smaller as approaching the divided end 4c. Therefore, the stress accompanying the thermal expansion or thermal contraction of the sealing resin 4 near the divided end 4c at the time of temperature change is reduced, and the vicinity of the joint surface 8 between the sealing resin 4 and the base substrate 1 at the divided end 4c is reduced. Since the thermal stress acting on the base member 1 is suppressed, it is possible to prevent the sealing resin 4 and the base substrate 1 from being separated from each other on the bonding surface 8.

【0029】また、分割端部4cの湾曲の度合いは、半
導体装置5のパッケージサイズが大きくなるのに伴なっ
て、図9に示すように、封止樹脂4とベース基板1との
接合面8の一端部8aにおいて、分割端部4cの湾曲形
状が示す傾き角θを小さくするように設定する。斯様に
設定すれば、パッケージサイズが大きくなるのに伴なっ
て大となる熱応力の作用を低減することができる。
Further, as the package size of the semiconductor device 5 increases, the degree of curvature of the divided end portion 4c increases as shown in FIG. At one end 8a, the inclination angle θ indicated by the curved shape of the divided end 4c is set to be small. With this setting, it is possible to reduce the effect of thermal stress that increases as the package size increases.

【0030】以上のように第3実施例によれば、治具7
を用いて封止樹脂4表面に湾曲形状を有する補助溝4b
を形成することにより、各単位区画1bの封止樹脂4の
分割端部4cの形状を湾曲させたので、温度変化時にお
いて封止樹脂4とベース基板1との接合面8近傍におい
て作用する熱応力が小さくなり、接合面8で封止樹脂4
とベース基板1との剥離が生じるのを防止し得て、半導
体装置5の歩留まりを向上させることができる。
As described above, according to the third embodiment, the jig 7
Auxiliary groove 4b having a curved shape on the surface of sealing resin 4 by using
Is formed, the shape of the divided end 4c of the sealing resin 4 in each unit section 1b is curved, so that the heat acting near the joint surface 8 between the sealing resin 4 and the base substrate 1 when the temperature changes. The stress is reduced, and the sealing resin 4
Separation from the base substrate 1 can be prevented, and the yield of the semiconductor device 5 can be improved.

【0031】本発明は上記し且つ図面に記載した実施例
にのみ限定されるものではなく、次のような変形または
拡張が可能である。第2または第3実施例において、治
具6または7を適当な温度に加熱した状態で、封止樹脂
4の表面に押当てるようにしても良い。斯様にすれば、
封止樹脂4の硬化が促進されて、硬化に要する時間を短
縮することができる。また、封止樹脂4を半硬化させる
加熱処理を行わずに、治具6または7を半硬化させる加
熱条件で加熱して、補助V溝4aまたは補助溝4bを形
成するようにしても良い。斯様にすれば、治具6または
7を封止樹脂4の表面に押当てた状態で所要時間が経過
すれば封止樹脂4を半硬化させることができるので、半
硬化処理工程を別個に行う必要がなくなる。
The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. In the second or third embodiment, the jig 6 or 7 may be pressed against the surface of the sealing resin 4 while being heated to an appropriate temperature. In this way,
The curing of the sealing resin 4 is accelerated, and the time required for curing can be reduced. Alternatively, the auxiliary V-groove 4a or the auxiliary groove 4b may be formed by heating under a heating condition of semi-curing the jig 6 or 7 without performing the heat treatment for semi-curing the sealing resin 4. By doing so, the sealing resin 4 can be semi-cured if the required time elapses while the jig 6 or 7 is pressed against the surface of the sealing resin 4, so that the semi-curing process is separately performed. There is no need to do it.

【0032】ベース基板1に形成するV溝1aは、部品
面のみ或いは部品面と反対側の面のみに設けても良い。
ベース基板は6個取りに限らない。また、各実施例中に
示した寸法は一例であり、適宜変更して実施が可能であ
る。ベース基板の周辺に形成される耳部は、必要に応じ
て設ければ良い。治具の形状は、複数枚の刃先を格子状
に組み合わせたものに限らず、1枚の刃先からなるもの
でも良く、斯様な治具を、ベース基板の単位区画の寸法
に合わせて移動させながら、封止樹脂に複数回押当てる
ことによって補助分割溝部を形成しても良い。
The V-groove 1a formed in the base substrate 1 may be provided only on the component surface or only on the surface opposite to the component surface.
The number of base substrates is not limited to six. In addition, the dimensions shown in each embodiment are merely examples, and can be implemented by appropriately changing the dimensions. The ears formed around the base substrate may be provided as needed. The shape of the jig is not limited to one in which a plurality of blades are combined in a lattice shape, and may be one formed of one blade. Such a jig is moved according to the size of a unit section of the base substrate. The auxiliary division groove may be formed by pressing the sealing resin a plurality of times.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例における、ベース基板のベ
アチップ搭載面全体に亘って封止樹脂を塗布した状態を
示す概略的な断面図
FIG. 1 is a schematic cross-sectional view showing a state where a sealing resin is applied over the entire bare chip mounting surface of a base substrate in a first embodiment of the present invention.

【図2】単位区画毎に分割された半導体装置の概略的な
断面図
FIG. 2 is a schematic cross-sectional view of a semiconductor device divided into unit sections.

【図3】ベアチップ及びその他部品が搭載された状態の
ベース基板の平面図
FIG. 3 is a plan view of a base substrate on which a bare chip and other components are mounted.

【図4】本発明の第2実施例を示す図1相当図FIG. 4 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

【図5】治具の上下を反転してその刃先の形状を部分的
に示す斜視図
FIG. 5 is a perspective view showing the shape of the cutting edge of the jig by turning the jig upside down;

【図6】実施態様の変形を示す図1相当図FIG. 6 is a view corresponding to FIG. 1 showing a modification of the embodiment.

【図7】本発明の第3実施例を示す図1相当図FIG. 7 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

【図8】図5相当図FIG. 8 is a diagram corresponding to FIG. 5;

【図9】封止樹脂とベース基板との接合面の一端部にお
いて、分割端部の湾曲形状が示す傾き角θを表した図
FIG. 9 is a diagram illustrating an inclination angle θ indicated by a curved shape of a divided end portion at one end of a bonding surface between a sealing resin and a base substrate.

【符号の説明】 1はベース基板、1aはV溝(分割溝部)、1bは単位
区画、2はベアチップ、4は封止樹脂、4a及び4a′
は補助V溝(補助分割溝部)、4bは補助溝(補助分割
溝部)、4cは分割端部、5は半導体装置、6及び7は
治具を示す。
[Description of Signs] 1 is a base substrate, 1a is a V-groove (divided groove portion), 1b is a unit section, 2 is a bare chip, 4 is a sealing resin, 4a and 4a '
Denotes an auxiliary V-groove (auxiliary division groove), 4b denotes an auxiliary groove (auxiliary division groove), 4c denotes a division end, 5 denotes a semiconductor device, and 6 and 7 denote jigs.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路のベアチップが単位区画
毎に搭載されると共に、該単位区画分割用の分割溝部が
形成されているパッケージ用のベース基板に、熱硬化性
の封止樹脂をベアチップの搭載面全体に亘って塗布する
工程と、 前記封止樹脂を硬化させる工程と、 前記ベース基板を、当該ベース基板に形成されている前
記分割溝部に沿って分割する工程とからなることを特徴
とする半導体装置の製造方法。
1. A bare chip of a semiconductor integrated circuit is mounted in each unit section, and a thermosetting sealing resin is provided on a base substrate for a package in which a division groove for dividing the unit section is formed. A step of applying over the entire mounting surface; a step of curing the sealing resin; and a step of dividing the base substrate along the division grooves formed on the base substrate. Semiconductor device manufacturing method.
【請求項2】 半導体集積回路のベアチップが単位区画
毎に搭載されると共に、該単位区画分割用の分割溝部が
形成されているパッケージ用のベース基板に、熱硬化性
の封止樹脂をベアチップの搭載面全体に亘って塗布する
工程と、 前記封止樹脂を半硬化させる工程と、 前記ベース基板に形成されている分割溝部に対応する位
置の前記封止樹脂表面に、治具を押当てることにより補
助分割溝部を形成する工程と、 前記封止樹脂を硬化させる工程と、 前記ベース基板を、前記分割溝部に沿って分割する工程
とからなることを特徴とする半導体装置の製造方法。
2. A bare chip of a semiconductor integrated circuit is mounted in each unit section, and a thermosetting sealing resin is provided on a base substrate for a package in which a division groove for unit division is formed. Applying over the entire mounting surface, semi-curing the sealing resin, and pressing a jig against the sealing resin surface at a position corresponding to the dividing groove formed on the base substrate. A method of forming an auxiliary division groove by the method, a step of curing the sealing resin, and a step of dividing the base substrate along the division groove.
【請求項3】 前記治具は、加熱されていることを特徴
とする請求項2記載の半導体装置の製造方法。
3. The method according to claim 2, wherein the jig is heated.
【請求項4】 前記封止樹脂表面に形成される前記補助
分割溝部の深さは、塗布した封止樹脂の厚さ寸法と略等
しくなるように設定されることを特徴とする請求項2ま
たは3記載の半導体装置の製造方法。
4. The method according to claim 2, wherein a depth of the auxiliary dividing groove formed on the surface of the sealing resin is set to be substantially equal to a thickness dimension of the applied sealing resin. 4. The method for manufacturing a semiconductor device according to item 3.
【請求項5】 前記封止樹脂表面に形成される前記補助
分割溝部の形状は、前記単位区画毎の封止樹脂の分割端
部が湾曲形状となるように形成されていることを特徴と
する請求項2乃至4の何れかに記載の半導体装置の製造
方法。
5. The shape of the auxiliary dividing groove formed on the surface of the sealing resin is such that the dividing end of the sealing resin for each unit section has a curved shape. A method for manufacturing a semiconductor device according to claim 2.
JP18502397A 1997-07-10 1997-07-10 Manufacture of semiconductor device Pending JPH1131704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18502397A JPH1131704A (en) 1997-07-10 1997-07-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18502397A JPH1131704A (en) 1997-07-10 1997-07-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH1131704A true JPH1131704A (en) 1999-02-02

Family

ID=16163436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18502397A Pending JPH1131704A (en) 1997-07-10 1997-07-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH1131704A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277550A (en) * 1999-03-25 2000-10-06 Mitsubishi Electric Corp Semiconductor device and its manufacture
US7223636B2 (en) 2003-10-28 2007-05-29 Renesas Technology Corp. Manufacturing method of semiconductor device and semiconductor device
US7709941B2 (en) 2004-03-24 2010-05-04 Sanyo Electric Co., Ltd. Resin-sealed semiconductor device and method of manufacturing the same
US7948059B2 (en) 2006-03-17 2011-05-24 Hitachi Metals, Ltd. Dividable semiconductor device having ceramic substrate and surface mount components collectively sealed on principle surface of ceramic substrate
JP2017112264A (en) * 2015-12-17 2017-06-22 株式会社ディスコ Wafer processing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277550A (en) * 1999-03-25 2000-10-06 Mitsubishi Electric Corp Semiconductor device and its manufacture
US7223636B2 (en) 2003-10-28 2007-05-29 Renesas Technology Corp. Manufacturing method of semiconductor device and semiconductor device
US7709941B2 (en) 2004-03-24 2010-05-04 Sanyo Electric Co., Ltd. Resin-sealed semiconductor device and method of manufacturing the same
US7948059B2 (en) 2006-03-17 2011-05-24 Hitachi Metals, Ltd. Dividable semiconductor device having ceramic substrate and surface mount components collectively sealed on principle surface of ceramic substrate
JP2017112264A (en) * 2015-12-17 2017-06-22 株式会社ディスコ Wafer processing method

Similar Documents

Publication Publication Date Title
US7443022B2 (en) Board-on-chip packages
US5936304A (en) C4 package die backside coating
US20040043537A1 (en) Method of manufacturing a semiconductor device having a flexible wiring substrate
JPH1174296A (en) Manufacture of semiconductor package
US20090039506A1 (en) Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof
JP2004349728A (en) Method for manufacturing encapsulated electronic component, particularly integrated circuit
US7652385B2 (en) Semiconductor device and method of manufacturing the same
JP3522177B2 (en) Method for manufacturing semiconductor device
JPH1131704A (en) Manufacture of semiconductor device
KR100495644B1 (en) Method for manufacturing semiconductor devices
JP3879823B2 (en) Thin semiconductor device molding method and mold
JP2003249510A (en) Method for sealing semiconductor
CN100559572C (en) Electronic device and manufacture method thereof
JPH10172446A (en) Gas discharge type display device and manufacture thereof
JP4010860B2 (en) Hybrid integrated circuit device and manufacturing method thereof
JPH10209194A (en) Semiconductor device, its manufacture, and device for resin molding process used therefor
JPH1168254A (en) Optical module and manufacture of optical module
JP2005158873A (en) Method of manufacturing semiconductor device
JP3345759B2 (en) Semiconductor device and method of manufacturing the same
JP3472342B2 (en) Method of manufacturing semiconductor device package
JPH05275570A (en) Semiconductor device
TW499750B (en) Substrate strip and its manufacturing method
CA1213678A (en) Lead frame for plastic encapsulated semiconductor device
JP2005251900A (en) Jig for manufacturing electronic device, jig set for manufacturing electronic device, method of manufacturing electronic device using the jig set, and apparatus of manufacturing electronic device using the jig set
JP2000208559A (en) Resin-sealed semiconductor device and production thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040210

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040409

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20050719