JPH1126680A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH1126680A JPH1126680A JP9182005A JP18200597A JPH1126680A JP H1126680 A JPH1126680 A JP H1126680A JP 9182005 A JP9182005 A JP 9182005A JP 18200597 A JP18200597 A JP 18200597A JP H1126680 A JPH1126680 A JP H1126680A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element mounting
- mounting portion
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に用い
られる半導体装置用リードフレームに係わり、特に半導
体素子を搭載する半導体素子搭載部（ダイパット）を備
えた半導体装置用リードフレームの半導体素子搭載部の
形状に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device used for a semiconductor device, and more particularly to a semiconductor device mounting portion of a semiconductor device lead frame having a semiconductor device mounting portion (die pad) for mounting a semiconductor device. It is related to the shape of.
【０００２】[0002]
【従来の技術】一般に、半導体装置用リードフレームと
しては、その材料や形状等において多種多様のものが存
在するが、その一つとして、例えば図４に示すように構
成された樹脂封止型半導体装置（以下、単に半導体装置
と称す）に用いられるものが広く知られている。2. Description of the Related Art In general, there are various types of lead frames for semiconductor devices in their materials and shapes. One of them is a resin-encapsulated semiconductor device as shown in FIG. Devices used for devices (hereinafter simply referred to as semiconductor devices) are widely known.
【０００３】この半導体装置では、例えば０．１〜０．
２mm厚の銅系合金材料からなるリードフレームの半導体
素子搭載部１０に、シリコン系材料等からなる半導体素
子１１が接着剤１２を介して搭載されるとともに、この
半導体素子１１がボンディングワイヤー１３によりリー
ドフレームの内部導出リード１４と電気的に接続されて
おり、さらにはこれらの各部がエポキシ樹脂等の封止樹
脂１５によって封止されている。また、封止樹脂１５か
らは、リードフレームの外部導出リード１６が、外装メ
ッキおよび成形加工等が加えられた状態で突出してい
る。[0003] In this semiconductor device, for example, 0.1-0.
A semiconductor element 11 made of a silicon-based material or the like is mounted on a semiconductor element mounting portion 10 of a lead frame made of a copper-based alloy material having a thickness of 2 mm via an adhesive 12, and the semiconductor element 11 is lead-bonded by a bonding wire 13. The lead is electrically connected to the lead-out lead 14 inside the frame, and these parts are sealed with a sealing resin 15 such as an epoxy resin. Further, the external lead 16 of the lead frame protrudes from the sealing resin 15 in a state where exterior plating, molding, and the like are applied.
【０００４】このような半導体装置に用いられるリード
フレームでは、従来、半導体素子１１を搭載する半導体
素子搭載部１０が、図５に示すように形成されている。
すなわち、半導体素子搭載部１０は、略方形の平板状に
形成されており、さらに半導体素子１１搭載面からその
裏面へ貫通するスリット１７が、格子状に配設されてい
る。これらのスリット１７は、半導体素子搭載部１０の
耐クラック性向上のために設けられている。In a lead frame used in such a semiconductor device, a semiconductor element mounting portion 10 for mounting a semiconductor element 11 is conventionally formed as shown in FIG.
That is, the semiconductor element mounting portion 10 is formed in a substantially rectangular flat plate shape, and the slits 17 penetrating from the mounting surface of the semiconductor element 11 to the back surface thereof are arranged in a lattice shape. These slits 17 are provided for improving crack resistance of the semiconductor element mounting portion 10.
【０００５】ここで、このような半導体装置用リードフ
レームを用いて、上述したような半導体装置を構成する
場合の組立手順について、図６を参照しながら説明す
る。先ず、図６（ａ）に示すように、半導体素子搭載部
１０に例えば熱硬化性の接着剤１２を塗布し、続いて図
６（ｂ）に示すように、半導体素子搭載部１０上に半導
体素子１１を搭載する。そして、これらを例えば１５０
℃程度で１〜２時間加熱することで接着剤１２の硬化を
促進させる。Here, an assembling procedure when the above-described semiconductor device is constructed using such a semiconductor device lead frame will be described with reference to FIG. First, as shown in FIG. 6A, for example, a thermosetting adhesive 12 is applied to the semiconductor element mounting portion 10, and then, as shown in FIG. The element 11 is mounted. And these are, for example, 150
The curing of the adhesive 12 is promoted by heating at about ° C for 1 to 2 hours.
【０００６】次いで、図６（ｃ）に示すように、ボンデ
ィングワイヤー１３により半導体素子１１と内部導出リ
ード１４とを電気的に接続する。この接続は、加熱処理
を必要とする方法により行うこともある。ボンディング
ワイヤー１３による接続が完了すると、これらの各部を
所定の金型に挟み込み、図６（ｄ）に示すように、エポ
キシ樹脂等を溶融した封止樹脂１５を流し込み、その封
止樹脂１５を硬化させて封止する。このとき、封止樹脂
１５を流し込む際および乾燥させるために加熱処理が行
われる。そして、最後に外部導出リード１６を所定の形
に成形して、図６（ｅ）に示すような半導体装置を形成
する。Next, as shown in FIG. 6C, the semiconductor element 11 and the internal lead 14 are electrically connected by a bonding wire 13. This connection may be made by a method requiring a heat treatment. When the connection with the bonding wire 13 is completed, these parts are sandwiched between predetermined molds, and as shown in FIG. And sealed. At this time, a heat treatment is performed when the sealing resin 15 is poured and for drying. Finally, the external lead 16 is formed into a predetermined shape to form a semiconductor device as shown in FIG.
【０００７】[0007]
【発明が解決しようとする課題】ところで、上述した半
導体装置のうち、銅系合金材料からなる半導体素子搭載
部１０と、シリコン系材料等からなる半導体素子１１と
では、その熱膨張係数が異なる。そのために、上述した
組立手順のように、例えば半導体素子搭載部１０と半導
体素子１１とを接着する接着剤１２の硬化促進のための
加熱処理を行うと、半導体装置では、接着剤１２の硬化
後に変形等が発生してしまう可能性がある。In the above-mentioned semiconductor device, the semiconductor element mounting portion 10 made of a copper-based alloy material and the semiconductor element 11 made of a silicon-based material have different thermal expansion coefficients. For this reason, as in the above-described assembling procedure, for example, when heat treatment for accelerating the curing of the adhesive 12 that bonds the semiconductor element mounting portion 10 and the semiconductor element 11 is performed, in the semiconductor device, after the adhesive 12 is cured, Deformation or the like may occur.
【０００８】これを図７を参照しながら詳細に説明す
る。図７は、図４中のＢ−Ｂ断面から見た場合の搭載手
順を示す図である。図７（ａ）は、半導体素子搭載部１
０上に半導体素子１１を搭載した直後を示す。このと
き、接着剤１２は未乾燥状態である。その後、接着剤１
２を乾燥させるために、半導体素子搭載部１０および半
導体素子１１を含めて加熱処理を行うと、半導体素子搭
載部１０および半導体素子１１には、図７（ｂ）に示す
ように、それぞれの熱膨張係数に応じて熱膨張が生じ
る。例えば、半導体素子搭載部１０の熱膨張係数のほう
が半導体素子１１の熱膨張係数よりも大きければ、半導
体素子搭載部１０は、半導体素子搭載部１１よりも大き
く熱膨張する。This will be described in detail with reference to FIG. FIG. 7 is a diagram showing a mounting procedure when viewed from the BB section in FIG. FIG. 7A shows the semiconductor element mounting section 1.
0 shows the state immediately after the semiconductor element 11 is mounted. At this time, the adhesive 12 is in an undried state. Then, adhesive 1
When the heat treatment is performed on the semiconductor element mounting part 10 and the semiconductor element 11 in order to dry the semiconductor element 2, the semiconductor element mounting part 10 and the semiconductor element 11 are heated as shown in FIG. Thermal expansion occurs according to the expansion coefficient. For example, if the thermal expansion coefficient of the semiconductor element mounting part 10 is larger than the thermal expansion coefficient of the semiconductor element 11, the semiconductor element mounting part 10 expands more thermally than the semiconductor element mounting part 11.
【０００９】そして、加熱による接着剤１２の硬化後、
常温状態に戻して、半導体素子搭載部１０と半導体素子
１１との接着を完了する。ところが、接着剤１２は半導
体素子搭載部１０および半導体素子１１が熱膨張した状
態で硬化している。しかも、半導体素子搭載部１０と半
導体素子１１とは、いずれも部材の連続性を有してい
る。したがって、これらを常温状態に戻すことによって
半導体素子搭載部１０および半導体素子１１が収縮する
と、その熱膨張係数の違いから、例えば半導体素子搭載
部１０の収縮の度合いのほうが大きくなってしまい、図
７（ｃ）に示すように半導体素子搭載部１０と半導体素
子１１との間で反り等の変形が発生してしまう。After the adhesive 12 is cured by heating,
After returning to the normal temperature state, the bonding between the semiconductor element mounting portion 10 and the semiconductor element 11 is completed. However, the adhesive 12 is hardened while the semiconductor element mounting portion 10 and the semiconductor element 11 are thermally expanded. Moreover, both the semiconductor element mounting portion 10 and the semiconductor element 11 have continuity of members. Therefore, when the semiconductor element mounting portion 10 and the semiconductor element 11 shrink by returning them to the normal temperature state, for example, the degree of shrinkage of the semiconductor element mounting portion 10 becomes larger due to the difference in the coefficient of thermal expansion. As shown in (c), deformation such as warpage occurs between the semiconductor element mounting portion 10 and the semiconductor element 11.
【００１０】このような半導体素子搭載部１０と半導体
素子１１との間の変形は、半導体装置自体の形状の変化
も招いてしまう。よって、例えば、外部導出リード１６
の位置が安定せずに、半導体装置が不良品となってしま
う可能性がある。その他にも、組み立て過程および半導
体装置実装時における加熱および冷却に起因する変形に
より、半導体素子１１にストレスを与え、これによりそ
の機能の破損を引き起こすといった不具合が生じてしま
うことがある。Such a deformation between the semiconductor element mounting portion 10 and the semiconductor element 11 causes a change in the shape of the semiconductor device itself. Therefore, for example, the external lead 16
May not be stable and the semiconductor device may be defective. In addition, due to deformation caused by heating and cooling during the assembling process and mounting of the semiconductor device, stress may be applied to the semiconductor element 11, thereby causing a problem that the function of the semiconductor element 11 is damaged.
【００１１】そこで、本発明は、半導体装置の組立手順
において加熱処理を必要とする工程が存在しても、半導
体素子搭載部と半導体素子との間の熱膨張係数の差に起
因する変形を極力抑えることのできる半導体装置用リー
ドフレームを提供することを目的とする。Therefore, the present invention minimizes deformation caused by a difference in thermal expansion coefficient between a semiconductor element mounting portion and a semiconductor element even if a step requiring heat treatment is present in a semiconductor device assembling procedure. It is an object of the present invention to provide a semiconductor device lead frame that can be suppressed.
【００１２】[0012]
【課題を解決するための手段】本発明は、上記目的を達
成するために案出された半導体装置用リードフレーム
で、半導体素子が搭載される平板状の半導体素子搭載部
を備えるとともに、前記半導体素子と異なる熱膨張係数
の部材により形成されたリードフレームにおいて、前記
半導体素子搭載部には、前記半導体素子の搭載面からそ
の裏面へ貫通する複数のスリット部が設けられ、さら
に、前記複数のスリット部は、前記半導体素子搭載部の
中心点近傍を通る全ての仮想直線および前記半導体素子
搭載部の縁部とこれに対向する縁部とを結ぶ全ての仮想
直線のそれぞれが、少なくとも一つのスリット部を通過
するように、前記半導体素子搭載部上に配置されている
ことを特徴とするものである。According to the present invention, there is provided a lead frame for a semiconductor device devised to achieve the above object, comprising a flat semiconductor element mounting portion on which a semiconductor element is mounted, and a semiconductor device. In a lead frame formed of a member having a thermal expansion coefficient different from that of the element, the semiconductor element mounting portion is provided with a plurality of slits penetrating from a mounting surface of the semiconductor element to a back surface thereof, and further includes a plurality of slits. Each virtual straight line connecting the edge of the semiconductor element mounting portion and the edge facing the virtual straight line passing near the center point of the semiconductor element mounting portion has at least one slit portion. Are arranged on the semiconductor element mounting portion so as to pass through.
【００１３】上記構成の半導体装置用リードフレームに
よれば、半導体素子搭載部上において、その中心点近傍
を通る仮想直線およびその縁部とこれに対向する縁部と
を結ぶ全ての仮想直線のそれぞれが、少なくとも一つの
スリット部を通過するように、各スリット部が配置され
ている。よって、これらの仮想直線上における半導体素
子搭載部の断面には、必ずスリット部が含まれる。つま
り、半導体素子搭載部は、各断面において部材の連続性
を有することがない。したがって、この半導体装置用リ
ードフレームでは、例えば半導体素子搭載部上に半導体
素子を搭載する過程等で加熱処理が行われても、半導体
素子搭載部と半導体素子との熱膨張による変形量の差が
スリット部によって吸収され、熱膨張係数の違いによる
変形の発生が極力抑えられる。According to the lead frame for a semiconductor device having the above-described structure, on the semiconductor element mounting portion, each of the virtual straight line passing near the center point and all the virtual straight lines connecting the edge portion and the edge portion facing the virtual straight line. However, each slit portion is arranged so as to pass through at least one slit portion. Therefore, the cross section of the semiconductor element mounting portion on these virtual straight lines always includes the slit portion. That is, the semiconductor element mounting portion does not have continuity of members in each cross section. Therefore, in this semiconductor device lead frame, even if heat treatment is performed, for example, in the process of mounting the semiconductor element on the semiconductor element mounting section, the difference in the amount of deformation between the semiconductor element mounting section and the semiconductor element due to thermal expansion is small. It is absorbed by the slit portion, and the occurrence of deformation due to a difference in thermal expansion coefficient is suppressed as much as possible.
【００１４】[0014]
【発明の実施の形態】以下、図面に基づき本発明に係わ
る半導体装置用リードフレームについて説明する。ただ
し、ここでは、既に説明した樹脂封止型半導体装置に用
いられる半導体装置用リードフレームに、本発明を適用
した場合を例に挙げて説明する。図１は、本発明に係わ
る半導体装置用リードフレームの一例の半導体素子搭載
部の形状を示す平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame for a semiconductor device according to the present invention will be described below with reference to the drawings. However, here, a case in which the present invention is applied to a semiconductor device lead frame used in the resin-encapsulated semiconductor device described above will be described as an example. FIG. 1 is a plan view showing the shape of a semiconductor element mounting portion of an example of a lead frame for a semiconductor device according to the present invention.
【００１５】図例のように、この半導体装置用リードフ
レームは、略方形の平板状に形成された半導体素子搭載
部１を備えており、さらには半導体素子搭載部１に複数
のスリット部、すなわち第１のスリット部２および第２
のスリット部３が設けられている。As shown in the drawing, the lead frame for a semiconductor device includes a semiconductor element mounting portion 1 formed in a substantially rectangular flat plate shape. Further, the semiconductor element mounting portion 1 has a plurality of slits, ie, a plurality of slits. First slit part 2 and second slit part
Are provided.
【００１６】第１のスリット部２は、半導体素子搭載部
１の中心点近傍を中心にして、その半導体素子搭載部１
上のそれぞれの対角線に沿って、略十字状に形成された
開口からなるものである。なお、略十字状に形成された
第１のスリット部２のそれぞれの端部（４か所）は、Ｒ
形状にすると加工が容易になる。The first slit portion 2 is provided around the center point of the semiconductor element mounting portion 1.
It consists of openings formed in a substantially cross shape along the respective diagonals above. In addition, each end (four places) of the first slit part 2 formed in a substantially cross shape is R
Processing becomes easier when the shape is formed.
【００１７】第２のスリット部３は、略方形の半導体素
子搭載部１の４つの端辺（以下、縁部と称す）の中央近
傍から、半導体素子搭載部１の中心点近傍に向けて、そ
れぞれの箇所に形成された切り欠きからなるものであ
る。なお、第２のスリット部３の半導体素子搭載部１中
心点近傍側の端部も、第１のスリット部２と同様にＲ形
状にすると加工が容易になる。The second slit portion 3 extends from near the center of four edges (hereinafter, referred to as edges) of the substantially rectangular semiconductor element mounting portion 1 to near the center of the semiconductor element mounting portion 1. It consists of notches formed at each location. The end of the second slit portion 3 near the center of the semiconductor element mounting portion 1 is also formed in an R-shape in the same manner as the first slit portion 2 to facilitate processing.
【００１８】また、第２のスリット部３は、その半導体
素子搭載部１中心点近傍側の端部が、その第２のスリッ
ト部３が設けられた側における第１のスリット部２の端
部（２か所）を結ぶ線よりも、半導体素子搭載部１中心
点近傍側に達している。The second slit 3 has an end near the center point of the semiconductor element mounting portion 1 and an end of the first slit 2 on the side where the second slit 3 is provided. It reaches the vicinity of the center point of the semiconductor element mounting part 1 from the line connecting the (two places).
【００１９】このように、半導体素子搭載部１には、第
１のスリット部２と、４つの第２のスリット部３とが、
配置されている。これにより、半導体素子搭載部１上で
は、半導体素子搭載部１の中心点近傍を通る全ての仮想
直線４が、第１のスリット部２を通過するようになる。
さらには、半導体素子搭載部１の縁部とこれに対向する
縁部とを結ぶ全ての仮想直線５，６が、第１のスリット
部２と第２のスリット部３とのいずれか一方または両方
を通過するようになる。As described above, the first slit portion 2 and the four second slit portions 3 are formed in the semiconductor element mounting portion 1.
Are located. Thereby, on the semiconductor element mounting portion 1, all the virtual straight lines 4 passing near the center point of the semiconductor element mounting portion 1 pass through the first slit portion 2.
Furthermore, all the virtual straight lines 5 and 6 connecting the edge of the semiconductor element mounting portion 1 and the edge facing the edge are formed with one or both of the first slit portion 2 and the second slit portion 3. Will pass through.
【００２０】つまり、半導体素子搭載部１上では、半導
体素子搭載部１の中心点近傍を通る全ての仮想直線４
と、半導体素子搭載部１の縁部とこれに対向する縁部と
を結ぶ全ての仮想直線５，６とのそれぞれが、少なくと
も第１のスリット部２と第２のスリット部３とのいずれ
かを通過するように、第１のスリット部２と第２のスリ
ット部３とが配置されている。したがって、これらの仮
想直線４，５，６上における半導体素子搭載部１の断面
には、必ず第１のスリット部２または第２のスリット部
３が含まれることとなり、結果として半導体素子搭載部
１は各断面において部材の連続性を有することがなくな
る。That is, on the semiconductor element mounting portion 1, all virtual straight lines 4 passing near the center of the semiconductor element mounting portion 1
And all of the virtual straight lines 5 and 6 connecting the edge of the semiconductor element mounting portion 1 and the edge facing the edge are at least one of the first slit portion 2 and the second slit portion 3. The first slit portion 2 and the second slit portion 3 are arranged so as to pass through. Therefore, the cross section of the semiconductor element mounting portion 1 on these virtual straight lines 4, 5, 6 always includes the first slit portion 2 or the second slit portion 3, and as a result, the semiconductor element mounting portion 1 Does not have continuity of members in each section.
【００２１】ここで、このように構成された半導体装置
用リードフレームを用いて半導体装置を構成する手順、
特に半導体素子搭載部１上に半導体素子１１を搭載する
手順について説明する。図２は、図１中のＡ−Ａ断面か
ら見た場合の手順を示す図である。なお、半導体素子搭
載部１上に搭載する半導体素子１１およびこれらを接着
する接着剤１２は、既に説明した従来の場合と同一のも
のとする。Here, a procedure for configuring a semiconductor device using the semiconductor device lead frame configured as described above,
In particular, a procedure for mounting the semiconductor element 11 on the semiconductor element mounting section 1 will be described. FIG. 2 is a diagram showing a procedure when viewed from the AA cross section in FIG. The semiconductor elements 11 mounted on the semiconductor element mounting section 1 and the adhesive 12 for bonding them are the same as those in the conventional case described above.
【００２２】図２（ａ）は、半導体素子搭載部１上に半
導体素子１１を搭載した直後を示す。このとき、接着剤
１２は未乾燥状態である。その後、接着剤１２を乾燥さ
せるために、半導体素子搭載部１および半導体素子１１
を含めて加熱処理を行うと、半導体素子搭載部１および
半導体素子１１には、図２（ｂ）に示すように、それぞ
れの熱膨張係数に応じて熱膨張が生じる。そして、加熱
による接着剤１２の硬化後、常温状態に戻して、半導体
素子搭載部１と半導体素子１１との接着を完了する。こ
のとき、半導体素子搭載部１と半導体素子１１とには、
常温状態に戻すことにより、熱膨張前の状態への収縮が
生じる。FIG. 2A shows a state immediately after the semiconductor element 11 is mounted on the semiconductor element mounting section 1. At this time, the adhesive 12 is in an undried state. Thereafter, the semiconductor element mounting portion 1 and the semiconductor element 11 are dried in order to dry the adhesive 12.
Is performed, the semiconductor element mounting portion 1 and the semiconductor element 11 undergo thermal expansion according to their respective thermal expansion coefficients, as shown in FIG. 2B. Then, after the adhesive 12 is cured by heating, the temperature is returned to a normal temperature state, and the bonding between the semiconductor element mounting portion 1 and the semiconductor element 11 is completed. At this time, the semiconductor element mounting portion 1 and the semiconductor element 11
By returning to the normal temperature state, contraction to a state before thermal expansion occurs.
【００２３】ところが、半導体素子搭載部１の断面に
は、第１のスリット部２が含まれている。つまり、半導
体素子搭載部１は、部材の連続性を有していない。した
がって、接着剤１２が半導体素子搭載部１および半導体
素子１１が熱膨張した状態で硬化し、その後にこれらを
常温状態に戻すことによって半導体素子搭載部１および
半導体素子２が収縮しても、第１のスリット部２がニゲ
として機能し、半導体素子搭載部１と半導体素子１１と
の熱膨張による変形量の差が第１のスリット部２によっ
て吸収されるので、図２（ｃ）に示すように、その熱膨
張係数の違いに起因する反り等の変形が発生し難くな
る。これは、上述した全ての仮想直線４，５，６上の断
面についても同様である。However, the cross section of the semiconductor element mounting portion 1 includes the first slit portion 2. That is, the semiconductor element mounting portion 1 does not have continuity of members. Therefore, even if the adhesive 12 hardens in a state where the semiconductor element mounting part 1 and the semiconductor element 11 are thermally expanded, and then returns to a normal temperature state, the semiconductor element mounting part 1 and the semiconductor element 2 shrink. The first slit portion 2 functions as a relief, and the difference in the amount of deformation due to thermal expansion between the semiconductor element mounting portion 1 and the semiconductor element 11 is absorbed by the first slit portion 2, as shown in FIG. In addition, deformation such as warpage due to the difference in the coefficient of thermal expansion hardly occurs. This is the same for the cross sections on all the imaginary straight lines 4, 5, and 6 described above.
【００２４】また、半導体素子搭載部１と半導体素子２
とでは、銅系合金材料からなる半導体素子搭載部１のほ
うが、シリコン系材料等からなる半導体素子１１より
も、熱膨張係数が大きいのが一般的である。Further, the semiconductor element mounting portion 1 and the semiconductor element 2
In general, the semiconductor element mounting portion 1 made of a copper alloy material has a larger thermal expansion coefficient than the semiconductor element 11 made of a silicon material or the like.
【００２５】これに対して、この半導体素子搭載部１で
は、各仮想直線４，５，６上の断面には第１のスリット
部２と第２のスリット部３とのいずれかが含まれている
ので、これらがいずれも含まれていない場合に比べて、
その断面積が小さくなり、熱膨張による変形量を小さく
することができる。さらに、半導体素子搭載部１に熱膨
張による変形が発生した場合に、第１のスリット部２ま
たは第２のスリット部３は、その大きさが小さくなる方
向に変形する。これにより、この半導体素子搭載部１で
は、第１のスリット部２または第２のスリット部３がい
ずれかも含まれていない場合に比べて、半導体素子搭載
部１全体の熱膨張による変形量、すなわち半導体素子搭
載部１の一端から他端までの間における熱膨張による変
形量を小さくすることができる。On the other hand, in the semiconductor element mounting portion 1, the cross section on each of the virtual straight lines 4, 5, 6 includes either the first slit portion 2 or the second slit portion 3. Compared to when none of these are included,
The cross-sectional area is reduced, and the amount of deformation due to thermal expansion can be reduced. Further, when the semiconductor element mounting portion 1 is deformed by thermal expansion, the first slit portion 2 or the second slit portion 3 is deformed in a direction in which the size is reduced. As a result, in the semiconductor element mounting part 1, the amount of deformation of the entire semiconductor element mounting part 1 due to thermal expansion, that is, the amount of deformation, that is, in comparison with the case where neither the first slit part 2 nor the second slit part 3 is included, that is, The amount of deformation due to thermal expansion between one end and the other end of the semiconductor element mounting portion 1 can be reduced.
【００２６】したがって、半導体素子搭載部１のほうが
半導体素子１１よりも熱膨張係数が大きい場合であって
も、この半導体素子搭載部１では、半導体素子１１との
間の変形量の差を少なくすることができるので、結果と
して反り等の変形が発生し難くなる。Therefore, even when the semiconductor element mounting part 1 has a larger thermal expansion coefficient than the semiconductor element 11, the difference in the amount of deformation between the semiconductor element mounting part 1 and the semiconductor element 11 is reduced. As a result, deformation such as warpage hardly occurs.
【００２７】以上のように、本実施の形態の半導体装置
用リードフレームによれば、半導体素子搭載部１が各仮
想直線４，５，６上の断面において部材の連続性を有し
ていないので、例えば半導体素子搭載部１上に半導体素
子１１を搭載する過程等で加熱処理が行われた後に冷却
されても、半導体素子搭載部１と半導体素子１１との熱
膨張による変形量の差が、第１のスリット部２または第
２のスリット部３に吸収され、これらの間の熱膨張係数
の違いに起因する反り等の変形の発生を極力抑えること
ができるようになる。As described above, according to the lead frame for a semiconductor device of the present embodiment, the semiconductor element mounting portion 1 does not have continuity of members in the cross sections on the virtual straight lines 4, 5, and 6. For example, even if the semiconductor element 11 is cooled after being subjected to a heat treatment in the process of mounting the semiconductor element 11 on the semiconductor element mounting part 1, the difference in the amount of deformation due to the thermal expansion between the semiconductor element mounting part 1 and the semiconductor element 11 becomes smaller. It is absorbed by the first slit portion 2 or the second slit portion 3 and the occurrence of deformation such as warpage due to a difference in thermal expansion coefficient between them can be suppressed as much as possible.
【００２８】そのために、本実施の形態の半導体装置用
リードフレームを用いて半導体装置を構成すれば、その
組立手順において加熱処理を必要としても、半導体装置
自体の形状の変化を招いてしまうことがなく、例えば外
部導出リード１６の位置が安定せずに、半導体装置が不
良品となってしまうといったこともなくなる。しかも、
加熱処理を行っても変形の発生を極力抑えることができ
るので、このような変形により半導体素子１１にストレ
スを与えてしまい、これによりその機能の破損を引き起
こすといった不具合も防ぐことができるようになる。Therefore, if a semiconductor device is formed using the semiconductor device lead frame of the present embodiment, a change in the shape of the semiconductor device itself may occur even if heat treatment is required in the assembly procedure. For example, the semiconductor device does not become defective because the position of the external lead 16 is not stabilized. Moreover,
Since the occurrence of deformation can be suppressed as much as possible even by performing the heat treatment, such a deformation gives stress to the semiconductor element 11, thereby preventing a problem that the function is damaged. .
【００２９】次に、本発明に係わる半導体装置用リード
フレームの他の実施の形態について説明する。図３は、
他の実施の形態における半導体装置用リードフレームの
半導体素子搭載部の形状を示す平面図である。Next, another embodiment of the lead frame for a semiconductor device according to the present invention will be described. FIG.
FIG. 15 is a plan view showing a shape of a semiconductor element mounting portion of a semiconductor device lead frame according to another embodiment.
【００３０】図例のように、この半導体装置用リードフ
レームは、略方形の平板状に形成された半導体素子搭載
部１ａに、複数のスリット部、すなわち第１のスリット
部２ａおよび第２のスリット部３ａが設けられている。As shown in the figure, the semiconductor device lead frame has a plurality of slits, that is, a first slit 2a and a second slit, formed in a semiconductor element mounting portion 1a formed in a substantially rectangular flat plate shape. A portion 3a is provided.
【００３１】第１のスリット部２ａは、半導体素子搭載
部１ａの中心点近傍を中心にして、その半導体素子搭載
部１の縁部と平行な方向に沿って、略十字状に形成され
た開口からなるものである。なお、略十字状に形成され
た第１のスリット部２のそれぞれの端部（４か所）は、
段状（クランク形状）に形成されている。The first slit portion 2a has an opening formed in a substantially cross shape along a direction parallel to the edge of the semiconductor element mounting portion 1 around the center of the semiconductor element mounting portion 1a. It consists of In addition, each end (four places) of the first slit part 2 formed in a substantially cross shape is
It is formed in a step shape (crank shape).
【００３２】第２のスリット部３ａは、略方形の半導体
素子搭載部１ａの４つの縁部の中央近傍から半導体素子
搭載部１ａの中心点近傍に向けて、なおかつ第１のスリ
ット部２ａに対応する状態で、それぞれの箇所に形成さ
れた切り欠きからなるものである。なお、第２のスリッ
ト部３ａの半導体素子搭載部１中心点近傍側の端部は、
それぞれが、第１のスリット部２ａの端部に応じた段状
（クランク形状）に形成されている。The second slit portion 3a extends from near the center of the four edges of the substantially rectangular semiconductor element mounting portion 1a to near the center point of the semiconductor element mounting portion 1a and corresponds to the first slit portion 2a. In this state, the cutouts are formed at the respective locations. The end of the second slit 3a near the center of the semiconductor element mounting portion 1 is
Each of them is formed in a step shape (crank shape) corresponding to the end of the first slit portion 2a.
【００３３】このように、第１のスリット部２ａおよび
４つの第２のスリット部３ａが配置された半導体素子搭
載部１ａにおいても、半導体素子搭載部１ａの中心点近
傍を通る全ての仮想直線４と、半導体素子搭載部１ａの
縁部とこれに対向する縁部とを結ぶ全ての仮想直線５，
６とのそれぞれが、第１のスリット部２ａと第２のスリ
ット部３とのいずれか一方または両方を通過するように
なる。As described above, even in the semiconductor element mounting portion 1a in which the first slit portion 2a and the four second slit portions 3a are arranged, all the virtual straight lines 4 passing near the center point of the semiconductor element mounting portion 1a. And all virtual straight lines 5 connecting the edge of the semiconductor element mounting portion 1a and the edge facing the same.
6 pass through one or both of the first slit portion 2 a and the second slit portion 3.
【００３４】したがって、このような形状の半導体素子
搭載部１ａを備える半導体装置用リードフレームにおい
ても、上述した場合と同様に、半導体素子搭載部１ａと
半導体素子１１との間の熱膨張係数の違いに起因する反
り等の変形の発生を極力抑えることができるようにな
る。Therefore, even in the lead frame for a semiconductor device having the semiconductor element mounting portion 1a having such a shape, the difference in the thermal expansion coefficient between the semiconductor element mounting portion 1a and the semiconductor element 11 is the same as in the case described above. This can minimize the occurrence of deformation such as warpage due to the above.
【００３５】なお、上述した実施の形態では、半導体素
子搭載部１，１ａの熱膨張係数のほうが半導体素子１１
よりも大きい場合を例に挙げて説明したが、例えばその
逆の場合であっても、半導体素子搭載部１，１ａが部材
の連続性を有さないように複数のスリット部を設けれ
ば、これらの間の熱膨張係数の違いに起因する反り等の
変形の発生を極力抑えることができるようになる。In the above-described embodiment, the thermal expansion coefficient of the semiconductor element mounting portions 1 and 1a is larger than that of the semiconductor element 11a.
Although the case where it is larger is described as an example, for example, even in the opposite case, if a plurality of slit portions are provided so that the semiconductor element mounting portions 1 and 1a do not have continuity of members, The occurrence of deformation such as warpage due to the difference in thermal expansion coefficient between them can be minimized.
【００３６】また、上述した実施の形態では、本発明
を、樹脂封止型半導体装置に用いられる半導体装置用リ
ードフレームに適用した場合について説明したが、これ
以外の半導体装置の用いられるリードフレームであって
も、組み立て過程において熱処理を要するものであれ
ば、本発明は適用可能であり、その場合にも上述と同様
の効果を得ることができる。In the above-described embodiment, the case where the present invention is applied to a lead frame for a semiconductor device used for a resin-encapsulated semiconductor device has been described. Even so, the present invention is applicable as long as heat treatment is required in the assembling process, and in such a case, the same effect as described above can be obtained.
【００３７】[0037]
【発明の効果】以上に説明したように、本発明の半導体
装置用リードフレームでは、半導体素子搭載部が部材の
連続性を有さないように、その半導体素子搭載部に複数
のスリット部が設けられているので、例えば半導体装置
の組み立て過程において加熱処理が行われても、半導体
素子搭載部と半導体素子との熱膨張による変形量の差が
スリット部によって吸収され、熱膨張係数の違いによる
変形の発生が極力抑えることができ、結果として熱膨張
による変形に起因する半導体装置の不良品発生や機能破
損等の不具合発生を防ぐことができるようになる。As described above, in the semiconductor device lead frame of the present invention, a plurality of slits are provided in the semiconductor element mounting portion so that the semiconductor element mounting portion does not have continuity of members. For example, even if heat treatment is performed in the process of assembling the semiconductor device, the difference in the amount of deformation due to thermal expansion between the semiconductor element mounting portion and the semiconductor element is absorbed by the slit portion, and the deformation due to the difference in the coefficient of thermal expansion Can be suppressed as much as possible, and as a result, it is possible to prevent defects such as defective products and functional damage of the semiconductor device caused by deformation due to thermal expansion.
【図１】本発明に係わる半導体装置用リードフレームの
実施の形態の一例における半導体素子搭載部の形状を示
す平面図である。FIG. 1 is a plan view showing a shape of a semiconductor element mounting portion in an example of an embodiment of a lead frame for a semiconductor device according to the present invention.
【図２】図１の半導体装置用リードフレームの半導体素
子搭載部に半導体素子を搭載する手順を示す説明図であ
り、（ａ）は搭載直後の状態を示す図、（ｂ）は加熱時
の状態を示す図、（ｃ）は冷却後の状態を示す図であ
る。2A and 2B are explanatory views showing a procedure for mounting a semiconductor element on a semiconductor element mounting portion of the lead frame for a semiconductor device of FIG. 1, wherein FIG. 2A is a view showing a state immediately after mounting, and FIG. FIG. 3C is a diagram illustrating a state, and FIG. 3C is a diagram illustrating a state after cooling.
【図３】本発明に係わる半導体装置用リードフレームの
他の実施の形態における半導体素子搭載部の形状を示す
平面図である。FIG. 3 is a plan view showing a shape of a semiconductor element mounting portion in another embodiment of a lead frame for a semiconductor device according to the present invention.
【図４】樹脂封止型半導体装置の概略構成の一例を示す
断面図である。FIG. 4 is a cross-sectional view illustrating an example of a schematic configuration of a resin-sealed semiconductor device.
【図５】従来の半導体装置用リードフレームにおける半
導体素子搭載部の形状を示す平面図である。FIG. 5 is a plan view showing the shape of a semiconductor element mounting portion in a conventional semiconductor device lead frame.
【図６】半導体装置用リードフレームを用いた半導体装
置の組立手順を示す説明図であり、（ａ）は半導体素子
搭載前の状態を示す図、（ｂ）は半導体素子搭載後の状
態を示す図、（ｃ）はワイヤーボンディング後の状態を
示す図、（ｄ）は樹脂封止後の状態を示す図、（ｅ）は
外部導出リード成型後のの状態を示す図である。6A and 6B are explanatory views showing a procedure for assembling a semiconductor device using a semiconductor device lead frame, wherein FIG. 6A shows a state before the semiconductor element is mounted, and FIG. 6B shows a state after the semiconductor element is mounted; FIG. 3C is a view showing a state after wire bonding, FIG. 4D is a view showing a state after resin sealing, and FIG. 4E is a view showing a state after external lead-out molding.
【図７】従来の半導体装置用リードフレームの半導体素
子搭載部に半導体素子を搭載する手順を示す説明図であ
り、（ａ）は搭載直後の状態を示す図、（ｂ）は加熱時
の状態を示す図、（ｃ）は冷却後の状態を示す図であ
る。7A and 7B are explanatory views showing a procedure for mounting a semiconductor element on a semiconductor element mounting portion of a conventional semiconductor device lead frame, wherein FIG. 7A shows a state immediately after mounting, and FIG. 7B shows a state at the time of heating. FIG. 3C is a diagram showing a state after cooling.
１…半導体素子搭載部、２，３…スリット部、４，５，
６…仮想直線、１１…半導体素子、１２…接着剤1 ... Semiconductor element mounting part, 2,3 ... Slit part, 4,5,5
6: virtual straight line, 11: semiconductor element, 12: adhesive
Claims (1)
素子搭載部を備えるとともに、前記半導体素子と異なる
熱膨張係数の部材により形成された半導体装置用リード
フレームにおいて、 前記半導体素子搭載部には、前記半導体素子の搭載面か
らその裏面へ貫通する複数のスリット部が設けられ、 前記複数のスリット部は、前記半導体素子搭載部の中心
点近傍を通る全ての仮想直線および前記半導体素子搭載
部の縁部とこれに対向する縁部とを結ぶ全ての仮想直線
のそれぞれが、少なくとも一つのスリット部を通過する
ように、前記半導体素子搭載部上に配置されていること
を特徴とする半導体装置用リードフレーム。1. A semiconductor device lead frame comprising a semiconductor element mounting portion having a plate-like shape on which a semiconductor element is mounted and having a thermal expansion coefficient different from that of the semiconductor element. A plurality of slits penetrating from a mounting surface of the semiconductor element to a back surface thereof, wherein the plurality of slits are formed by all virtual straight lines passing near a center point of the semiconductor element mounting part and the semiconductor element mounting part. A semiconductor device, wherein all virtual straight lines connecting an edge and an edge facing the edge are arranged on the semiconductor element mounting portion so as to pass through at least one slit. Lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9182005A JPH1126680A (en) | 1997-07-08 | 1997-07-08 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9182005A JPH1126680A (en) | 1997-07-08 | 1997-07-08 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1126680A true JPH1126680A (en) | 1999-01-29 |
Family
ID=16110666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9182005A Pending JPH1126680A (en) | 1997-07-08 | 1997-07-08 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1126680A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002007490A2 (en) * | 2000-07-18 | 2002-01-24 | Robert Bosch Gmbh | Assembly comprising a structured support element and a substrate functionally linked therewith |
| JP2003017625A (en) * | 2001-06-29 | 2003-01-17 | Sony Corp | Interposer and semiconductor package |
-
1997
- 1997-07-08 JP JP9182005A patent/JPH1126680A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002007490A2 (en) * | 2000-07-18 | 2002-01-24 | Robert Bosch Gmbh | Assembly comprising a structured support element and a substrate functionally linked therewith |
| WO2002007490A3 (en) * | 2000-07-18 | 2002-06-27 | Bosch Gmbh Robert | Assembly comprising a structured support element and a substrate functionally linked therewith |
| JP2003017625A (en) * | 2001-06-29 | 2003-01-17 | Sony Corp | Interposer and semiconductor package |
| JP4581301B2 (en) * | 2001-06-29 | 2010-11-17 | ソニー株式会社 | Semiconductor package |
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