JPH11312704A - ボンドパッドを有するデュアルダマスク - Google Patents

ボンドパッドを有するデュアルダマスク

Info

Publication number
JPH11312704A
JPH11312704A JP10365074A JP36507498A JPH11312704A JP H11312704 A JPH11312704 A JP H11312704A JP 10365074 A JP10365074 A JP 10365074A JP 36507498 A JP36507498 A JP 36507498A JP H11312704 A JPH11312704 A JP H11312704A
Authority
JP
Japan
Prior art keywords
layer
bond pad
forming
etching
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10365074A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11312704A5 (enExample
Inventor
Rainer Florian Schnabel
フロリアン シュナーベル ライナー
Xian J Ning
ジェイ ニン クシャン
Bruno Spuler
シュプーラー ブルーノ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPH11312704A publication Critical patent/JPH11312704A/ja
Publication of JPH11312704A5 publication Critical patent/JPH11312704A5/ja
Pending legal-status Critical Current

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    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP10365074A 1997-12-23 1998-12-22 ボンドパッドを有するデュアルダマスク Pending JPH11312704A (ja)

Applications Claiming Priority (2)

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US08/997,682 US6033984A (en) 1997-12-23 1997-12-23 Dual damascene with bond pads
US08/997682 1997-12-23

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JPH11312704A true JPH11312704A (ja) 1999-11-09
JPH11312704A5 JPH11312704A5 (enExample) 2006-02-02

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JP (1) JPH11312704A (enExample)
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TW (1) TW436930B (enExample)

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US6879049B1 (en) * 1998-01-23 2005-04-12 Rohm Co., Ltd. Damascene interconnection and semiconductor device
US6090696A (en) * 1999-10-20 2000-07-18 Taiwan Semicondutor Manufacturing Company Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6838769B1 (en) 1999-12-16 2005-01-04 Agere Systems Inc. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
GB2364170B (en) * 1999-12-16 2002-06-12 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
US6960496B2 (en) * 2003-04-03 2005-11-01 Taiwan Semiconductor Manufacturing Method of damascene process flow
US20060071304A1 (en) * 2004-09-29 2006-04-06 International Business Machines Corporation Structure and layout of a fet prime cell
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
US20120273937A1 (en) * 2011-04-30 2012-11-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
US8575022B2 (en) * 2011-11-28 2013-11-05 International Business Machines Corporation Top corner rounding of damascene wire for insulator crack suppression
US20250062124A1 (en) * 2023-08-18 2025-02-20 Tokyo Electron Limited Methods and structures for improving etch profile of underlying layers

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DE2428373C2 (de) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von weichlötbaren Anschlußkontakten auf einer Halbleiteranordnung
JPS5561027A (en) * 1978-10-30 1980-05-08 Chiyou Lsi Gijutsu Kenkyu Kumiai Gas plasma etching
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
US5773363A (en) * 1994-11-08 1998-06-30 Micron Technology, Inc. Semiconductor processing method of making electrical contact to a node
US5516710A (en) * 1994-11-10 1996-05-14 Northern Telecom Limited Method of forming a transistor
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5739563A (en) * 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
JP2728025B2 (ja) * 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
US5534460A (en) * 1995-04-27 1996-07-09 Vanguard International Semiconductor Corp. Optimized contact plug process
US5780337A (en) * 1996-09-23 1998-07-14 United Microelectronics Corporation Method of fabricating a bit line of a dynamic random access memory
US5877076A (en) * 1997-10-14 1999-03-02 Industrial Technology Research Institute Opposed two-layered photoresist process for dual damascene patterning

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US6033984A (en) 2000-03-07
TW436930B (en) 2001-05-28
EP0926721A2 (en) 1999-06-30
KR19990063359A (ko) 1999-07-26

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