TW436930B - Dual damascene with bond pads - Google Patents

Dual damascene with bond pads Download PDF

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Publication number
TW436930B
TW436930B TW087118611A TW87118611A TW436930B TW 436930 B TW436930 B TW 436930B TW 087118611 A TW087118611 A TW 087118611A TW 87118611 A TW87118611 A TW 87118611A TW 436930 B TW436930 B TW 436930B
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TW
Taiwan
Prior art keywords
layer
bonding pad
forming
item
hole
Prior art date
Application number
TW087118611A
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English (en)
Chinese (zh)
Inventor
Rainer Florian Schnabel
Xian J Ning
Bruno Spuler
Original Assignee
Siemens Ag
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Publication of TW436930B publication Critical patent/TW436930B/zh

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L2924/049Nitrides composed of metals from groups of the periodic table
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    • H01L2924/05042Si3N4
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
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    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
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    • H01L2924/3025Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
TW087118611A 1997-12-23 1998-11-09 Dual damascene with bond pads TW436930B (en)

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US08/997,682 US6033984A (en) 1997-12-23 1997-12-23 Dual damascene with bond pads

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JP (1) JPH11312704A (enExample)
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TW (1) TW436930B (enExample)

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US6090696A (en) * 1999-10-20 2000-07-18 Taiwan Semicondutor Manufacturing Company Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6838769B1 (en) 1999-12-16 2005-01-04 Agere Systems Inc. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
GB2364170B (en) * 1999-12-16 2002-06-12 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
US6960496B2 (en) * 2003-04-03 2005-11-01 Taiwan Semiconductor Manufacturing Method of damascene process flow
US20060071304A1 (en) * 2004-09-29 2006-04-06 International Business Machines Corporation Structure and layout of a fet prime cell
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
US20120273937A1 (en) * 2011-04-30 2012-11-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
US8575022B2 (en) * 2011-11-28 2013-11-05 International Business Machines Corporation Top corner rounding of damascene wire for insulator crack suppression
US20250062124A1 (en) * 2023-08-18 2025-02-20 Tokyo Electron Limited Methods and structures for improving etch profile of underlying layers

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JPS5561027A (en) * 1978-10-30 1980-05-08 Chiyou Lsi Gijutsu Kenkyu Kumiai Gas plasma etching
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
US5773363A (en) * 1994-11-08 1998-06-30 Micron Technology, Inc. Semiconductor processing method of making electrical contact to a node
US5516710A (en) * 1994-11-10 1996-05-14 Northern Telecom Limited Method of forming a transistor
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5739563A (en) * 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
JP2728025B2 (ja) * 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
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US5780337A (en) * 1996-09-23 1998-07-14 United Microelectronics Corporation Method of fabricating a bit line of a dynamic random access memory
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JPH11312704A (ja) 1999-11-09
EP0926721A3 (en) 2001-12-19
US6033984A (en) 2000-03-07
EP0926721A2 (en) 1999-06-30
KR19990063359A (ko) 1999-07-26

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