JPH11273256A - Automatic equalization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure responsiveness, convergence, and stability by accurately generating a reference signal for an input largely interfered with noises and mutual codes, in an automatic equalization circuit. SOLUTION: A transversal filter 10 equalizes the waveform of an input X recorded and reproduced based on a prescribed modulation system so as to have a characteristic similar to a prescribed PR characteristic, and outputs an output Yn. The input Yn is binarized by a code detecting circuit 102, while a reference signal generating circuit 103 generates a reference signal Bn-1 from successive three binary signals. An adder 104 adds a signal Yn-1 wherein the output Yn is delayed by a delayer 116 and a reference signal Bn-1, and outputs an equalization error signal ERRn-1. A coefficient updating circuit 105 updates tap coefficients K-2 to K+2 of the transversal filter 101 in accordance with the equalization error signal ERRn-1. The precise reference signal Bn-1 is generated from the successive three binary signals conforming to a state transition permitting state transition which does not appear on a state transition drawing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to RLL (1, 7) encoding and PR used in the field of high-density recording and reproduction.
At the time of the combination of (1, 2, 1) equalization, it operates adaptively with respect to the input signal and outputs the output of the equalization circuit to PR (1, 2).
(2) 1) The present invention relates to an automatic equalizing circuit that approaches characteristics.

[0002]

2. Description of the Related Art A conventional automatic equalizing circuit will be described with reference to FIG.

Conventionally, an automatic equalizing circuit has been disclosed in Japanese Patent Laid-Open No. 1-2723.
Japanese Unexamined Patent Application Publication No. 11-112 is known. FIG. 3 is a block diagram showing a configuration of a conventional automatic equalizing circuit. FIG.
, The transversal filter 301 includes delay units 311 to 314, multipliers 321 to 325, and an addition circuit 33.
1 and performs waveform equalization on the input X so as to be close to the desired equalization characteristic, and outputs Y (= Yi, Yi at time i
Output at T, i is any integer, T is sampling period)
Is output. The comparator 302 receives the output Yi, selects one of the most probable reference values from a plurality of reference values, and outputs the selected reference value as a reference signal Bi. The adder 304 subtracts the reference signal Bi from the output Yi to obtain an equalization error signal ERRi.
Is output. The coefficient update circuit 305 has inputs Xi + 2 to Xi
Based on i-2 and the equalization error signal ERRi, the tap coefficient sequences K-2 to K + 2 of the transversal filter 301 are updated so that the square error of the equalization error signal ERRi is minimized.

The operation of the automatic equalizing circuit configured as described above will be described below. Comparator 302
Has a plurality of reference values, and a slice level is provided between the reference values. The comparator 302 compares the level of the output Yi of the transversal filter 301 with the slice level between the reference values according to the level, selects one of the most probable reference values, and outputs it as the reference signal Bi.
The equalizer ERRi is detected by the adder 304, and the coefficient updating circuit 305 performs a transversal operation based on the inputs Xi + 2 to Xi−2 and the equalizer error ERRi so that the square error of the equalizer error ERRi is minimized. Filter 301
Is updated. In this way, waveform equalization is performed on the input X so as to be close to desired equalization characteristics, and the output Y is output.

[0005]

A comparator in a conventional automatic equalizing circuit generates a reference signal only by comparing the output level of a transversal filter with a slice level provided for a plurality of reference values. ing. Due to various noises and waveform distortions, the signal input to the reference signal generation circuit (comparator) is not ideal. In reproducing a signal recorded at high density, intersymbol interference is larger than before, and a margin for noise is often reduced. Simply assuming the ideal signal state and setting the slice level so as to divide each reference value into two, select the wrong reference value,
There is a risk of creating a reference signal by mistake. Particularly at a portion where the level difference between the slice levels is small, it is more difficult to generate an accurate reference signal by comparing the levels. Therefore, in the conventional method of creating a reference signal using a comparator, the convergence and stability of the automatic equalization circuit deteriorate by performing adaptive processing based on an equalization error detected from an erroneous reference signal. There is fear.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem, and binarizes the output of a transversal filter and creates a reference signal according to a reference signal creation procedure based on the transition of the binary signal. As a result, for an input signal with large noise or intersymbol interference, a reference signal can be accurately created even when the level difference between adjacent slice levels is small, and the response is fast, and the automatic equalization with good convergence and stability is achieved. It is intended to realize a circuit.

[0007]

To solve this problem, the present invention provides an RLL (1,7) modulation (run length limit).
ed (1,7) modulation) and NRZI (non return to zero inv
erted) Modulated and input / output X
Output Y (= Yn, Yn is the output at time nT, n is an arbitrary integer, T is an arbitrary integer, and the waveform is equalized to a characteristic close to the R (1,2,1) characteristic (partial response (1,2,1) characteristic). Is a sampling cycle) and the output Y
n is binarized on the basis of the slice level,
A code detection circuit for outputting a binary signal An, and a binary signal An
, A reference signal generating circuit for generating a reference signal Bn-1 based on the transition of the signal Yn, a delay device for delaying the output Yn by 1T and outputting a signal Yn-1, and a reference signal Bn-1 from the signal Yn-1.
And a coefficient update circuit that updates the tap coefficient of the transversal filter according to the equalization error signal ERRn−1, and a reference signal creation circuit includes: Binary signal An and binary signal A
n-1T before the binary signal An-1 and 2T of the binary signal An
An automatic equalization circuit is characterized in that a reference signal Bn-1 is created according to a total of three binary signal sequences of a previous binary signal An-2.

Further, the reference value generated by the reference signal generation circuit is defined as four values (D1, D2, D3, D4, D1> D
2>D3> D4), and the binary signal sequence An, An-1, A
When the polarity of the sign of n-2 is all "negative", D4 is output as the reference signal Bn-1, and the binary signal sequence An, An-
1, when the polarity of the signs of An-2 are all “positive”, D1
Is output as a reference signal Bn-1 and the sign of the binary signal An-1 is "positive" and the binary signal An or the binary signal A
If the polarity of at least one of n-2 is "negative", D2 is output as the reference signal Bn-1 and the binary signal A
When the polarity of the sign of n-1 is "negative" and the polarity of at least one of the binary signal An and the binary signal An-2 is "positive", D3 is output as the reference signal Bn-1. Make up.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The first invention of the present invention is the RLL
An output Y (= Yn, Yn obtained by performing (1,7) modulation and NRZI modulation and equalizing the waveform of the input / recorded / reproduced input X to a characteristic close to the PR (1,2,1) characteristic at time nT An output, n is an arbitrary integer, T is a sampling period), a transversal filter that outputs a binary signal to the output Yn based on the slice level, and a code detection circuit that outputs a binary signal An. A reference signal generation circuit for generating a reference signal Bn-1 based on the transition of the value signal An; a delay unit for delaying the output Yn by 1T to output a signal Yn-1; and a reference signal Bn-1 from the signal Yn-1. And a coefficient update circuit that updates the tap coefficient of the transversal filter according to the equalization error signal ERRn−1, and a reference signal creation circuit includes: Binary signal And n, before 1T binary signal An 2
The value signal An-1 and the binary signal A 2T before the binary signal An
n-2, a reference signal Bn-1 according to a total of three binary signal sequences.
Which generates a reference signal Bn-1 based on the transition of the binary signal An, thereby generating an adjacent slice level for an input signal having large noise or intersymbol interference. Even when the level difference between them is small, the reference signal Bn-1 can be created accurately.

According to a second aspect of the present invention, in addition to the above aspect, the reference value generated by the reference signal generation circuit is four values (D
1, D2, D3, D4, D1>D2>D3> in order of level
D4), when the sign polarity of the binary signal strings An, An-1, and An-2 are all "negative", D4 is set to the reference signal Bn-
1 and output as a binary signal sequence An, An-1, An-2
Are all "positive", D1 is used as the reference signal B
n2, and when the polarity of the sign of the binary signal An-1 is “positive” and the polarity of at least one of the signs of the binary signal An or the binary signal An-2 is “negative”, D2 is used as a reference. The binary signal An-1 is output as the signal Bn-1 and the sign of the binary signal An-1 is "negative" and the binary signal An or the binary signal A
When the polarity of at least one code of n-2 is "positive", D3 is output as a reference signal Bn-1, RLL (1, 7) modulation and NRZI modulation are performed, and the input / output signal recorded / reproduced. For X, the reference signal creation circuit creates an accurate reference signal Bn-1 from the continuous binary signal by following the state transition diagram, and allows the state transition that does not appear on the state transition diagram to be continuous. Three binary signals (2
It is possible to generate a reference signal from only the value signal sequence), and it is possible to realize an automatic equalizing circuit with fast response, good convergence, and good stability.

An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration example of an automatic equalization circuit according to an embodiment of the present invention. In FIG. 1, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, a transversal filter 101 includes delay units 311 to 314 and 315 and a multiplier 3
21 to 325, and an adder circuit 331.
L (1, 7) modulation and NRZI modulation, and a signal recorded and reproduced are used as input X, waveform equalization is performed to a characteristic close to PR (1, 2, 1) characteristic, and output Y (= Yn, Yn is time An output at nT, n is an arbitrary integer, and T is a sampling cycle) is output. The code detection circuit 102 receives the output Yn as an input,
The center value of the amplitude of the output Yn is set as a slice level (1.0), and a binary signal is output by outputting “1” if Yn ≧ 1.0 and “0” if Yn <1.0. A
Output n. Delay unit 116 delays output Yn by 1T and outputs signal Yn-1. The reference signal generation circuit 103 includes a binary signal An and a binary signal An-
The reference signal Bn is based on the binary signal An-2 one or two times earlier.
Create -1. The subtractor 104 subtracts the reference signal Bn-1 from the signal Yn-1 (Yn-1-Bn-1) and outputs an equalization error signal ERRn-1. Coefficient update circuit 105
Are equalized error signal ERRn-1 and inputs Xn + 1 to Xn-
3, the coefficient sequence K-2 to K + 2 used in the transversal filter 101 is updated so that the square error of the equalization error signal ERRn-1 is minimized.

The operation of the automatic equalizing circuit configured as described above will be described below. Input X is RLL
This is a signal recorded and reproduced by (1,7) modulation and NRZI modulation, and the output Yn is waveform-equalized by the transversal filter 101 to characteristics close to PR (1,2,1) characteristics. FIG. 2 shows the state transition of the output Yn, and FIG. 2 will be described below.

The output Yn has a constraint length of 3 due to the PR (1, 2, 1) characteristic, and has eight types of interference patterns due to intersymbol interference. The output Yn can take five values (0.0, 0.5, 1.0, 1.5, 2.0).
However, the value “1.0” cannot be obtained by performing the RLL (1, 7) modulation and the NRZI modulation. The states are S (1,0) to S (0,1) and S (0,1) to S (1,0) shown in FIG. The state transition diagram shown in FIG. 2 has two features, the first of which is “S (1,0)” described above.
To S (0,1) and S (0,1) to S (1,0). That is, the output Yn is (1.
0) cannot be taken. When the output Yn crosses the slice level (1.0), the transition always occurs from 0.5 to 1.5 or from 1.5 to 0.5,
Otherwise, the state is 0.0 or 2.0. "

Reference signal Bn in reference signal generation circuit 103
A method of creating -1 will be described. 2 in the state transition diagram shown in FIG.
Features and binary signal sequence (An, An-1, An-2)
Thus, a prototype of the reference signal creation procedure as shown in (Table 1) can be created.

[0016]

[Table 1]

However, in the reproduction of a signal recorded at high density, intersymbol interference is larger than before, and a margin for noise is reduced due to various noise mixing and waveform distortion. Further, this tendency increases when the tap coefficient sequences K-2 to K + 2 of the transversal filter 101 deviate from the optimum values, that is, before convergence. That is, the actual output Yn is not in an ideal signal state. As a result, the first feature of the state transition diagram shown in FIG. 2 described above does not hold, and at the same time, the values of the reference signals Bn-1 at * 1 and * 2 shown in (Table 1) are required. become. In order to compensate for such a state transition, a state transition that is impossible in the state transition diagram shown in FIG. 2 is permitted. That is, the first feature of the state transition diagram shown in FIG. 2 is abandoned, and the second feature of the state transition diagram shown in FIG.
"When the output Yn crosses the slice level (1.0),
Be sure to go from 0.5 to 1.5, or 1.5 to 0.
5 is applied to Bn-1 at the time of the binary signal string pattern of * 1 shown in (Table 1), and to Bn-1 at the time of the binary signal string pattern of * 2 shown in (Table 1). Apply 0.5. Thus, the reference signal creation procedure shown in Table 2 is created, and the reference signal creation circuit 103 outputs the reference signal Bn-1 based on the reference signal creation procedure.

[0018]

[Table 2]

The equalizer error ERRn-1 is calculated by the adder 104.
Is detected, and the coefficient update circuit 105 outputs the inputs Xn + 1 to Xn
Based on n-3 and the equalization error signal ERRn-1, the coefficient sequences K-2 to K + 2 used in the transversal filter 101 are updated so that the square error of the equalization error signal ERRn-1 is minimized. In this way, automatic waveform equalization is performed on the input X so as to approximate desired equalization characteristics, and the output Y is output.

Therefore, in the automatic equalization circuit according to the present embodiment, the code detection circuit 102 performs the operation of the reference signal generation circuit 103 on the output Yn equalized to a characteristic close to the PR (1, 2, 1) characteristic. Four reference values (0.0, 0.5, 1.5, 2,.
Part where the level difference between 0) is the largest (0.5 to 1.5)
And the reference signal creation circuit 103 creates an accurate reference signal Bn-1 according to the state transition diagram. Furthermore, by allowing state transitions that do not appear on the state transition diagram, three consecutive binary signals (An, An
−1, An−2), it is possible to generate the reference signal Bn−1, and it is possible to realize an automatic equalization circuit with fast response, good convergence and good stability. The erroneous state transition instantaneously disturbs the input of the coefficient updating circuit 105, but is smoothed by the integration (filter) effect of the coefficient updating circuit 105,
The effect is eliminated.

In the above embodiment, the four values of the reference signal Bn-1 of 0.0, 0.5, 1.5, 2.0
Is an example for explanation, and is of course not limited to this, and a relationship obtained by multiplying the above four values by an integer or a relationship obtained by adding or subtracting an integer (for example, -1.0, -0.5, 0.5, 1.
0) and all combinations of these two relationships. Also, the reference signal generation procedure of (Table 1) for generating the reference signal Bn-1 is an example for explanation,
Of course, the present invention is not limited to this. When the output Yn crosses the slice level (1.0), the output Yn must be 1.5 to 0.
5 or from 0.5 to 1.5, and in other states, 0.0 or 2.0. " Further, the least square method for updating the coefficients of the transversal filter is an example for explanation, and is not limited to this. Of course, the tap coefficient sequence of the transversal filter according to the equalization error signal ERRn-1 And a coefficient update circuit that adaptively and automatically equalizes the input waveform by updating the input signal. Further, the number of taps (the number of tap coefficients) constituting the transversal filter is an example for explanation, and is not limited to this.

[0022]

As described above, according to the present invention, the PR
For the output Yn equalized to a characteristic close to the (1, 2, 1) characteristic, the code detection circuit performs binary conversion using only the portion where the level difference between the four reference values of the reference signal generation circuit is the largest. And the reference signal creation circuit creates an accurate reference signal according to the state transition diagram. Furthermore, by permitting state transitions that do not appear on the state transition diagram, it is possible to generate a reference signal from only three consecutive binary signals, thereby achieving quick response, automatic convergence, and good stability. A circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic equalization circuit according to a first embodiment of the present invention.

FIG. 2 shows RLL (1, 7) encoding and PR (1, 2, 1)
State transition diagram when combining

FIG. 3 is a block diagram showing a conventional automatic equalization circuit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Transversal filter 102 Code detection circuit 103 Reference signal creation circuit 104 Adder 105 Coefficient update circuit 116, 311 to 315 Delay unit 321 to 325 Multiplier 331 Addition circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tatsuya Suzuki 1006 Kazuma Kadoma, Kadoma, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] An input X that has been subjected to RLL (1,7) modulation and NRZI modulation and recorded and reproduced is subjected to PR (1,2,2).
1) Output Y (= Yn, Y) whose waveform is equalized to a characteristic close to the characteristic
n is an output at time nT, n is an arbitrary integer, T is a sampling cycle), and a transversal filter that outputs a binary signal An to the output Yn and outputs a binary signal An A signal detection circuit for generating a reference signal Bn-1 based on the transition of the binary signal An; a delay unit for delaying the output Yn by 1T and outputting a signal Yn-1; Signal Yn-
1 is subtracted from the reference signal Bn-1 to obtain an equalization error signal E
A subtractor that outputs RRn-1 and the equalization error signal ER
A coefficient updating circuit for updating a tap coefficient of the transversal filter in accordance with Rn-1; wherein the reference signal creating circuit includes the binary signal An and a binary signal An 1T before the binary signal An. -1 and 2T of the binary signal An
An automatic equalization circuit for generating the reference signal Bn-1 according to a total of three binary signal sequences of the previous binary signal An-2. 2. The method according to claim 1, wherein the reference value generated by the reference signal generation circuit is four.
Values (D1, D2, D3, D4, D1>D2> in order of level)
D3> D4), and the binary signal strings An, An−1, An−
If all the signs of the sign 2 are “negative”, the D4 is output as the reference signal Bn−1, and the binary signal sequence An,
When the sign polarities of the An-1 and An-2 are all "positive", the D1 is output as the reference signal Bn-1, and the sign of the binary signal An-1 is "positive" and the 2 When the polarity of at least one sign of the value signal An or the binary signal An-2 is "negative", the D2 is output as the reference signal Bn-1, and the sign of the sign of the binary signal An-1 Is “negative” and the binary signal An or the 2
The polarity of at least one sign of the value signal An-2 is “positive”
2. The automatic equalization circuit according to claim 1, wherein in the case of (1), said D3 is output as said reference signal Bn-1.