JPH11111969A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a leakage current flowing between a drain and a source in the state in which a voltage is not applied to an insulation gate. SOLUTION: An epitaxial layer 2 is formed on a semiconductor substrate 1, and a (p)-type well area 3 is formed inside the epitaxial layer 2. An n<+> -type drain region 4 and an n<+> -type source region 5 are formed away from each other inside the (p)-type well region 3, and the insulation gate 7 is formed through a gate oxidized film 6 on the (p)-type well region 3 interposed between the n<+> -type drain area 4 and the n<+> -type source region 5. Also, a LOCOS oxidized film 10 is formed inside the (p)-type well region 3 so as to be exposed to the surface of the (p)-type well region 3 interposed between adjacent nMOS transistors and a p<+> -type impurity region 11, as a channel stopper for parasitic nMOS is formed inside the (p)-type well region 3 at the lower part of the LO COS oxidized film 10. Also, an (n)-type impurity region 12 is formed between the n<+> -type drain region 4 and the (p)-type impurity region 11. In this case, the p<+> -type impurity region 11 is formed in contact with the n<+> -type source region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a high withstand voltage nMOS transistor.

[0002]

2. Description of the Related Art FIGS. 5A and 5B are schematic diagrams showing an nMOS transistor according to a conventional example. FIG. 5A is a schematic cross-sectional view showing the shape of a mask for forming an nMOS transistor. In the conventional nMOS transistor, an n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1, and a p-type well region 3 is formed in the epitaxial layer 2 so as to be exposed on the surface.

In the p-type well region 3, an n + type drain region 4 and an n + type
And n + -type source region 5 are formed separately from each other, and ap interposed between n + -type drain region 4 and n + -type source region 5.
On the mold well region 3, an insulating gate 7 made of polysilicon or the like is formed via a gate oxide film 6 having a small thickness.

Then, a gate electrode (not shown) made of aluminum (Al) or the like is formed so as to be electrically connected to the insulating gate 7, and the n + type drain region 4 and n
A drain electrode 8 and a source electrode 9 made of aluminum (Al) or the like are formed so as to be electrically connected to the + type source region 5, respectively, to constitute an nMOS transistor.

A LOCOS oxide film 10 is formed in p-type well region 3 so as to be exposed on the surface of p-type well region 3 interposed between adjacent nMOS transistors, and a p-type well below LOCOS oxide film 10 is formed. In the region 3, a p + type impurity region 11 is formed as a channel stopper for a parasitic nMOS.

In the case of a complementary transistor, a pMOS transistor is also formed on the same chip. The pMOS transistor also forms a parasitic pMOS channel stopper as in the case of the nMOS transistor. At this time, between the n + -type source region 5 and the p + -type impurity region 11 and between the n + -type drain region 4 and the p + -type impurity region 11 of the nMOS transistor.
An n-type impurity region 12 is formed between the two.

Hereinafter, a manufacturing process of an nMOS transistor according to a conventional example will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view showing a first stage of a manufacturing process of an NMOS transistor according to a conventional example, FIG. 7 is a schematic cross-sectional view showing a middle stage of a manufacturing process of an NMOS transistor according to a conventional example, and FIG. FIG. 14 is a schematic cross-sectional view showing a latter stage of a manufacturing process of an NMOS transistor according to a conventional example. First, an n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1, and a field oxide film 13 is formed on the epitaxial layer 2 by thermal oxidation or the like. And
The field oxide film 13 is patterned into a predetermined shape using a photolithography technique and an etching technique to form an opening 13a in the field oxide film 13 (FIG. 6).
(A)).

Subsequently, a p-type impurity such as boron (B) is ion-implanted into the epitaxial layer 2 using the field oxide film 13 in which the opening 13a is formed as a mask, and the p-type well region 3 is formed by an oxidation and drive process. Form (Fig. 6
(B)). Note that a thermal oxide film is formed in the opening 13a by this oxidation step.

Next, the field oxide film 13 is patterned into a predetermined shape using a photolithography technique and an etching technique.
Is formed, and a p-type impurity such as boron (B) is ion-implanted into the p-type well region 3 using the field oxide film 13 in which the opening 13b is formed as a mask (PB mask) (FIG. 6).
(C)). The region into which the p-type impurity has been ion-implanted forms ap + -type impurity region 11 as a channel stopper for a parasitic nMOS in a subsequent thermal process.

Next, the field oxide film 13 formed on the epitaxial layer 2 is completely removed by etching, and a thin thermal oxide film 14 is formed by thermal oxidation or the like. Thereafter, a silicon nitride film 15 is formed on the thermal oxide film 14 by a CVD method (FIG. 6D).

Next, the silicon nitride film 15 is etched by using the photoresist 16 patterned into a predetermined shape as a mask so that the silicon nitride film 15 is left at a position where an nMOS transistor and a pMOS transistor are to be formed later. An opening 15a is formed in the hole 15. Then, using the silicon nitride film 15 having the opening 15a formed therein and the photoresist 16 as a mask (OD mask), an n-type impurity region 12 such as phosphorus (P) is formed to form the n-type impurity region 12 as a channel stopper for a parasitic pMOS. Impurities are ion-implanted (FIG. 7A), and the photoresist 16 is removed by plasma ashing or the like.

The dose of the n-type impurity to be implanted at this time is determined by p + as a channel stopper for the parasitic nMOS.
Since the dose of the p-type impurity implanted for the formation of the p-type impurity region 11 is about two orders of magnitude smaller, the effect of the n-type impurity implantation can be ignored in the region where the p-type impurity is implanted.

Next, using the silicon nitride film 15 in which the opening 15a is formed as a mask, a LOCOS (Localized Oxi
LOCOS oxide film 1 by performing dation of Silicon)
0 is formed, and the silicon nitride film 15 is removed by etching using phosphoric acid or the like. In this step, the p + -type impurity region 11 serving as a parasitic nMOS channel stopper is formed by the p-type impurity previously implanted into the p-type well region 3, and the parasitic pMOS channel is formed by the n-type impurity implanted into the p-type well region 3. An n-type impurity region 12 as a stopper is formed. Then, the thermal oxide film 1 remaining in the transistor formation region
4 is removed by etching using hydrofluoric acid or the like, and then thermal oxidation is performed to form a thin gate oxide film 6 (FIG. 7B).

Next, a polysilicon layer is formed by a CVD method, and the polysilicon layer is selectively etched by using a photoresist (not shown) patterned in a predetermined shape as a mask (PS mask). Is formed, and the photoresist is removed (FIG. 7C).

Next, ions of a p-type impurity such as boron (B) for forming a drain region and a source region of the pMOS transistor are implanted. At this time, since the nMOS transistor formation region is covered with the front resist, no p-type impurity is implanted.

Next, using the photoresist 17 and insulating gate 7 patterned in a predetermined shape as a mask, nMO
An n-type impurity such as phosphorus (P) is ion-implanted for forming the n + -type drain region 4 and the n + -type source region 5 of the S transistor (FIG. 7D), and the photoresist 17 is removed. At this time, since the pMOS transistor formation region is covered with the resist, no n-type impurity is implanted. Then, by the driving process, n +
A drain region 4 and an n + -type source region 5 are formed, and a drain region and a source region (not shown) of the pMOS transistor are formed.

Next, an interlayer insulating film 18 is formed by a CVD method (FIG. 8A), and a contact hole 19 is formed by selectively etching the interlayer insulating film 18 using a photolithography technique and an etching technique. (FIG. 8B).

Next, an aluminum (Al) layer is formed so as to fill the contact hole 19 by sputtering, and the aluminum layer is selectively etched using a photolithography technique and an etching technique. A drain electrode 8, a source electrode 9, and a gate electrode (not shown) electrically connected to the n + type source region 5 and the insulated gate 7, respectively, are formed (FIG. 8C).

Finally, CVD is performed on the entire surface side on which the electrodes are formed.
A passivation film 20 is formed by a method (FIG. 8)
(D)).

In the nMOS transistor, by applying a positive voltage to the insulated gate 7, a channel is created immediately below the insulated gate 7, and a current flows between the drain and the source through the channel. If the insulated gate 7 is set to 0 potential, a channel cannot be formed, so that no current flows between the drain and the source. This is a device that controls the current flowing between the drain and the source by the potential applied to the insulating gate 7.

[0021]

However, in the above-mentioned nMOS transistor, the n + -type drain region 4 and the n + -type drain region 4 are formed by the n-type impurity implanted to form the n-type impurity region 12 as the channel stopper for the parasitic pMOS. Since the n-type impurity region 12 is formed between the p + -type impurity region 11 and the n + -type source region 5 and the p + -type impurity region 11 as an nMOS channel stopper, the n-type impurity region 12 (current path I).

The present invention has been made in view of the above points, and has as its object to suppress a leak current flowing between a drain and a source when no voltage is applied to an insulated gate. To provide a semiconductor device capable of performing such operations.

[0023]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the semiconductor substrate, and a first conductivity type well formed in the epitaxial layer so as to be exposed on the surface of the epitaxial layer A high-concentration second-conductivity-type drain region and a high-concentration second-conductivity-type source region and a high-concentration second-conductivity-type source region, which are included in the region and the well region, and are exposed to the surface of the epitaxial layer and formed separately from each other. An nMOS transistor having an insulated gate formed on the well region via a gate oxide film interposed between the source region and an nMOS transistor; and an LO formed on the surface of the epitaxial layer between the adjacent nMOS transistors.
In a semiconductor device having a COS oxide film and a high concentration first conductivity type impurity region formed in the epitaxial layer below the LOCOS oxide film, the high concentration first conductivity type impurity region is formed in the source region. Are arranged so as to contact with.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, there is provided a semiconductor device according to the first aspect of the present invention, wherein the well region under the LOCOS oxide film between the drain region and the high concentration first conductivity type impurity region is It is characterized in that a two-conductivity type impurity region is provided.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating an nMOS transistor according to an embodiment of the present invention.
(A) shows the shape of a mask when an nMOS transistor is formed, and (b) is a schematic sectional view. In the nMOS transistor according to the present embodiment, a p + type impurity region 11 as a channel stopper for a parasitic nMOS is formed so as to be in contact with the n + type source region 5 in the nMOS transistor shown in FIG. The configuration is such that an n-type impurity region 12 interposed between the n-type impurity region 11 and the n + -type source region 5 is removed.

That is, by forming the p + -type impurity region 11 as a channel stopper for the parasitic nMOS in contact with the n + -type source region 5, the path of the leak current between the drain and the source can be eliminated.

The breakdown voltage between the drain and the source is n +
Since the distance between the n + -type drain region 4 and the p + -type impurity region 11 is determined by the distance between the n + -type drain region 4 and the p + -type impurity region 11,
The drain-source breakdown voltage can be maintained.

Further, n for forming the n-type impurity region 12 is
Since it is not necessary to reduce the dose of the ion implantation of the type impurity, the parasitic pMOS can also be maintained in the OFF state.

Hereinafter, the manufacturing process of the nMOS transistor according to this embodiment will be described with reference to the drawings. FIG.
FIG. 3 is a schematic cross-sectional view showing a first stage of a manufacturing process of the nMOS transistor according to the present embodiment, FIG. 3 is a schematic cross-sectional view showing a middle stage of the manufacturing process of the nMOS transistor according to the present embodiment, and FIG. FIG. 10 is a schematic cross-sectional view showing a latter stage of a manufacturing process of the nMOS transistor according to the embodiment. Since the manufacturing process of the nMOS transistor according to the present embodiment is substantially the same as the manufacturing process of the nMOS transistor shown in FIGS. 6 to 8 as a conventional example, only different processes will be described. In FIG. 2C, a p-type impurity for forming a p + -type impurity region 11 as a channel stopper for a parasitic nMOS is ion-implanted in contact with an n + -type source region 5 to be formed later. That is, the opening 13b near the n + type source region 5 formation region is formed in contact with the transistor formation region.

Then, in FIG. 3A, the parasitic pMOS
Implantation of an n-type impurity for forming the n-type impurity region 12 as a channel stopper is performed around the transistor formation region. Therefore, in the region that is in contact with the n + -type source region 5, high-concentration p-type impurities are ion-implanted so as to be in contact with the transistor formation region in the previous step. It becomes p-type.

Since the dose of the p-type impurity for forming the p + -type impurity region 11 is about two orders of magnitude higher than the dose of the n-type impurity for forming the n-type impurity region 12,
The n-type impurity at the location where the p-type impurity is implanted can be ignored.

Thus, p + -type impurity region 11 is formed so as to be in contact with n + -type source region 5.

[0033]

According to the first aspect of the present invention, there is provided a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the semiconductor substrate, and an epitaxial layer formed on the epitaxial layer so as to be exposed on the surface of the epitaxial layer. A high-concentration second-conductivity-type drain region and a high-concentration second-conductivity-type drain region formed in the well region and the well region of the first conductivity type, and exposed to the surface of the epitaxial layer and formed apart from each other. An nMOS transistor having an insulated gate formed via a gate oxide film on a well region interposed between a source region, a drain region, and a source region;
Formed on the surface of the epitaxial layer between the transistors
In a semiconductor device having a LOCOS oxide film and a high-concentration first-conductivity-type impurity region formed in an epitaxial layer below the LOCOS oxide film, the high-concentration first-conductivity-type impurity region may be in contact with a source region. The arrangement provided a semiconductor device capable of suppressing a current flowing between the drain and the source when no voltage was applied to the insulated gate.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a second conductive type is provided in the well region below the LOCOS oxide film between the drain region and the high-concentration first conductive type impurity region. Since the impurity region is provided, it is possible to prevent a decrease in withstand voltage between the drain and the source.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an nMOS transistor according to an embodiment of the present invention, wherein (a) shows a shape of a mask when an nMOS transistor is formed, and (b) is a schematic sectional view.

FIG. 2 is a schematic cross-sectional view showing a first stage of a manufacturing process of the nMOS transistor according to the embodiment.

FIG. 3 is a schematic cross-sectional view showing a middle stage of a manufacturing process of the nMOS transistor according to the embodiment.

FIG. 4 is a schematic cross-sectional view showing a latter stage of a manufacturing process of the nMOS transistor according to the embodiment.

5A and 5B are schematic configuration diagrams showing an nMOS transistor according to a conventional example, in which FIG. 5A shows a shape of a mask when an nMOS transistor is formed, and FIG. 5B is a schematic sectional view.

FIG. 6 is a schematic cross-sectional view showing a first stage of a manufacturing process of an nMOS transistor according to a conventional example.

FIG. 7 is a schematic cross-sectional view showing a middle stage of a manufacturing process of an nMOS transistor according to a conventional example.

FIG. 8 is a schematic cross-sectional view showing a latter stage of a manufacturing process of an nMOS transistor according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 epitaxial layer 3 p-type well region 4 n + type drain region 5 n + type source region 6 gate oxide film 7 insulated gate 8 drain electrode 9 source electrode 10 LOCOS oxide film 11 p + type impurity region 12 n type impurity region 13 field Oxide film 13a, 13b Opening 14 Thermal oxide film 15 Silicon nitride film 15a Opening 16, 17 Photoresist 18 Interlayer insulating film 19 Contact hole 20 Passivation film

Claims (2)

[Claims] A first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the semiconductor substrate, and a second conductivity type epitaxial layer formed in the epitaxial layer so as to be exposed on a surface of the epitaxial layer. A well region of one conductivity type, a high-concentration second conductivity-type drain region and a high-concentration second conductivity type source region which are included in the well region, and are formed on the surface of the epitaxial layer and separated from each other. An nMOS transistor having an insulated gate formed via a gate oxide film on the well region interposed between the drain region and the source region; and an nMOS transistor formed on a surface of the epitaxial layer between adjacent nMOS transistors. Having a LOCOS oxide film formed therein and a high-concentration first-conductivity-type impurity region formed in the epitaxial layer below the LOCOS oxide film. In the device, the semiconductor device being characterized in that arranging the high concentration first conductivity type impurity region in contact with the source region. 2. A second conductivity type impurity region is provided in the well region below the LOCOS oxide film between the drain region and the high concentration first conductivity type impurity region. 2. The semiconductor device according to 1.