JPH10269189A - Device and method for verifying program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for program development. SOLUTION: The number (i) of processor blocks 7-i used for verification is successively set from '1' to the processor block number PBMax of an actual equipment for processing the program. Then, by changing (j) from '1' to (PBMax-i+1) for the respective processor block numbers (i), the verification using the (i) pieces of the sensor blocks 7-j-7-(j+i-1) from the number (j) to the number (j+i-1) is performed in (PBMax-i+1) ways. In the case that an excellent result can not be obtained by the respective verifications, debugging is appropriately performed. Then, finally, the verification using the PBMax pieces of the processor blocks 7-1-7-PBMax is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for verifying a program, and more particularly, to a method and apparatus for verifying a program processed by an information processing apparatus having a plurality of processor blocks.
The present invention relates to a program verification device and method for verifying using a processing unit having a predetermined number of processor blocks.

[0002]

2. Description of the Related Art With recent advances in semiconductor technology, images have been treated as electrical data.
In signal processing for such image data, 1
In many cases, the same arithmetic processing is performed on all pixels constituting a sheet of image. In that case, a SIM developed to execute the same arithmetic processing at high speed for many data
A D (Single Instruction Multiple Data-stream) processing device may be used.
In the SIMD type processing device, a required number of arithmetic devices are arranged, and each arithmetic device operates according to the same instruction. Therefore, when separate data is given to each processing device, a calculation result for each data can be obtained by one calculation.

[0003] As an example of applying image processing of a SIMD type processing apparatus, for example, "Kurokawa et al.," 5.4 GOPS L
inear Array Architecture DSP for Video-Format Conv
ersion ", IEEE 1969 / Feb. ISCC, FP 15.7." FIG. 7 shows such a SIM
2 shows a configuration example of a D-type image processing apparatus.

As shown in FIG. 7, a SIMD type image processing apparatus comprises a signal control unit 64, an input SAM (Serial Access Me
mory) unit 61, processor blocks 62-1, 61-
2 and an output SAM unit 63. The processor blocks 62-1 and 62-2 include a data memory unit 71-1 and 71-2, an ALU array unit 72-1 and 72-
2 and program control units 73-1 and 73-2.

[0005] The signal control section 64 supplies an instruction code corresponding to an application program to each of the processor blocks 62-1 and 62-2, and also receives an input SA.
The input / output timing of data by the M unit 61 and the output SAM unit 63 is controlled. Input SA
The M section 61 is composed of a plurality of columns, and inputs 1-bit information from each column (square hatched in FIG. 7) to the data memory section 71-1.

The data memory section 71-1 of the processor block 62-1 temporarily stores the data supplied from the input SAM section 61, and, if necessary, stores the data in the ALU array section 7.
2-1.

The ALU array section 72-1 reads data from the data memory section 71-1 and stores the data in the program control section 7-1.
A predetermined calculation process is executed in response to a command from 3-1 and the calculation result is output to the data memory unit 71-2 of the next processor block 62-2.

[0008] The processor block 62-2 has the same configuration as the processor block 62-1 and will not be described.

The output SAM unit 63 sequentially outputs data output from the ALU array unit 72-2 of the processor block 62-2 as output data Dout.

The input SAM unit 61, data memory units 71-1 and 71-2, and ALU array units 72-1 and 72-
2, and the output SAM unit 63 constitute a group of element processors parallelized in a linear array (linear array) type. Each part of these element processors is controlled by the program control unit 73-1 or 73-2 of the processor block including the part. In the SIMD-type image processing apparatus, as described above, by configuring the processor blocks in multiple stages, it is possible to improve the processing capability almost in proportion to the number of stages.

Further, in each processor block of the SIMD type image processing apparatus shown in FIG. 7, SIMD type processing is executed, but different processing can be executed for each processor block. Is
MIMD (Multiple) that processes multiple programs in parallel
Instruction Multiple Data Stream (multiple instruction multiple data) type processing is executed.

General-purpose processor (CPU: Central Proc)
essing Unit), a predetermined number of bits (for example,
The arithmetic processing is performed on the data of (64 bits). In the device shown in FIG.
1, 72-2, the data is operated one bit at a time.
That is, in FIG. 7, the input SAM unit 61, the data memory unit 7,
1-1, 71-2, the output SAM unit 63 constitutes a column of a memory, and the ALU array units 72-1 and 72-2 have 1-bit ALUs (Arithmetic and Logical Units). (Full adder).

[0013] Such an element processor, which is a processing processor in units of one bit, is realized by a small-scale circuit, so that a large number of element processors can be configured (formed) on a semiconductor substrate. Therefore, in a parallel processor for image processing, the parallel number of element processors (the number N of element processors in FIG. 7) is often set to be equal to the number of pixels (H) of one horizontal scanning period of an image signal.

Next, the operation of the SIMD type image processing apparatus shown in FIG. 7 will be described.

The input SAM section 61 receives N (= H) signals corresponding to one horizontal scanning line during the horizontal scanning active period of the image signal.
After inputting and storing the image data, the image data is transferred to the data memory unit 71-1 of the processor block 62-1 during the horizontal scanning unit blanking period of the image signal.

The data memory unit 71-1 temporarily stores the image data supplied from the input SAM unit 61, and stores the stored image data in the ALU array unit 72-
1 and stores data in the middle of the operation output from the ALU array unit 72-1. And
The ALU array section 72-1 performs program control on the data supplied from the data memory section 71-1.
A process (for example, an addition process) according to the instruction supplied from 1 is performed and output to the data memory unit 71-1 or the processor block 62-2.

The data memory section 71-2 temporarily stores the processed image data supplied from the processor block 62-1 and stores the stored image data in the ALU array section 72-2 as necessary. The data is supplied and the data output from the ALU array unit 72-2 during the course of the operation is stored. Then, the ALU array unit 72-2 performs a process according to the instruction supplied from the program control unit 73-2 on the data supplied from the data memory unit 71-2, and Output to the output SAM unit 63.

The output SAM unit 63 outputs image data for one horizontal scanning line obtained as a result of the processing when the image signal is in a horizontal scanning active period.

When such processing is executed, all the element processors in each processor block operate in parallel according to the same instruction.

FIG. 8 shows an example of a configuration of a program verifying apparatus for verifying a program for the parallel processor shown in FIG. 7, for example.

The control unit 101 reads a program to be verified and data to be processed at the time of verification from the recording medium 102, supplies the program to the signal control unit 5, supplies the data to the input SAM unit 6, A signal corresponding to the operation is supplied to the signal control unit 5 in response to a user operation on the operation unit 3.

The signal control unit 5 supplies an instruction corresponding to the program supplied from the control unit 101 to the input SAM unit 6, each processor block 107-i, and the output SAM unit 8.

The processor block 107-1 receives the input S
The data supplied from the AM unit 6 is processed by the signal control unit 5
The operation is performed according to the supplied instruction, and the operation result is output to the output data observing device 9 while being output to the processor block 107-2 of the next stage.

Processor blocks 107-2 to 107
-(M-1) performs an operation on the data supplied from the preceding processor block in accordance with the instruction supplied from the signal control unit 5, outputs the operation result to the next processor block, and outputs data Output to the observation device 9.

The processor block 107-M performs an operation on the data supplied from the preceding processor block 107- (M-1) in accordance with the instruction supplied from the signal control unit 5, and outputs the operation result to the output SAM unit. 8 and to the output data observation device 9.

The output SAM unit 8 sequentially outputs the data supplied from the last processor block 107-M to the output data observation device 9.

The output data observation device 9 converts the data (intermediate data) calculated by the processor blocks 107-1 to 107-M and the calculation result supplied from the output SAM unit 8 into, for example, display data. Then, an image corresponding to the display data is displayed on a predetermined display unit.

FIG. 9 shows the processor block 107 of FIG.
1 shows configuration examples of -1 to 107-M.

The input data transfer circuit 21 supplies data supplied from the preceding processor block to the data memory unit 31 of the parallel processor simulation unit 22. The input data transfer circuit 21 of the first processor block 107-1 supplies the data supplied from the input SAM unit 6 to the data memory unit 31.

The parallel processor simulation unit 22
Is composed of a data memory unit 31 and an ALU array unit 32, performs a process corresponding to an instruction supplied from the program control unit 41, and outputs a result of the process to the output data transfer circuit 23.

The output data transfer circuit 23 outputs the result of the processing to the next processor block and to the output data observation device 9. The output data transfer circuit 23 of the last processor block 107-M outputs the processing result to the output SAM unit 8 and the output data observation device 9.

FIG. 10 shows an example of a processing flow when a program for such a parallel processor is developed.

First, in step S41, the control unit 1
01 reads predetermined data from the recording medium 102,
The program is supplied to the input SAM unit 6, a program to be verified is read in step S 42, and supplied to the signal control unit 5.
Then, in step S43, the signal control unit 5 supplies an instruction to the program control unit 41 of each processor block, controls the data memory unit 31 and the ALU array unit 32 of each processor block according to the program, and performs data processing. Then, the processing result is output to the output data observation device 9 via the output SAM unit 8.

At this time, the user refers to the processing result displayed on the output data observing device 9 and determines whether or not the result is good in step S44. If determined, step S4
In step 5, after debugging the program, the process returns to step S42, and the changed program is input.
The verification is performed again.

In this way, the program is developed while the verification is repeated until the program operates properly.

[0036]

By the way, when developing a parallel processor program, it is necessary to verify the program in detail, so that it is necessary to observe detailed information such as the value of the data memory section of each element processor. is there. Therefore, a program is often developed using a device having a mechanism for observing such detailed information while faithfully simulating a target parallel processor.

However, due to the fact that the parallel processor shown in FIG. 7 is composed of a large number of processor blocks having hundreds to thousands of element processors,
Software that runs on a single processor (general-purpose processor). When simulating a parallel processor, it takes thousands to tens of thousands of times as long as a real machine, and debugging is repeated many times during program development. There is a problem that a long time is wasted for work.

The present invention has been made in view of such a situation, and a program is developed by verifying a program using a part or all of a predetermined number of processor blocks. To reduce the time required.

[0039]

According to a first aspect of the present invention, there is provided a program verifying apparatus comprising: a processing unit having a first number of processor blocks;
It is characterized by comprising a selecting means for selecting a second number of processor blocks to be used for verification, a supplying means for supplying an instruction code corresponding to a program to the processing means, and an output means for outputting a result of the verification. .

[0040] The program verifying method according to claim 8 is characterized in that:
Selecting a second number of processor blocks from the first number of processor blocks for use in verification;
The method includes a step of processing an instruction code corresponding to a program by a second number of processor blocks and a step of outputting a verification result.

In the program verifying apparatus according to the first aspect, the selecting means selects a second number of processor blocks used for verification from the first number of processor blocks of the processing means, and the supply means And supplying an instruction code corresponding to the program to the processing means,
A second number of processor blocks among the number of processor blocks execute the processing and perform verification, and the output unit includes:
Output the result of verification.

In the program verifying method according to the present invention, a second number of processor blocks to be used for verification are selected from the first number of processor blocks, and an instruction code corresponding to the program is stored in the second number. It processes in a number of processor blocks and outputs the result of verification.

[0043]

FIG. 1 shows an example of the configuration of an embodiment of a program verification device according to the present invention. In this program verification device, the control unit 1 (selection unit, change unit, input unit) reads out a program to be verified and data to be processed at the time of verification from the recording medium 2 and transmits the program to the signal control unit 5. (Supply means) to supply data to the input SAM unit 6, and to supply a signal corresponding to the operation to the signal control unit 5 in response to a user operation on the operation unit 3. . Further, the control unit 1 outputs a signal corresponding to the number of the processor block used at the time of verification to the processor block selection circuit 4.

The processor block selection circuit 4 has an M for designating the operation states of the processor blocks 7-1 to 7-M.
Has a list-structured buffer for storing a number of flags, and outputs a signal corresponding to the value of the flag to the processor block 7.
-1 to 7-M.

M-stage processor blocks 7-1 to 7-
The processor block 7-1 of M (processing means)
Only when a predetermined signal is supplied from the processor block selection circuit 4, an operation is performed on the data supplied from the input SAM unit 6 in accordance with the instruction supplied from the signal control unit 5, and the operation result is transmitted to the next processor. Output to block 7-2 and output data observation device 9 (output means)
Output.

The processor blocks 7-2 to 7- (M-
1) Only when a predetermined signal is supplied from the processor block selection circuit 4, the data supplied from the preceding processor block is operated according to the instruction supplied from the signal control unit 5, and the operation result is calculated. Output to the next processor block and output data observation device 9
Output.

Only when a predetermined signal is supplied from the processor block selection circuit 4, the processor block 7-M receives the signal supplied from the preceding processor block 7- (M-1), The operation is performed in accordance with the supplied instruction, and the operation result is output to the output SAM unit 8 and the output data observation device 9.

The signal control unit 5, the input SAM unit 6, the output SAM unit 8, and the output data observation device 9
Therefore, the description is omitted.

FIG. 2 shows the processor blocks 7-1 to 7
13 illustrates a configuration example of −M.

Parallel processor simulation unit 22A
Has a data memory unit 31 and an ALU array unit 32,
When a predetermined signal is supplied from the processor block control circuit 33, an operation is performed on data from the input data transfer circuit 21 in accordance with an instruction supplied from the program control unit 41, and a predetermined signal is supplied from the processor block control circuit 33. When the signal is not supplied, the data from the input data transfer circuit 21 is output to the output data transfer circuit 23A as it is.

In the parallel processor simulation unit 22A, when performing an operation on data, only the number of element processors corresponding to the signal supplied from the element processor number control unit 42 of the signal control unit 5 is operated. Has been made.

The parallel processor simulation unit 22A may be configured as hardware such as a gate array, or may be realized as software in a general-purpose parallel processor.

The output data transfer circuit 23A outputs the data supplied from the parallel processor simulation section 22A to the next processor block and, when a predetermined signal is supplied from the processor block control circuit 33, outputs the data. The data is output to the output data observation device 9. The output data transfer circuit 23A of the last processor block 7-M outputs data to the output SAM unit 8 instead of the next processor block.

The processor block control circuit 33 controls the parallel processor simulation section 22A and the output data transfer circuit 23A according to the signal corresponding to the value of the flag supplied from the processor block selection circuit 4.

Next, a flow of processing when a program is developed using the program verification device of FIG. 1 will be described with reference to flowcharts of FIGS.

In step S 1, the control unit 1 reads input data stored in the recording medium 2 according to a user operation on the operation unit 3 and outputs the data to the input SAM unit 6.

Next, in step S2, the control unit 1
Recording medium 2 according to a user operation on operation unit 3
Is read out and stored in the signal control unit 5.

In step S3, the control unit 1 reads out a file in which the verification conditions are described, which is stored in the recording medium 2 according to the operation of the operation unit 3 by the user, and in step S4, the processor block 7 used for verification. -Set the number of i (initial number) i to 1.

Then, in step S5, the control unit 1
Is the first number j of the processor block used for verification.
Is set to 1.

In step S6, the controller 1 sets the flags PBenable [1] to PBenable corresponding to the operation states of the processor blocks 7-1 to 7-M.
The value of [M] is changed to a value OF corresponding to a state where the process is not executed.
Set to F. That is, the flags PBenable [1] to PBenable [M] are reset.

Then, steps S7 to S10
, The flag PBe corresponding to the processor block used in the current verification, corresponding to the values of i and j described above.
table [j] to PBenable [j + i-1]
Is set to the value ON corresponding to the state in which the process is executed.

First, in step S7, the controller 1 substitutes the value of j for the counter k, and in step S8, sets the value of the flag PBenable [k] to the value ON corresponding to the state in which the processing is performed.

Next, in step S9, the control unit 1
Determines whether or not the value of the counter k is (j + i-1). If it is determined that k is not equal to j + i-1, the value of the counter k is increased by 1 in step S10. Returning to step S8, the value of the next flag is set.

On the other hand, in step S9, k = j + i
If it is determined to be -1, that is, the flags PBenable [j] to PBenable [j +] corresponding to the i processor blocks 7-j to 7- (j + i-1).
When it is determined that the value ON corresponding to the state in which the process is executed is set in [i-1], the process proceeds to step S11.

In step S11, the control unit 1 sets the flags PBenable [1] to PBenable
The signal corresponding to [M] is sent to the processor block selection circuit 4
To supply.

In step S12, the control unit 1 sets the number N of element processors to be used for verification in accordance with the control information read in step S3, and outputs a signal corresponding to the number N to the signal control unit 5. Element processor number control unit 42
To supply.

Then, in step S13, the control section 1 supplies a predetermined signal to the processor block selection circuit 4 and the signal control section 5, and the i processor blocks 7-j to 7-j to 7 out of the M processor blocks. − (J + i−
1) is operated to verify the program.

At this time, the processing results of the processor blocks 7-j to 7- (j + i-1) are directly supplied to the output data observing device 9, respectively.
The processing result of (j + i−1), that is, the final processing result according to the program is supplied to the output data observation device 9 via the output SAM unit 8. The output data observation device 9
Images corresponding to the processing results are displayed on a predetermined display unit, for example.

Then, in step S14, it is determined whether or not the verification result is good. If it is determined that the verification result is good, step S16 is performed.
Proceed to.

When determining whether or not the verification result is satisfactory, the user makes a determination with reference to the display on the output data observation device 9 and operates the operation unit 3 in accordance with the determination. Alternatively, a predetermined reference value is stored in the control unit 1 in advance, and the reference value is compared with the verification result.

On the other hand, if it is determined that the verification result is not good, the program recorded on the recording medium 2 is changed by the user in step S15.
That is, the program is debugged. After the end of debugging, the process returns to step S13, and in response to a user operation on the operation unit 3, the control unit 1 reads the program after debugging from the recording medium 2, supplies the read program to the signal control unit 5, and updates the program. Let it. Then, step S1
At 3, the verification is performed again.

Then, in step S16, it is determined whether or not the number of used element processors is sufficient. If it is determined that the number of used element processors is sufficient, the process proceeds to step S18.

When it is determined whether or not the number of used element processors is sufficient, the user makes a determination with reference to the display on the output data observing device 9 and determines whether the operation unit 3
Or a predetermined reference value (for example, the number of element processors of a parallel processor as an actual machine) is stored in the control unit 1 in advance, and the reference value is compared with the verification result.

On the other hand, if it is determined that the number of used element processors is not a sufficient number, in step S17, the control unit 1 increases the number N of the element processors and sends a signal corresponding thereto to the signal control unit. After being supplied to the number-of-elements-controller 42, the process returns to step S13.
The verification is performed again.

Then, in step S18, the control unit 1 determines that the last processor block number (j + i-1) of the processor blocks 7-j to 7- (j + i-1) used for verification is It is determined whether the number is the same as the number PBMax of the last processor block among the processor blocks provided in a certain device,
If it is determined that (j + i-1) = PBMax is not satisfied,
In step S19, after increasing the value of the number j of the first processor block among the processor blocks used for verification by 1, the process returns to step S6, and in steps S7 to S11, the flag PBenab
After setting the value of le, verification is performed.

On the other hand, in step S18, (j + i
If it is determined that -1) = PBMax, the process proceeds to step S20, and the control unit 1 determines whether the number i of processor blocks used for verification is the same as the number PBMax of processor blocks provided in the device. If it is determined that i is not equal to PBMax, in step S21, the value of the number i of processor blocks used for verification is increased by one, and the process returns to step S5 to set the value of j to one. After resetting, verification is sequentially performed.

On the other hand, in step S20, i = PB
If it is determined to be Max, the process proceeds to step S22, and the output data observation device 9 outputs the final processing result.

For example, the number P of actual processor blocks
When BMax is 4, as shown in FIG. 5, i changes from 1 to 4, and j changes from 1 to (5-i). Then, when i is 1, as shown in FIG. 5A, when j is 1, only the first processor block PB [1] of the verification device performs processing, and j is 2. At this time, the second processor block PB
Only [2] performs the processing. Then, when j is 3,
Only the third processor block PB [3] performs processing, and when j is 4, only the fourth processor block PB [4] performs processing. After the four types of verification are performed, i is increased by one.

Next, when i is 2, as shown in FIG. 5B, when j is 1, PB [1] and PB [2]
Only performs processing, and when j is 2, PB [2] and PB [2]
Only B [3] performs the processing, and when j is 3, PB
Only [3] and PB [4] perform processing. Then, after three kinds of verifications are performed, i is incremented by one.

When i is 3, as shown in FIG. 5C, when j is 1, PB [1], PB
[2] and PB [3] perform the processing, and when j is 2, PB [2], PB [3] and PB [4]
Performs the processing. After two types of verification, i
Is increased by one.

Finally, when i is 4, as shown in FIG. 5D, when j is 1, all the processor blocks PB [1] to PB [4] are processed only once. I do.

As described above, the number i of processor blocks used for verification is sequentially increased, and verification is performed in (PBMax-i + 1) combinations with each processor block number i.

Next, as an example of program verification, verification of a program describing horizontal low-pass filter processing and gain control processing in an image processing parallel processor having two processor blocks shown in FIG. 7 will be described. This parallel processor has 1
NT having 720 pixel data for horizontal scanning period
Since processing is performed on image data of the SC system, 720
Built-in element processors.

For example, as shown in FIG. 6, each pixel value of the original image is represented by A _ij , and each pixel value of the image subjected to the low-pass filter processing and the gain control processing is represented by B _ij. pixel value B ₂₂ is expressed by the following equation. _{B 22 = (A 21/4} + A 22/4 + A 23/4) × 4/3

In the horizontal low-pass filter processing, a value of 1/4 of the value of a predetermined pixel, a value of 1/4 of a value of a pixel on the left of the pixel, and a value of a pixel on the left of the pixel are determined. The sum of 1/4 of the values is calculated. Then, in the gain control processing, the calculation result in the low-pass filter processing is multiplied by 4/3. Therefore, FIG.
In the processor block 62-1, a low-pass filter process in the horizontal direction is performed.
At -2, a gain control process is performed.

When verifying a program for performing such processing, first, in step S1 of FIG.
Reads the original image data of the NTSC system from the recording medium 2 and supplies it to the input SAM unit 6.

Next, in step S2, the control unit 1
Reads the program for the parallel processor corresponding to the above-described low-pass filter processing from the recording medium 2 and supplies the program to the program control unit 41 of the processor block 7-1 via the signal control unit 5 to support the above-described gain control processing. The program for the parallel processor is read from the recording medium 2, and the processor block 7-
2 program control unit 41.

When the parallel processor program is described in a language other than the machine language (for example, when the program is described in an assembly language corresponding to the parallel processor), the control unit 1 converts the parallel processor program into a machine language. After the translation into words, supply the translated program.

Then, in step S3, the control unit 1
Reads a file in which control information such as the number of element processors used for verification is recorded.

Next, in step S4, the control unit 1 sets the number i of the processor blocks used for verification to one, and in step S5, sets the head number j of the processor block used for verification to one. .

Then, in step S6, the control section 1 sets the flags PBenable [1] to PBen [1] to PBnn corresponding to the operation states of the processor blocks 7-1 to 7-M, respectively.
A value OFF corresponding to a state in which the process is not executed is set to Benable [M]. Thereafter, in step S7, the control unit 1 stores the value of j in the counter k (in this case, j =
1), and in step S8, the flag PBenable [1] corresponding to the processor block 62-1
Is set to a value ON corresponding to the state in which the processing is executed.

Next, in step S9, the control unit 1
Determines whether k = j + i−1. In this case, since k is 1 and (j + i-1) is 1, the process proceeds to step S11, and the signals corresponding to the flags PBenable [1] to PBenable [M] are supplied to the processor block selection circuit 4. In this case, PBena
The value of ble [1] is ON and PBenable
The values of [2] to PBenable [M] are OFF.

In step S12, the control unit 1 sets the number N of element processors used for verification to a value specified by the control information read in step S3.
A signal corresponding to the value is supplied to the element processor number control unit 42 of the signal control unit 5. In the early stages of validation,
Since a bug often exists in a program, the number N of element processors used for verification is set to a small number (for example, three) in advance and recorded in a file in which control information is recorded. To do. In this case, N is set to 3.

Next, in step S13, the control unit 1
Causes the program to perform a corresponding process. At this time,
The processor block selection circuit 4 supplies a predetermined signal only to the processor block 7-1 to operate only the processor block 7-1. Further, the element processor number control unit 3 sends a predetermined signal to the processor block 7-1.
The number of element processors used is 3
The processor block 7-1 is notified that the number is the number.

Therefore, in this case, the processor block 7
Only the three element processors in -1 perform the processing (low-pass filter processing).

The data processed by the three element processors in the processor block 7-1 is output to the output data observation device 9 via the processor block 7-2 and the output SAM unit 8. At this time,
The processor block 7-2 includes a processor block 7-
The data received from 1 is output to the output SAM unit 8 as it is.

The output data observation device 9 outputs the data and the output data transfer circuit 2 of the processor block 7-1.
Detailed information such as memory and register values from 3A
After conversion into a predetermined format (for example, a text format), it is displayed on a predetermined display unit.

Then, for example, by the user, step S
At 14, it is determined whether or not the verification result is good, and an operation corresponding to the determination is performed on the operation unit 3.

If it is determined that the verification result is not good, the control unit 1 stops the processing. Then, proceeding to step S15, the user debugs the program, and then records the debugged program on the recording medium 2. Then, the verification is performed again in response to the operation of the operation unit 3 by the user.

On the other hand, if it is determined that the verification result is good, the process proceeds to step S16.

Then, in step S16, it is determined whether the number N of used element processors is a sufficient number. At this time, the number of element processors of the parallel processor in FIG. 7 is compared with the number N of element processors used.

In this case, since the number of element processors of the parallel processor of FIG. 7 is 720 and the number N of element processors used is three, it is determined that the number is not a sufficient number. After the number of element processors used for verification is increased to, for example, 720, verification is performed again.

On the other hand, in step S16, the number of used element processors is sufficient (720 in this case).
If it is determined that the answer is YES, the process proceeds to step S18.

Then, in step S18, the control unit 1 determines the last processor block number (j + i-1) (in this case, j + i-1 = 1) of the processor blocks used for the verification by the actual device. It is determined whether or not the number is the same as the number PBMax (= 2) of the last processor block among the processor blocks provided in a certain device (FIG. 7).

In this case, it is determined that (j + i-1) = PBMax is not satisfied, and in step S19, the value of the number j of the first processor block among the processor blocks used for verification is increased from 1 to 2. Thereafter, the process returns to step S6, and in steps S7 to S11, after the value of the flag PBenable [1] is set to OFF and the value of the flag PBenable [2] is set to ON, the gain control process is performed in the processor block 7-2. Is verified only for the program that describes.

Also in this case, first, verification is performed by three element processors, and then the number of element processors used for verification is sequentially increased to 720.

After the verification is performed only in the processor block 7-2, in step S18, (j + i
-1) = PBMax (in this case, j = 2, i = 1, PB
Max = 2), the process proceeds to step S20, and the control unit 1 determines whether the number i of processor blocks used for verification is the same as the number PBMax of processor blocks provided in the device. to decide. In this case, since i = 1 and PBMax = 2, i = P
It is determined that it is not BMax, and in step S21, after the value of the number i of processor blocks used for verification is increased from 1 to 2, the process returns to step S5, and after the value of j is reset to 1 in step S5, Verification is performed by two processor blocks 7-1 and 7-2.

Also in this case, first, verification is performed by three element processors, and then the number of element processors used for verification is sequentially increased to 720.

Then, the two processor blocks 7-
After the verification is performed in steps 1 and 7-2, it is determined in step S20 that i = PBMax (in this case, i = PBMax).
(2, PBMax = 2), the process proceeds to step S22, and the output data observation device 9 outputs a final processing result.

As described above, first, only the program of the low-pass filter processing is verified, then, only the program of the gain control processing is verified, and finally,
The verification of the program of the low-pass filter processing and the verification of the program of the gain control processing are performed simultaneously.

Note that the present invention is not limited to the above embodiment, but can be applied to other verification devices.

[0112]

As described above, according to the program verifying device of the first aspect and the program verifying method of the eighth aspect, the second number used for verification among the first number of processor blocks is used. Select the processor block of
Since the instruction code corresponding to the program is processed by the second number of processor blocks and the result of the verification is output, debugging can be performed for each part of the program, and the time required for debugging is reduced, The time required for program development can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a program verification device of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a processor block in FIG. 1;

FIG. 3 is a flowchart illustrating a processing flow when a program is developed using the program verification device of FIG. 1;

FIG. 4 is a flowchart illustrating a processing flow when a program is developed using the program verification device of FIG. 1;

FIG. 5 is a diagram showing an example of the order of processor blocks used for verification.

FIG. 6 is a diagram illustrating an example of image processing.

FIG. 7 is a block diagram illustrating a configuration example of a parallel processor for image processing.

FIG. 8 is a block diagram illustrating a configuration example of a conventional program verification device.

FIG. 9 is a block diagram illustrating a configuration example of a processor block in FIG. 8;

FIG. 10 is a flowchart illustrating an example of a processing flow when a program for the parallel processor in FIG. 8 is developed.

[Explanation of symbols]

Reference Signs List 1 control unit, 2 recording medium, 3 operation unit, 4 processor block selection circuit, 5 signal control unit, 6
Input SAM unit, 7-1 to 7-M processor block, 8 output SAM unit, 9 output data observation device,
Reference Signs List 21 input data transfer circuit, 22A parallel processor simulation unit, 23A output data transfer circuit, 31 data memory unit, 32 ALU array unit, 41 program control unit, 42 element processor number control unit

Claims (8)

[Claims] 1. A program verification device for verifying a program processed by an information processing device having a plurality of processor blocks, wherein: a processing unit having a first number of processor blocks; Selecting means for selecting a second number of processor blocks to be used for verification, supplying means for supplying an instruction code corresponding to the program to the processing means, and output means for outputting the result of the verification. A program verification device characterized by the above-mentioned. 2. The program verifying apparatus according to claim 1, further comprising changing means for changing the second number in accordance with the number of processor blocks used in the previous verification. 3. The method according to claim 1, wherein the selecting unit selects the second number of processor blocks in which at least one of the second number of processor blocks used in the previous verification is changed to another processor block. The program verification device according to claim 1, wherein: 4. The program verification apparatus according to claim 1, further comprising an input unit that inputs a program changed according to a result of the verification to the supply unit. 5. The program verification device according to claim 1, wherein the information processing device is a SIMD type parallel processor. 6. The program verification apparatus according to claim 1, wherein the processing unit has an arithmetic unit that performs parallel processing in a SIMD type. 7. The processor block includes a predetermined number of element processors, and includes a second selection unit that selects an element processor to be used for verification from among the predetermined number of element processors. The program verification device according to claim 1, wherein 8. A program verification method for verifying a program processed by an information processing device having a plurality of processor blocks by using a processing unit having a first number of processor blocks, wherein the first number of processors is provided. Selecting, from the blocks, a second number of processor blocks to be used for verification; processing the instruction code corresponding to the program by the second number of processor blocks; outputting the result of the verification And a program verifying method.