JPH10240565A - Application program verification device, application program verification method and medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the verification efficiency of an application program for an image processing DSP(digital signal processor). SOLUTION: A chip mode selection part 302 sets the operation mode of an image processing DSP verification part 200 and a processor block selection part 320 selects a processor block to be the object of verification. An element processor number control part 335 decides an element processor to be the object of the verification. A machine language program supply part 325 supplies a machine language program to the processor block to be the object of the verification. The image processing DSP verification part 200 executes a processing corresponding to an instruction code described in the machine language program to image data supplied from an input data 1 supply part 311-1 or an input data 2 supply part 311-2 and outputs an obtained result to an output data obtaining part 313. Also, the value of a register and a memory inside the image processing DSP verification part 200 is supplied to a verified result obtaining part 360. The data of a verified result are displayed and outputted to an image display part 317, a signal waveform display part 352 and a text information display part 351.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application program verification device, an application program verification method, and a medium, and more particularly, to an application program verification device and application program for verifying an application program for controlling a data processing semiconductor device. The present invention relates to a verification method and a medium.

[0002]

2. Description of the Related Art For example, when data processing is performed on image data, arithmetic processing is performed using each of the pixels constituting the image as a basic unit, but the individual arithmetic processing is the same processing. Often. As described above, as a method of executing the same arithmetic processing on a large amount of data at high speed, SIMD (Single Instruction Multiple Data Str
An eam (single instruction multiple data) type architecture has been proposed, and is used not only in image processing but also in a wide range of fields.

In the SIMD type architecture, a required number of arithmetic units are arranged in parallel, and each arithmetic unit executes arithmetic processing according to the same instruction. Therefore, if different arithmetic data is given to each arithmetic unit to execute arithmetic processing, arithmetic processing for a plurality of data is executed at once.

As an example of application of a processing device using the SIMD type architecture to image processing, “Kurokawa et a
l., "5.4 GOPS Linear Array Architecture DSP for Vid
eo-Format Conversion ", IEEE 1969 / Feb. ISCC, FP 15.
7. "is known. FIG. 3 shows a configuration example of such a SIMD type image processing apparatus.

As shown in FIG. 3, a SIMD type image processing apparatus (hereinafter abbreviated as “image processing apparatus”) includes a signal control unit 30, an input SAM (Serial Access Memory) unit 31,
It comprises a processor block 32, a processor block 33, and an output SAM unit 39. The processor blocks 32 and 33 are configured by data memory program sections 32a and 33a, data memory sections 32b and 33b, and ALU array sections 32c and 33c, respectively.

[0006] The signal control unit 30 supplies an instruction code constituting an application program to each of the processor blocks 32 and 33, and an input SAM unit 31.
The output SAM unit 33 controls the data input / output timing. Input SAM unit 31
Is composed of a plurality of columns (rectangular hatched in FIG. 3), and each column inputs 1-bit information.

The data memory section 32b constituting the processor block 32 temporarily stores data supplied from the input SAM section 31, and transfers the data to the ALU array section 32c as necessary.

[0008] The ALU array section 32c reads data from the data memory section 32b, and reads the data from the program control section 32a.
In response to a command from the CPU, predetermined arithmetic processing is executed, and the obtained result is output to the data memory unit 33b of the processor block 33 in the next stage.

The program control unit 33a, the data memory unit 33b and the ALU array unit 33c have the same configuration as that of the program control unit 32a, the data memory unit 32b and the ALU array unit 32c, and a description thereof will be omitted.

The output SAM unit 39 is provided with an ALU array unit 33.
After temporarily storing the data output from c, the data is output as output data Dout.

The input SAM unit 31, the data memory units 32b and 33b, the ALU array units 32c and 33c, and the output SAM unit 39 as a whole are a number of element processors that are parallelized in a linear array type. These element processors are controlled by a program control unit 32a or a program control unit 33a in the same processor block. In such an image processing apparatus, by configuring the processor blocks in multiple stages, it is possible to improve the processing capacity in proportion to the number of stages.

In each processor block of the image processing apparatus shown in FIG. 3, SIMD type information processing is executed by a plurality of element processors, but a plurality of programs can be processed in parallel as a whole apparatus. MIMD
(Multiple Instruction Multiple Data Stream) type information processing is executed.

A general processor (CPU: Central Pr
Ocessing Unit), a predetermined number of bits (for example, 64
Bit) is the processing unit, and the arithmetic processing is executed.
In the example shown in FIG. 3, the processing unit is 1 bit.
That is, in FIG. 3, the input SAM unit 31, the data memory unit 3
2b and 33b and the output SAM unit 39 are columns of a memory, and the ALU array units 32c and 33c are 1
It is a bit ALU and has a configuration mainly based on a full adder (full adder). Therefore, if the word processor is to be referred to as an 8-bit machine or a 16-bit machine, which is an ordinary processor, the image processing apparatus shown in this example is a 1-bit machine. Since the size of each element processor, which is such a bit processor, is small, a large number of element processors can be formed (formed) on a semiconductor substrate. Therefore, in the processor for image processing, the parallel number of the element processors (the number N of the element processors in FIG. 3) is set to be equal to the number of pixels (H) of the video signal in one horizontal scanning period.

Next, the operation of the image processing apparatus shown in FIG. 3 will be described.

The input SAM unit 31 inputs and stores image data for one horizontal scanning line during the horizontal scanning active period of the image signal, and then stores the image data in the data memory unit 32b during the horizontal scanning unit blanking period of the image signal. Forward.

The data memory section 32b stores the input SAM section 3
1 to temporarily store the image data supplied thereto, supply the stored image data to the ALU array unit 32c as necessary, and store the data in the course of the operation output from the ALU array unit 32c. .

The ALU array section 32c performs predetermined processing (for example, addition processing) on the data supplied from the data memory section 32b under the control of the program control section 32a, and outputs the data to the data memory section 33b. .

The data memory unit 33b and the ALU array unit 33c correspond to the data memory unit 32b and the ALU
As in the case of the array unit 32c, arithmetic processing is performed under the control of the program control unit 33a, and the obtained data is output to the output SAM.
Output to the unit 39.

The output SAM section 39 outputs image data for one horizontal scanning line obtained as a result of the processing when the image signal is in a horizontal scanning active period.

When the above processing is being executed, each element processor operates in parallel (simultaneously according to the same instruction).

By the way, the image processing apparatus shown in FIG. 3 incorporates a mode switching circuit, so that a "multi-stage parallel processing mode" (FIG. 4A) and a "multi-element processor mode" (FIG. 4 (B)). In both operation modes, there is no difference in the total number of processor blocks. However, due to the difference in the configuration method of the processor blocks, double-type processing can be performed on data for one horizontal line in the “multi-stage parallel processing mode”. In the “multi-element processor mode”, processing of image data for two horizontal lines is performed by one.
It can be executed every time. Therefore, the "multi-stage parallel processing mode" can be used when performing more complicated image processing on a standard television signal such as NTSC or PAL. Also, "Multi-element processor mode"
Can be used when processing high-definition images such as high-definition television signals.

When developing an application program for an image processing apparatus characterized by performing parallel processing as described above, it is necessary to verify whether the application program operates normally. Examples of such methods include (1) a method using an image processing device configured as hardware, and (2) a method using an image processing device configured as software.

In the former method using a hardware configuration, (A) a method of performing verification using an actual image processing apparatus, and (B) an image processing apparatus that is composed of discrete components (such as a gate array) must be reconfigured. There is a method of using the result.

In the method (A) of performing verification using an actual image processing apparatus, verification can be performed at a normal processing speed (an original processing speed of the image processing apparatus). However, in this method, since the image processing apparatus itself is treated as a black box, for example, inside the image processing apparatus, for example,
Register values and data being calculated cannot be displayed.

In the method (B) of reconfiguring the image processing apparatus with discrete components, the image processing apparatus is usually composed of hundreds to thousands of element processors. It is very difficult to realize this because many components are required to configure all of them with discrete components. Even if such a circuit can be configured, control for controlling all individual components as desired or obtaining desired data (data during calculation or register values) is extremely difficult. It becomes complicated.

On the other hand, in the latter method using a software configuration, since the internal functions of the target image processing apparatus are simulated by software, it is possible to easily obtain data in the middle of calculation and the value of each register. it can.

FIG. 5 shows an example in which an apparatus for verifying an application program for an image processing DSP (Digital Signal Processor), which is a kind of image processing apparatus, is realized by a software configuration. In this example, each function of the software is shown as a block.

In FIG. 5, the image processing DSP verification unit 20
0 indicates the input unit 220, the processor unit 400, and the output unit 25
0, and simulates the operation of the target image processing DSP by software.

The interface unit 100 performs image processing D
An application program to be verified and image data to be processed are supplied to the SP verification unit 200 at a predetermined timing, and the processed image data is obtained at a predetermined timing. ing. Hereinafter, a detailed configuration of the interface unit 100 will be described.

In FIG. 6, a project name setting unit 10
Numeral 1 is used to input a name of a file for recording each setting information of the interface unit 100. If the file name input to the project name setting unit 101 has already been recorded on the data recording medium 301 described later, the setting contents of the file are to be changed.

The message display unit 103 is provided with an image processing DS
When the P verification unit 200 is operating, a predetermined message (for example, “currently being verified”) indicating that fact is displayed, and when it is necessary to call the user's attention, a predetermined message is displayed. (For example, “An error has occurred”) is displayed.

The input data setting section 111 is operated when setting image data to be processed. When this portion is operated, a predetermined window is displayed, and It is possible to input a file name or the like of the target image data.

The output data setting unit 113 performs image processing DS
The operation is performed when the file name or output destination of the image data processed by the P verification unit 200 is determined or changed. When this part is operated, it becomes possible to input the file name of the processing result data (the file name when recording the data on the data recording medium 301), and to output the processing result data to an image One of the display unit 317, the signal waveform display unit 352, and the text information display unit 351 can be selected.

The program name setting section 121 is adapted to input a file name of an application program to be verified. The program display unit 122
When a file name of an application program is received from the program setting unit 121, and a source program display request is made from a source program display selection unit 124 described later, the corresponding source program is displayed. When the display request of the object program is made from 125, the corresponding object program is displayed.

The program compiling section 123 instructs a compiler 323 described later to compile a source program. The source program display selection unit 124 selects to display the source program on the program display unit 122. The object file display selection section 125 selects to display the object program on the program display section 122. When one of the source program display selection unit 124 and the object file display selection unit 125 is selected, the other cannot be selected.

The control signal setting section 130 calls an interface for setting control signal information, and supplies the control signal information supplied from the interface to a signal control section 280 described later.

The memory grouping unit 131 performs image processing D
A specific register in the element processor to be verified by the SP verification unit 200 is grouped, and an interface for setting a display format of the grouped registers is called. Information set in this interface is transmitted to a verification result acquisition unit 3 described later.
60 and the information obtained from the output data acquisition unit 313 are reflected in the display format when the result display unit 153 displays the information.

The processing point display section 132 displays the number of cycles of the processor of the image processing DSP verification section 200 when the verification processing is executed.

The interruption point setting section 133 designates a point at which the verification process is interrupted by the number of cycles of the processor.

The termination condition setting section 134 designates the point at which the verification processing is terminated by the number of cycles of the processor.

The verification executing section 140 sends a request command for executing the verification processing to the image processing DSP verification section 200.

The verification continuation section 141 sends a request to the image processing DSP verification section 200 to continue the verification processing when the verification processing is interrupted at the point set by the interruption point setting section 133. Has been made.

The verification suspending unit 142 sends a verification suspension request to the image processing DSP verifying unit 200 during the execution of the verification process.

The verification step execution unit 143 receives the verification suspension request from the suspension point setting unit 133 or the verification suspension unit 143, and if the image processing DSP verification unit 200 suspends the verification process, the designated step ( A request to continue the processing for one to several steps) is supplied to the image processing DSP verification unit 200.

The result display section 153 displays data output from the output data acquisition section 313 or the verification result acquisition section 360 described later.

When displaying the data output from the output data obtaining unit 313 or the verification result obtaining unit 360 on the result display unit 153, the text information display selecting unit 151 displays the data as text information (that is, character information). You have been made to choose.

The signal waveform information display selection unit 152 displays the signal output from the output data acquisition unit 313 or the verification result acquisition unit 360 on the result display unit 153 as signal waveform information (ie, image information). You have been made to choose.

The result output file selecting section 160 is an interface for recording the processing results obtained from the verification result obtaining section 360 or the output data obtaining section 313 on the data recording medium 301 described later.

The result output file setting section 161 performs various settings for recording the processing result obtained from the verification result obtaining section 360 or the output data obtaining section 313 on the data recording medium 301 described later. . That is,
The result output file setting unit 161 includes a result output file name setting unit 162 and a result output file output range setting unit 163. The processing result corresponding to the range set by the result output file output range setting unit 163. Output data file name setting unit 16
2, and the data is recorded on the data recording medium 301.

Returning to FIG. 5, the signal control section 280 receives control signal information supplied via the interface section 100 and controls signals of each section.

The source program supply unit 324 acquires the program name of the application program to be verified from the program name setting unit 121 and supplies the corresponding program to the compiler 323.

The compiler 323 compiles the source program supplied from the source program supply section 324 under the control of the program compilation section 123 of the interface section 100.

The machine language program supply section 325 supplies the machine language program (compiled application program) supplied from the compiler 323 to a predetermined processor block of the processor block section 400.

The input data supply unit 311 obtains the file name of the image data set in the input data setting unit 111, and stores the corresponding image data in the data recording medium 3.
01 and supplied to the image processing DSP verification unit 200.

The verification result acquisition unit 360 is provided with an image processing DSP
The data and the values of the registers stored in the memory of each processor block of the verification unit 200 are received and supplied to the interface unit 100.

The output data acquisition unit 313 is provided with an image processing DS
The image data processed by the P verification unit 200 is received and output to the interface unit 100.

The data recording medium 301 supplies data such as image data and application programs to the interface unit 100 in response to a request from the interface unit 100, and outputs the various files output from the interface unit 100. Is recorded.

The image display unit 317 displays and outputs the processing result data output from the image processing DSP verification unit 200 as image data.

The signal waveform display unit 352 includes an image processing DSP
The processing result data output from the verification unit 200 or the value of the register of the processor block or the like is displayed and output as a signal waveform.

The text information display section 351 performs image processing D
The processing result data output from the SP verification unit 200 or the value of the register of the processor block or the like is displayed and output as text format data.

Next, the operation of the above example will be described.

Now, as a project file name,
If "hfil.prj" is input, the project file name is supplied to the data recording medium 301. If a project file having the same name exists, the file is read out and the interface unit 1
00 is supplied. If a file with the same name does not exist, for example, when ending the verification process,
The input file name is given and recorded on the data recording medium 301 as a new file.

Next, it is assumed that, for example, a file name of a source file “matrix-b.lap” is input to the program name setting unit 121 as a program name of an application program to be verified.
Then, the file name is supplied to the data recording medium 301, the corresponding source file is read, and supplied to the interface unit 100. As a result, the program display unit 122 of the interface unit 100 displays FIG.
The source file will be displayed as shown in.

Next, the input data setting unit 111 is operated, and as a file name of the image data to be processed, for example,
Assuming that “car.vd” is input, the file name is transmitted from the interface unit 100 to the data recording medium 3.
01, and the corresponding file is read and supplied to the interface unit 100. The interface unit 100 outputs the supplied image data to the input data supply unit 311.

Further, if the output data setting unit 113 is operated and, for example, the text information display unit 351 is selected as the output destination of the verification result data, the information is transmitted from the interface unit 100 to the text information display unit 351. Supplied.

Subsequently, the result output file setting unit 161 sets “resu” as the file name of the verification result data.
lt. out ”is input, and 0 is set as the output range.
This data is stored in the interface unit 100 if steps 1500 through 1500 are input. Then, the verification is started and the processor cycle is set to 0 to 15
00, the data of the verification result is transmitted to the data recording medium 301, and “result.
"out".

Next, the interruption point setting section 133 and the end condition setting section 134 are operated, and 1 is set as the interruption point.
Assuming that 23 steps are input and 1500 steps are input as the end condition, these data are stored inside the interface unit 100.

After the above settings have been made, when the program compiling section 123 is operated to instruct compilation of the program, the interface section 100 reads the data from the data recording medium 301 to the source program supply section 324. Supply source programs,
A compile request signal is supplied to the compiler 323. As a result, the source program output from the source program supply unit 324 is converted into a machine language by the compiler 323 and supplied to the machine language program supply unit 325.

The machine language program output from the machine language program supply unit 325 is supplied to each processor block of the processor unit 400. That is, in the example shown in FIG. 4A, the application program converted into the machine language is supplied to each of the processor blocks A to D. At this time, since the image data is supplied to the processor unit 400 via the input data supply unit 311 and the input unit 220, the processing described in the machine language program is performed on the image data. Will be. The resulting data is output to output unit 2
The output data is supplied to the output data acquisition unit 313 via 50.
When this process is being performed, the verification result acquisition unit 360 is supplied with the values stored in the registers and the memory inside the processor block.

The values of the registers and the memory of the processor block obtained by the verification result obtaining unit 360 and the processing result data obtained by the output data obtaining unit 313 are supplied to the result display unit 153 of the interface unit 100. . Then, according to the setting contents of the output data setting unit 113, the obtained data is supplied to the output unit in a corresponding display format. Since the text information display unit 351 is selected as the output destination, the data obtained by the verification result obtaining unit 360 and the output data obtaining unit 313 is converted into text format data in the interface unit 100, and The information is supplied to the information display unit 351. As a result, for example, a display as shown in the result display section 153 of FIG. 6 is performed.

At this time, when the number of cycles of the processor is within the range (0 to 1500 steps in this example) set in the result output file output range setting unit 163 of the result output setting unit 161. The data of the processing result acquired by the output data acquiring unit 313 is recorded on the data recording medium 301 with the file name (“result.out” in this example) set by the result output file name setting unit 162 added. You.

During the execution of the verification process, the number of cycles of the processor is displayed on the processing point display unit 13.
2 will be displayed sequentially. Then, when the number of cycles of the processor matches the value set in the interruption point setting unit 133, a message such as “processing has been stopped by Break Point” is displayed on the message display unit 103. Is displayed and the verification process is interrupted. In such a state, when the verification continuation unit 142 is operated, the verification processing is restarted. When the verification step execution unit 143 is operated in a state where the verification process is suspended, the set number of steps (for example, one step)
The processing will be executed step by step.

The verification process proceeds, and if the number of cycles of the processor matches the value set in the end condition setting unit 134, the verification process ends.

In the conventional verification apparatus as described above, since the image processing DSP is simulated by software, it is possible to display registers in the image processing DSP and data in the course of arithmetic processing. . As a result, it is possible to accurately perform the application software verification work of the image processing DSP.

[0075]

However, in the case of performing verification using the above-described software configuration, the target image processing apparatus (image processing DSP) requires a plurality of processor blocks and hundreds to thousands of blocks. It is composed of as many element processors as possible. Therefore, for example, when attempting to simulate such a parallel processing processor by a serial processing processor such as a workstation or a personal computer, the necessary arithmetic processing becomes enormous, and debugging (which is repeated many times during application program development) is repeated. There was a problem that a great deal of time was required for the verification) work.

Further, in the conventional verification device, when the image processing device has different operation modes (see FIG. 4),
Since it was designed to support only one of the operation modes, there was a problem that the same verification device could not simultaneously cover both different operation modes.

The present invention has been made in view of the above situation, and reduces the time required for developing an application program for an image processing apparatus that performs parallel processing, and also enables the image processing apparatus to operate in a plurality of operation modes. In this case, the verification can be performed by the same device even when the device is provided.

[0078]

According to a first aspect of the present invention, there is provided an application verification apparatus, comprising: a first selection unit that selects a processor block to be verified from at least one or more processor blocks; Second selecting means for selecting an application program corresponding to the processor block selected by the selecting means, and converting means for converting the application program selected by the second selecting means into an instruction code in a format that can be processed by the processor block And a supply unit that supplies the instruction code obtained by the conversion unit to the corresponding processor block, and a verification execution unit that executes application verification.

The application program verification method according to the present invention is selected by a first selection step of selecting a processor block to be verified from at least one or more processor blocks, and a first selection step. A second selecting step of selecting an application program corresponding to the processed processor block;
A conversion step of converting the application program selected by the second selection step into an instruction code in a format that can be processed by the processor block, a supply step of supplying the instruction code obtained from the conversion step to the corresponding processor block, And a verification execution step of executing the verification.

According to a twelfth aspect of the present invention, there is provided a medium comprising: a first selection step of selecting a processor block to be verified among processor blocks; and an application program corresponding to the processor block selected by the first selection step. A second selection step of selecting
A conversion step of converting the application program selected by the second selection step into an instruction code in a format that can be processed by the processor block, a supply step of supplying the instruction code obtained from the conversion step to the corresponding processor block, And a verification execution step of executing the verification of the above.

According to a thirteenth aspect of the present invention, the application program verifying device is selected by the first selecting means for selecting an element processor to be verified from at least one or more element processors, and the first selecting means. Second selection means for selecting an application program corresponding to a processor block including an element processor; conversion means for converting the application program selected by the second selection means into an instruction code in a format that can be processed by the processor block; It is characterized by comprising supply means for supplying the instruction code converted by the conversion means to the element processor, and verification execution means for executing application verification.

According to a sixteenth aspect of the present invention, an application program verifying method is selected by a first selecting step of selecting an element processor to be verified from at least one or more element processors and a first selecting step. A second selecting step of selecting a program corresponding to a processor block including each element processor;
A converting step of converting the program selected by the selecting step into an instruction code in a format that can be processed by the processor block, a supplying step of supplying the converted instruction code to the element processor, and a verification of the application. And a verification execution step.

The medium according to claim 17 has at least one medium.
A first selecting step of selecting an element processor to be verified from among one or more element processors, and a second selecting step of selecting a program corresponding to a processor block including each element processor selected by the first selecting step. A selecting step, a converting step of converting the program selected by the second selecting step into an instruction code in a format that can be processed by the processor block, and a supplying step of supplying the instruction code converted by the converting step to the element processor; And performing a verification of the application. The computer program is stored or transmitted.

In the application verification apparatus according to the first aspect, the processor block to be verified among the at least one processor block is the first processor block.
Is selected by the selection means, the second selection means selects an application program corresponding to the processor block selected by the first selection means, and the processor block can process the application program selected by the second selection means The conversion means converts the instruction code into an appropriate format, the supply means supplies the instruction code obtained by the conversion means to the corresponding processor block, and the verification execution means executes the verification of the application. For example, at least one
The first selecting means selects only one processor block to be verified from the one or more processor blocks,
The second selecting means selects an application program corresponding to the processor block selected by the selecting means, the converting means converts the application program selected by the second selecting means into a machine language, and supplies the obtained machine language. The means supplies the data to the processor block selected by the first selecting means, and the executing means starts executing the verification processing.

In the application verification method according to the eleventh aspect, the processor block to be verified is selected by the first selecting step from among the at least one processor block, and the processor block is selected by the first selecting step. A second selection step selects an application program corresponding to the processor block, and the conversion step converts the application program selected in the second selection step into an instruction code in a format that can be processed by the processor block. The supply step supplies the obtained instruction code to the corresponding processor block, and the verification execution step executes the verification of the application. For example, the first selection step selects only one processor block to be verified from at least one or more processor blocks, and the second selection step selects an application program corresponding to the processor block selected in the selection step. Is selected,
The conversion step converts the application program selected by the second selection step into a machine language, supplies the obtained machine language to the processor block selected by the first selection step, and executes the verification processing by the execution step. Start running.

In the medium according to the twelfth aspect, the processor block to be verified is selected by the first selecting step from among the at least one processor block, and the processor selected by the first selecting step is selected. Application program corresponding to the block
Is selected by the selecting step, and the converting step converts the application program selected by the second selecting step into an instruction code in a format that can be processed by the processor block, and converts the instruction code obtained from the conversion step to the corresponding processor block. A computer program provided by the providing step and executed by the verification performing step to verify the application is stored or transmitted. For example, the first selection step selects only one processor block to be verified from at least one or more processor blocks, and executes an application program corresponding to the processor block selected in the selection step in the second selection step.
Is selected by the selection step, the conversion step converts the application program selected by the second selection step into a machine language, and the supply step supplies the obtained machine language to the processor block selected by the first selection step. Then, a program whose execution step starts execution of the verification process is stored or transmitted.

[0087] In the application program verification device according to the thirteenth aspect, among the at least one or more element processors, the element processor to be verified is selected by the first selection means, and selected by the first selection means. The second selecting means selects an application program corresponding to a processor block including the selected element processor, and the converting means converts the application program selected by the second selecting means into an instruction code in a format that can be processed by the processor block. The supply means supplies the instruction code converted by the conversion means to the element processor, and the verification execution means executes the verification of the application. For example, the first selection means selects the number of element processors to be verified from at least one or more element processors, and executes the second application program corresponding to the processor block including the element processor selected by the selection means. The conversion means converts the application program selected by the selection means to the machine language, and supplies the obtained machine language to the element processor selected by the first selection means. Then, the execution means starts execution of the verification process.

In the application program verification method according to the present invention, among the at least one element processor, the element processor to be verified is selected by the first selecting step, and the element processor is selected by the first selecting step. The second selection step selects an application program corresponding to the processor block including the element processor, and the conversion step converts the application program selected by the second selection step into an instruction code in a format that can be processed by the processor block. The supply step supplies the instruction code converted by the conversion step to the element processor, and the verification execution step executes the verification of the application. For example, the first selection step selects the number of element processors to be verified from at least one or more element processors, and executes the second application program corresponding to the processor block including the element processor selected in the selection step. Is selected by the selection step, the conversion step converts the application program selected by the second selection step into a machine language, and the supply step supplies the obtained machine language to the element processor selected by the first selection step Then, the execution step starts execution of the verification process.

In the transmission medium according to the seventeenth aspect,
A first selection step selects an element processor to be verified from at least one or more element processors,
The second selection step selects an application program corresponding to the processor block including the element processor selected in the first selection step, and the processor block can process the application program selected in the second selection step. The conversion step converts the instruction code into an instruction code, and the supply step supplies the instruction code converted by the conversion step to the element processor, and stores or transmits a computer program that executes the verification of the application in the verification execution step. For example, the first selection step selects the number of element processors to be verified from at least one or more element processors, and executes the second application program corresponding to the processor block including the element processor selected in the selection step. Is selected by the selection step, the conversion step converts the application program selected by the second selection step into a machine language, and the supply step supplies the obtained machine language to the element processor selected by the first selection step A computer program whose execution step starts execution of the verification process is stored or transmitted.

[0090]

FIG. 1 is a block diagram showing a configuration example of an embodiment of the present invention. In this figure, FIG.
The same reference numerals are given to the portions corresponding to and the description thereof will be omitted. In this configuration example, for example, when a verification device is configured as software on a workstation or a personal computer, each function of the software is divided into functional blocks and represented.

In this embodiment, as compared with the case of FIG.
11-1 (second supply unit) and input data 2 supply unit 31
1-2 (second supply means). The input unit 220 of the image processing DSP verification unit 200
Are input 1 SAM unit 220-1 and input 2 SAM unit 220
-2. In this embodiment, the chip mode selection unit 302 and the processor block selection unit 3
20 (first selection means, operation mode selection means) and an element processor number control device 335 (first selection means) are newly added. Other configurations are the same as those in FIG.

FIG. 2 shows the interface unit 1 shown in FIG.
FIG. 9 is a diagram illustrating a detailed configuration example of 00 (instruction means, second instruction means). In this figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted. In this embodiment, the input data setting unit 111 is divided into an input data 1 setting unit 111 and an input data 2 setting unit 112 as compared with the case of FIG. The setting items of the processing point display unit 132, the interruption point display unit 133 (verification interruption setting unit), the end condition setting unit 134 (verification end setting unit), and the result output file name setting unit 162 include a frame number and a line. Numbers and have been added. Further, a chip mode selection unit 102, a processor block selection unit 120 (first selection unit, third selection unit, operation mode selection unit), and element processor number setting unit 1
35 (first selecting means), element processor number setting unit 1
50 (third selection means) and data management unit 115
(Setting means) is newly added.

In the present embodiment shown in FIG. 1, input data 1 supply section 311-1 has input data 1 setting section 111
Image data set by the interface 100
, And supplied to the input 1 SAM unit 220-1. Also, the input data 2 supply unit 31
1-2 reads the image data set by the input data 2 setting unit 112 via the interface 100 and supplies the image data to the input 2 SAM unit 220-2.

Input 1SA of image processing DSP verification unit 200
The M section 220-1 and the input 2 SAM section 220-2 correspond to the input SAM section 31 and the input SAM section 40 shown in FIG.

The chip mode selection unit 302 receives setting information of the operation mode (“multi-stage parallel processing mode” or “multiple processor mode”) of the image processing DSP verification unit 200 from the chip mode selection unit 102, and selects a processor block. Unit 320 and image processing DSP verification unit 200
To supply against.

The processor block selecting section 320 receives information on the processor block selected by the processor block selecting section 120, and receives the source program supplying section 324 (second selecting means), the machine language program supplying section 3
25 (supply means) and processor block unit 40
For 0, information about the selected processor block is supplied.

The element processor number control unit 335 receives information on the number of element processors (see FIG. 3) to be verified from the element processor number setting unit 135,
The image processing DSP verification unit 200 is controlled according to this information.

Next, a detailed configuration example of the interface unit 100 will be described with reference to FIG. In this figure, the chip mode selection unit 102 selects one of the operation modes of the image processing DSP verification unit 200 (“multi-stage parallel processing mode: SD mode” or “multiple processor mode: HD mode”). ing. Here, the SD mode means a standard definition (Standard Density) mode, and the HD mode means a high definition (High D
ensity) mode.

The input data 1 setting unit 111 and the input data 2 setting unit 112
11-1 and data to be supplied to the input data 2 supply unit 311-2 are set. At the time of setting, the file name of the data set in the data management unit 115 is received, the data corresponding to this file name is read from the data recording medium 301, and the input data 1 supply unit 311-1 and the input data 2 supply unit 311- 2 respectively. Note that the data recording medium 301
May be a transmission medium (for example, the Internet or a public telephone line).

The processor block selector 120 selects processor blocks to be verified (processor blocks A to D shown in FIG. 4A). The information input from the processor block selection unit 120 includes a processor block selection unit 320, a program name setting unit 121 (second selection unit), a program display unit 122 (application display unit), a memory grouping unit 131, and a text information display. The information is supplied to the selection unit 151, the signal waveform information display selection unit 152, and the result output file selection unit 160.

The processor block selecting section 12
The processor block that can be selected by 0 changes according to the setting contents of the chip mode selection unit 102. That is, when the setting content of the chip mode selection unit 102 is the SD mode, the processor blocks A to D operate independently as shown in FIG. 4A, so that all the processor blocks can be selected. Becomes On the other hand, when the setting content of the chip mode selection unit 102 is the HD mode, the two processor blocks operate as a pair as shown in FIG. Only one of B can be selected.

The processing point display section 132 displays the frame number, line number, and number of processor cycles of the image data currently being processed.
The interruption point setting unit 133 sets the point at which the verification process is interrupted as the frame number, line number, and number of processor cycles of the image data. The end condition setting unit 134 sets a point at which the verification process is ended as a frame number, a line number, and the number of cycles of the image data. When the image data to be processed is an interlaced image, the field number may be set (or displayed).

The element processor number setting section 135 sets the number of element processors to be verified. That is, the number of element processors to be actually operated among all N element processors shown in FIG. 3 is specified.

Element processor number setting section 150 displays data output from verification result obtaining section 360 and output data obtaining section 313 on result display section 153 (display means, verification result display means, second display means). At this time, the number of the element processor to be displayed is input so that only the data output from the desired element processor is displayed.

The data management section 115 manages input / output data, and the input data 1 setting section 11
1, when the input data 2 setting unit 112 and the output data setting unit 113 are operated, this window is displayed, and each setting item can be input.

That is, in this example, the data name setting unit 11
6. The image data display section 117 and the data information display section 118 are displayed, and it becomes possible to input the setting contents of each item. The data name setting unit 116 inputs a file name of the target image data. The input file name is referred to when the interface unit 100 reads image data from the data recording medium 301, or is used as a file name when recording the processing result data on the data recording medium 301.

The image data display section 117 displays image data (data read from the data recording medium 301 or data of a processing result) corresponding to the file name set in the data name setting section 116 in a predetermined display form. Is displayed. That is, the image data display unit 117 displays
The image data is displayed on the image display unit 317 (display unit, verification result display unit, second display unit), signal waveform display unit 352
(Display means, verification result display means, second display means) or text information display section 351 (display means, verification result display means, second display means). . In addition, it is good also as being able to display simultaneously by all these display forms.

The data information display section 118 displays information about the image data input to the data name setting section 116. For example, information on image data includes the number of frames of a moving image, the number of pixels forming horizontal scanning lines, the number of horizontal scanning lines, and the like.

Further, the result output file setting unit 161
Various settings for recording data supplied from the verification result acquisition unit 360 and the output data acquisition unit 313 on the data recording medium 301 are performed. The result output file name setting section 162 is configured to input a file name when the above-described data is recorded on the data recording medium 301. Result output file output range setting unit 163
The (display range designating means) designates a range of data to be output to the data recording medium 301. The setting items include a frame number of image data, a line number, and a cycle number of the processor. Can be entered.

The element processor number setting section 150
As described above, when displaying data output from the verification result obtaining unit 360 and the output data obtaining unit 313 on the result display unit 153, only data output from a desired element processor is displayed. , The number of the element processor to be displayed is input.

Next, the operation of the above embodiment will be described.

Now, as the project file name,
When “hfil.prj” is input, if a project file having the same name as the project file name is recorded on the data recording medium 301, the file is read and supplied to the interface unit 100. If a file having the same name is not recorded, the file is recorded on the data recording medium 301 as a new file, for example, when the verification process is completed.

Subsequently, when the chip mode selection unit 102 is operated and, for example, the SD mode is selected, the selection information is supplied to the chip mode selection unit 302. The chip mode selection unit 302 controls the processor block 400, and connects the processor blocks to each other as shown in FIG.
Change as shown in (A). When the HD mode is selected, the chip mode selection unit 302 changes the connection of the processor blocks as shown in FIG. In this example, since SD mode is selected,
The diamond displayed on the right side of “SD” in the chip mode selection unit 302 is highlighted and the processor blocks are connected as shown in FIG.

Next, assuming that the processor block selection unit 120 is operated to select a processor block to be verified, the selected information is stored in the processor block selection unit 320, the program name setting unit 121, the program display unit 122, A memory grouping unit 131, a text information display selection unit 151, a signal waveform information display selection unit 152,
Then, it is supplied to the result output file selection unit 160.
Now, in the chip mode selection unit 102, since the SD mode is selected, all of the processor blocks A to D operate independently, and as a result, all of the processor blocks A to D can be selected. When the HD mode is selected, either the processor block A or the processor block B can be selected.

Now, assuming that the processor block B is selected, the program to be verified is "hf
il-b. "asm"("b" after hfil indicates a program corresponding to the processor block B) is selected, displayed on the program name setting unit 121, and the corresponding file is read from the data recording medium 301. Are supplied to the source program supply unit 324. Further, this program is executed by the
0 is also supplied to the program display unit 122. In this example, since the source program display selection unit 124 has been selected, the source file “hfil-
b. Asm "will be displayed.

Subsequently, the program compiling section 123
When the (conversion means) is operated, the compiler 323 (conversion means) executes the compilation processing of the source program, and the obtained machine language program is supplied to the machine language program supply unit 325. When the machine language program display selection unit 125 is operated after the execution of the compiling process, the machine language program generated by the compilation is displayed on the program display unit 122.

Next, when the input data 1 setting unit 111 is operated, the data management unit 115 is displayed, and the file name of the image data to be processed can be input. For example, when "car.vd" is input as the file name of the image data, the corresponding file is stored in the data recording medium 30.
1 and supplied to the input data 1 supply unit 311-1, and the image is displayed on the image data display unit 117. The data information display unit 118 also displays the number of frames of image data (= 3), the number of pixels forming horizontal scanning lines (= 320), and the number of horizontal scanning lines (= 24).
0) is displayed.

When output data setting section 113 is operated,
The result output file setting section 161 is displayed, and the output file name, the output range of the result output file, and the number of the element processor to be displayed can be input.

When control signal setting section 130 is operated, an interface (not shown) for setting control signal information is displayed, and the contents set on the interface are supplied to signal control section 280. .

When the memory grouping unit 131 is operated, a setting for grouping a specific register in an element processor to be verified becomes possible. The contents of the registers grouped in this manner are displayed on the result display unit 153 in a format corresponding to the information set on an interface (not shown) for setting a display format.

When the interruption point setting section 133 is operated and the interruption point is input as a frame number, a line number, and the number of cycles of the image data, those data are stored in the interface section 100. Further, even when the end condition setting unit 134 is operated and an end point is input, these data are stored in the interface unit 100.

Next, when the number-of-element-processors setting section 135 is operated and the number of element processors to be verified is input, the input value becomes the number-of-element-processors control section 3.
35. In this example, since the value 320 is input, the element processor number control unit 335 determines, for example, only the 320 element processors from the right side of the figure out of the N (≧ 320) element processors shown in FIG. Select and target for verification.

Then, the element processor number setting section 150
When the processor number of the element processor whose data is to be written to the output file is input, the value is stored in the interface unit 100 and is referred to when generating the output data. In this case, the value 2
Since the 9 and the value 34 have been input, when the verification process is started, the output data of the 29th to 34th element processors from the right side in FIG. 3 and the values of the registers and the like are supplied to the data recording medium 301, It will be recorded under the file name “result.out”.

After the settings described above have been made,
When the verification execution unit 140 (verification execution means) is operated, the verification process is started.

When the verification process is started, the machine language program is supplied from the machine language program supply unit 325 to the selected processor block in the processor block unit 400 of the image processing DSP verification unit 200. From the input data 1 supply unit 311-1, image data is supplied one horizontal line at a time.

In this example, the processor block selector 1
Since the processor block B is selected by 20, the machine language program supplied from the machine language program supply unit 325 is supplied to the processor block B.
The number of element processors setting unit input data 1 supply unit 31
The image data supplied from 1-1 is also supplied directly to the processor block B.
In 5, the number of element processors to be verified is 3
Since it is set to 20, the image data is supplied only to the 320 element processors from the right side in FIG.

Accordingly, the image data is processed by the 320 element processors from the right side of the processor block B in the figure, and the processing result is supplied to the output data acquisition unit 313. Also, the value of the register and the value of the memory during the processing are
The data is read out to the verification result obtaining unit 360 according to the setting content set in the memory grouping unit 131.

In the image processing DSP verification section 200, the chip mode selection section 102, the processor block selection section 12
0, the target image processing DSP is simulated according to the contents set in the element processor number setting unit 135 and the element processor number setting unit 150. For example, the processor blocks A to D correspond to the one-dimensional arrays A [] to D [], respectively, and the element processors of each processor block correspond to the elements of each array (for example, the second from the left side of the processor block A). The element processor corresponds to A [2]). Then, arithmetic processing corresponding to an instruction command (an instruction command for an image processing DSP) supplied from the machine language program supply unit 325 is performed on the values stored in these arrays, so that the target image is processed. It becomes possible to simulate the processing DSP.

When the operation mode of the chip is set to the HD mode, an array A [] and an array B [] having twice the number of elements are prepared, and the same processing as described above is performed on these. Should be executed.

Therefore, if the number of processor blocks (the number of arrays) and the number of element processors (the number of elements of an array) to be verified are limited as described above, the image processing DSP verification unit 200 executes the arithmetic processing. In this case, it is possible to reduce the amount of calculation required.

The data obtained by the verification result obtaining unit 360 is grouped according to the setting contents of the grouping unit 131. When the text information display selection unit 151 is selected, the grouped data is displayed on the result display unit 153 as text information. Also,
When the signal waveform information display selection section 152 is selected, the grouped data is displayed on the result display section 153 as a signal waveform.

The image data of the processing result obtained by the output data obtaining unit 313 is supplied to the image display unit 317 (display means, verification result display means), and as a result, for example, the data management unit 115 of FIG. Image data display section 1
The image is displayed and output as an image shown in FIG.

When the verification process is being executed, the program of the currently executed portion is highlighted in the program display section 122. In the data displayed and output on the result display unit 153, a part corresponding to the part currently being executed is highlighted.

The above processing continues, and the input data 1
When the image data supplied from the supply unit 311-1 becomes equal to the interruption point set in the interruption point setting unit 133, a control signal is supplied from the interface unit 100 to the image processing DSP verification unit 200. Thus, the verification process is temporarily interrupted.

Then, in a state where the processing is interrupted,
When the verification continuation unit 141 (verification continuation unit) is operated, a predetermined control signal is supplied from the interface unit 100 to the image processing DSP verification unit 200, and the verification process is restarted.

When the image data supplied from the input data 1 supply unit 311-1 becomes equal to the end point set in the end condition setting unit 134, the interface unit 100 sends the image processing DSP verification unit 200 , A control signal is supplied, and the verification processing ends.

Further, when the verification step execution unit 143 is operated in a state where the processing is interrupted, the program is executed forward or backward at every predetermined step for one operation.

When the verification process is completed as described above,
Among the data output from the verification result obtaining unit 360 and the output data obtaining unit 313, the result output file selecting unit 160
The data corresponding to the range set in the result output file output range setting section 163 is supplied to the data recording medium 301 and recorded with the file name set in the result output file name setting section 162 added. become.

In the above embodiment, since the operation mode of the image processing DSP can be selected by the chip mode selection unit 102, any of the “multi-stage parallel processing mode” and the “multi-element processor mode” It is also possible to respond to modes.

Further, since the processor block selecting section 120 and the element processor number setting section 135 are provided, it is possible to narrow down the target of the verification processing. For example, in a case where an application program includes an error, in order to find the error, first, a verification operation is performed for each block to find a block including the error,
Next, if the verification work is performed with the number of element processors limited, the time required for verification can be significantly reduced as compared with the case where all processor blocks are verified as in the past, and the accuracy can be reduced. Verification can be realized. Further, when the processor blocks A to D are all performing the same processing (all are operating with the same application program), verification of only one of the processor blocks can be performed on other processor blocks. Since the verification need not be performed, the time required for the verification can be reduced.

Further, the settings of the point currently being processed, the point at which the processing is interrupted, the end point of the processing, the output range of the result output file, etc. , It is possible to make these settings in units that are easy for the user to understand.

Furthermore, since the program display section 122 and the result display section 153 are displayed in reverse video (mark display) in conjunction with the processing steps, it is easy for the user to specify the location where the problem has occurred, and the image data can be easily displayed. It is possible to improve the verification efficiency of the image processing DSP that handles such a large amount of data.

In the above embodiment, the entire apparatus is configured on a workstation or a personal computer. For example, only the image processing DSP verification unit 20 is configured on a board (CPU, ROM, etc.). , R
AM, an interface, and the like), and a circuit formed on this board allows a target image processing D
Of course, the SP may be emulated. According to such a configuration, since the image processing DSP is emulated in hardware, it is possible to further reduce the time required for the verification processing.

Further, in the above embodiment, the case where the image processing DSP has two input SAM units and four processor blocks has been described, but the present invention is limited to such a case. However, it is needless to say that the present invention is applicable to cases where these numbers are different from such cases.

[0145]

According to the application verification apparatus of the first aspect and the application verification method of the eleventh aspect, a processor block to be verified is selected and selected from at least one or more processor blocks. Selecting an application program corresponding to the selected processor block, converting the selected application program into an instruction code in a format that can be processed by the processor block, supplying the obtained instruction code to the corresponding processor block, and verifying the application. Is executed, the verification of the application program can be executed quickly even when the semiconductor device to be dealt with comprises at least one or more processor blocks.

According to the medium of the twelfth aspect, a processor block to be verified is selected from at least one processor block, and an application program corresponding to the selected processor block is selected. Since the converted application program is converted into an instruction code in a format that can be processed by the processor block, the obtained instruction code is supplied to the corresponding processor block, and a program for executing application verification is stored or transmitted. Even when the semiconductor device to be dealt with includes at least one or more processor blocks, the verification of the application program can be executed quickly.

According to the application program verifying apparatus and the application program verifying method of the present invention, an element processor to be verified is selected and selected from at least one or more element processors. Selecting an application program corresponding to the processor block including the element processor, converting the selected application program into an instruction code in a format that can be processed by the processor block,
Since the obtained instruction code is supplied to the element processor and application verification is executed, even when the target semiconductor device is configured by at least one or more element processors, the element to be verified is By arbitrarily setting the number of processors, it is possible to efficiently execute the application program verification work.

In the transmission medium according to claim 17, an element processor to be verified is selected from among at least one or more element processors, and an application program corresponding to a processor block including the selected element processor is selected. Since the selected application program is converted into an instruction code in a format that can be processed by the processor block, the obtained instruction code is supplied to the element processor, and a computer program for executing application verification is stored or transmitted. Even when the target semiconductor device is configured by at least one or more element processors, the verification of the application program can be efficiently executed by arbitrarily setting the number of element processors to be verified. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration example of an interface unit 100 shown in FIG.

FIG. 3 is a block diagram illustrating each operation mode of the image processing DSP having a plurality of operation modes.

FIG. 4 is a block diagram illustrating an internal configuration of an image processing DSP.

FIG. 5 is a block diagram illustrating a configuration example of a conventional image processing DSP verification device.

FIG. 6 is a diagram showing a detailed configuration example of an interface unit 100 shown in FIG. 5;

[Explanation of symbols]

100 interface unit (instruction unit, second instruction unit), 115 data management unit (setting unit), 120
Processor block selection unit (first selection unit, third selection unit, operation mode selection unit), 121 program name setting unit (second selection unit), 122 program display unit (application display unit), 123 program compilation unit (Conversion means), 133 interruption point display section (verification suspension setting section), 134 end condition setting section (verification end setting section), 135 element processor number setting section (first selection section), 140 verification execution section (verification execution) Means, 141 verification continuation section (verification continuation means), 150 element processor number setting section (third selection means), 153 result display section (display means, verification result display means, second display means), 163 result output File output range setting unit (display range specifying means), 311-
1 input data 1 supply unit (second supply means), 311
-2 input data 2 supply unit (second supply means), 31
7 image display unit (display unit, verification result display unit, second display unit), 320 processor block selection unit (first selection unit, operation mode selection unit), 323 compiler (conversion unit), 324 source program supply unit (Second selection means), 325 machine language program supply section (supply means), 335 element processor number control device (first selection means), 351 text information display section (display means, verification result display means, second Display means),
352 signal waveform display unit (display means, verification result display means, second display means)

Claims (17)

[Claims] 1. An application program verifying apparatus for verifying an operation of an application program of a data processing semiconductor device including at least one processor block, wherein a processor block to be verified is selected from the processor blocks. First selecting means for selecting, an application program corresponding to the processor block selected by the first selecting means, and an application program selected by the second selecting means. A conversion unit that converts the instruction code into a format that can be processed by the processor block; a supply unit that supplies the instruction code obtained by the conversion unit to the corresponding processor block; and a verification execution unit that performs verification of the application. Be prepared Application program verification apparatus according to claim Rukoto. 2. A setting unit for setting processing target data to be supplied to each processor block selected by the first selection unit, and supplying the processing target data set by the setting unit to the processor block. The application program verification device according to claim 1, further comprising a second supply unit. 3. A processor for selecting a processor block for displaying a processing result from among the processor blocks selected by the first selector, and a processor for selecting a processor block selected by the third selector. The application program verification device according to claim 1, further comprising a display unit that displays a processing result. 4. The data processing semiconductor device has a plurality of operation modes, and further comprises an operation mode selection means for selecting any one of the plurality of operation modes. The application program verification device according to claim 1, wherein 5. The data processing semiconductor device is an image processing semiconductor device for processing image data, and after the verification is started by the verification execution means, a timing at which the verification is interrupted is set on the image data. The application program verification apparatus according to claim 1, further comprising a verification suspension setting unit that sets the information as the position information. 6. The application program according to claim 5, further comprising a verification continuation unit for continuing the verification again when the verification is interrupted at the timing set by the verification interruption setting unit. Verification device. 7. The data processing semiconductor device is an image processing semiconductor device that processes image data. After the verification is started by the verification execution unit, the timing of ending the verification is determined based on the image data. 2. The application program verification device according to claim 1, further comprising verification end setting means for setting the information as the position information. 8. The data processing semiconductor device is an image processing semiconductor device for processing image data, and among the verification results obtained when the verification is started by the verification execution unit, is to be displayed. A display range designating unit for designating a range by a position on the image data; and a verification result display unit for displaying a verification result corresponding to the image data included in the range designated by the display range designating unit. The application program verification device according to claim 1, wherein: 9. An application program displaying means for displaying the application program, and, when verification is started by the verification executing means, an application program currently being executed among the application programs displayed by the application program displaying means. 2. The application program verification device according to claim 1, further comprising instruction means for designating a part. 10. A verification result display means for displaying a verification result, and a part of the application program indicated by the instruction means among the verification results displayed on the verification result display means is executed. 10. The application program verification device according to claim 9, further comprising second instruction means for instructing the obtained verification result. 11. An application program verifying method for verifying an operation of an application program of a data processing semiconductor device including at least one processor block, wherein a processor block to be verified is selected from the processor blocks. A first selecting step of selecting an application program corresponding to the processor block selected by the first selecting step, and a step of selecting the application program selected by the second selecting step. A conversion step of converting the instruction code into a format that can be processed by the processor block; a supply step of supplying the instruction code obtained from the conversion step to the corresponding processor block; Application program verification method characterized by comprising a verification execution step of executing. 12. A medium in which a computer program for verifying an operation of an application program of a data processing semiconductor device including at least one processor block is stored or transmitted. A first selection step of selecting a processor block, a second selection step of selecting an application program corresponding to the processor block selected by the first selection step, and a selection step of the second selection step. A conversion step of converting the application program into an instruction code in a format that can be processed by the processor block; a supply step of supplying the instruction code obtained from the conversion step to the corresponding processor block; Medium having a computer program is stored or transmitted and a verification execution step of executing a validation Shon. 13. An application program verification device for verifying an operation of an application program of a SIMD semiconductor device including at least one or more element processors, wherein an element processor to be verified among the element processors is selected. 1 selecting means, 2nd selecting means for selecting an application program corresponding to a processor block including an element processor selected by the 1st selecting means, and the application program selected by the 2nd selecting means Converting means for converting the instruction code into an instruction code in a format that can be processed by the processor block; supplying means for supplying the instruction code converted by the conversion means to the element processor; and verification executing means for executing the verification of the application And Application program verification device, wherein the obtaining. 14. The apparatus further comprising: third selection means for selecting an element processor for which a processing result is to be displayed; and display means for displaying a processing result of the element processor selected by the third selection means. The application program verification device according to claim 13, wherein: 15. The apparatus according to claim 15, further comprising a second display unit for displaying a predetermined internal value of the element processor selected by the third selection unit when the verification is executed by the verification execution unit. The application program verification device according to claim 14, wherein: 16. An application program verification method for verifying an operation of an application program of a SIMD data semiconductor device comprising at least one or more element processors, wherein the at least one or more element processors are to be verified. A first selecting step of selecting an element processor; a second selecting step of selecting a program corresponding to a processor block including each element processor selected by the first selecting step; and a second selecting step. A conversion step of converting the selected program into an instruction code in a format that can be processed by the processor block; a supply step of supplying the instruction code converted by the conversion step to the element processor; and verifying the application. Application program verification method characterized by comprising a verification execution step of rows. 17. A medium for storing or transmitting a computer program for verifying an operation of an application program of a SIMD type data semiconductor device comprising at least one or more element processors, the element to be verified among the element processors A first selecting step of selecting a processor; a second selecting step of selecting a program corresponding to a processor block including each element processor selected by the first selecting step; and a selecting step by the second selecting step Converting the converted program into an instruction code in a format that can be processed by the processor block, supplying the instruction code converted by the conversion step to the element processor, and executing verification of the application Do Medium having a computer program is stored or transmitted in that it comprises a witness execution step.