JPH1165882A - Device and method for verifying program and transmission medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently verify a program to be used for a single instruction multiple data(SIMD) type processor by controlling a data bus for transforming data to a prescribed format and inputting the data corresponding to a control signal. SOLUTION: A data generating part 1 for image processing digital signal processor(DSP) transforms data corresponding to an input image select signal and an input data bus select signal inputted to an input part 4 and outputs these data to an image processing DSP verifying part 2. The image processing DSP verifying part 2 receives sample data through an input data bus 21 controlled corresponding to the input data bus select signal and performs the verifying processing of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a program verification device and method, and a transmission medium, and more particularly, to a program verification device and method for verifying a program used in a digital signal processor (DSP), and a transmission medium.

[0002]

2. Description of the Related Art With recent advances in semiconductor technology, images have been treated as digital data.
In signal processing for such image data, 1
In many cases, the same arithmetic processing is performed on all pixels constituting a sheet of image. In this case, SIMD (S) developed to execute similar arithmetic processing on many data at high speed
Ingle Instruction Multiple Data-stream (single instruction multiple data) type processors may be used. SIMD
In the type processor, the required number of element processors are arranged, and each element processor operates according to the same instruction. Therefore, by giving data to each element processor separately, an operation result for each data can be obtained by one operation.

[0003] An application of a SIMD type processor to an image processing apparatus is described in "SVP: SERIAL VIDEO PROCESSOR / PROCE".
EDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIRCUITS
The device described in "CONFERENCE / P.17.3.1-4" is known. FIG. 7 shows a configuration example of this device.
This device includes an input SAM (Serial Access Memory) unit 91,
Data memory unit 92, ALU (Arithmetic and Logical Uni
t) It comprises an array unit 93, an output SAM unit 94, and a program control unit 95.

An input SAM unit 91, a data memory unit 92, an ALU
The array unit 93 and the output SAM unit 94 constitute a group of element processors which are parallelized in a large number in the form of a linear array (linear array) as a whole. Represents. ALU array unit 93
Is a 1-bit arithmetic logic unit, which is a circuit mainly composed of full adders. That is, the element processors are bit processing processors. Since the bit processor is small in hardware, many element processors can be installed in parallel. For example, the parallel number of element processors for image processing often matches the number of pixels in a horizontal scanning period of an image signal.

The program control section 95 is provided with a program memory for storing a program, a sequence control circuit (not shown) for advancing the program, and the like. The program control unit 95 controls a number of element processors in conjunction with each other (SIMD control) according to a program stored in a program memory.

In order to develop a program used for such a SIMD type processor, it is necessary to verify whether the program is operating properly. FIG. 8 shows an example of such a program verification device.

[0007] The image processing DSP verification unit 2 includes an input SAM unit 22-
1, 22-2 (hereinafter, each input SAM unit 22-1, 22-2)
If it is not necessary to distinguish between
), The processor block unit 23, and the output
The SAM 24 is provided. Input SAM units 22-1, 22
-2 are input data supply units 15-1 and 15-2, respectively.
(Hereinafter, when it is not necessary to individually distinguish each of the input data supply units 15-1 and 15-2, the input data supply unit 15-1
) Is stored via the input data bus 21 and output to the processor block unit 23 at a predetermined timing. The processor block unit 23 includes:
The operations of the data memory unit 92, the ALU array unit 93, and the program control unit 95 of the image processing DSP shown in FIG. 7 are simulated by software, and the input data is processed according to a separately input program. Output. The output SAM unit 24 stores the input data and outputs it to the output data acquisition unit 3 at a predetermined timing.

[0008] The output data acquisition section 3 outputs the input data to the interface section 7 at a predetermined timing. The input unit 4 includes a user interface (e.g., a GUI (Graphic) for the user to select an input image.
cal User Interface)). The image display unit 5 displays data input from the interface unit 7. The data recording medium 6 stores image data. The interface unit 7 receives data or a control signal from each unit and outputs the data or control signal to a predetermined portion at a predetermined timing. The control unit 8 controls the entire program verification device. The input data supply units 15-1 and 15-2
At predetermined timing, the data input via the input data bus 21 is input to the input SAM units 22-1, 22-22, respectively.
Output to 2.

Next, the operation of the program verification device will be described with reference to the flowchart of FIG. In step S41, the user inputs an input image selection signal from the input unit 4, and selects image data to be a sample. In step S42, the image data corresponding to the input image selection signal is reproduced from the data recording medium 6, and the size of the image (the vertical direction H of the image and the horizontal direction W of the image) is obtained. In step 43, the vertical position of the image to be processed (the number of lines) h is set to an initial value h _0. In step S44, the position w of pixels in the horizontal direction of the image to be processed (scanning direction) is set to an initial value w _0.
In step S45, the position w in the scanning direction and the number of lines h
Are reproduced from the data recording medium 6 and input to the input data supply unit 15 via the interface unit 7.

In step S46, the position w of the pixel in the scanning direction is compared with its maximum value w ₀ + W, and if it is determined that w is smaller than w ₀ + W, the process proceeds to step S47. In step S47, w is incremented by 1, and the process returns to step S45. The same processing is sequentially repeated,
Pixel data on a predetermined line is sequentially acquired. In step S46, if it is determined that w and w ₀ + W is equal, the flow goes to Step S48. In step S48,
The number h of lines is compared with its maximum value h ₀ + H. If it is determined that h is smaller than h ₀ + H, the process proceeds to step S49 to acquire data of the next line. In step S49, h is incremented by 1, and the process returns to step S44. The same processing is repeated to sequentially acquire pixel data of a plurality of lines. In step S48, h
When it is determined that h ₀ + H are equal to each other, the data acquisition ends, and the process proceeds to step S50.

In step S50, the data input to the input data supply unit 15 is output to the image processing DSP processing unit 2. In step S51, the image processing DS
The data input to the P verification unit 2 is processed based on a separately input program, and the program verification processing is performed based on the processing result.

Next, details of the program verification processing in step S51 will be described with reference to the flowchart of FIG.

In step S61, sample data is input from the input data supply unit 15 to the input SAM unit 22. In step S62, a program to be verified is input to the processor block unit 23. Step S63
, The sample data is stored in the processor block 2
Processing is performed on the basis of the program input to 3, and the processing result is output to the output SAM unit 24. The processing result is output from the output SAM unit 24 by the output data acquisition unit 3 to the image display unit 5 via the interface unit 7.

In step S64, the user checks the processing result displayed on the image display unit 5 and determines whether the processing result is good. When it is determined that the processing result is good, the processing is terminated, and when it is determined that the processing result is not good, the process proceeds to step S65. Step S
At 65, a program debugging operation is performed.
The process returns to step S62 to verify the debugged program again.

As described above, verification and debugging are repeated until it is confirmed that the program is operating properly.

[0016]

SUMMARY OF THE INVENTION As described above, SIMD
When developing a program for a type processor, it is necessary to verify the details of the program.
The program is developed using a device that simulates the MD processor faithfully and that can observe input and output data.

However, the SIMD type processor is composed of hundreds to thousands of element processors,
The data input terminal of the MD type processor has a bus structure. Furthermore, since there are many types of data (format, size, bit length, etc.) to be input to the SIMD type processor, the input bus and the input bus are input. There are numerous combinations of various types of data. In order to verify all of these combinations, it is necessary to specially configure a device corresponding to the combination, and there has been a problem that the time required for this is longer than the time required for program development.

The present invention has been made in view of such a situation, and by converting input data and controlling the structure of an input bus, it is possible to efficiently verify a program used in a SIMD processor. Is what you do.

[0019]

According to a first aspect of the present invention, there is provided a program verifying apparatus for verifying a program used in a digital signal processor for performing data processing, comprising: a size converting means for converting a size of data; Format conversion means for converting the format of data, bit number conversion means for converting the number of bits of data, data bus conversion means for converting data into a format corresponding to a predetermined data bus, and processing corresponding to a digital signal processor. Processing means for performing, size conversion means,
It is characterized by comprising a format converting means, a bit number converting means, a data bus converting means, and a signal receiving means for receiving a control signal for controlling the processing means.

According to a second aspect of the present invention, there is provided a program verification method comprising:
In a program verification method for verifying a program used in a digital signal processor for performing data processing, a size conversion step for converting data size, a format conversion step for converting data format, and a bit number conversion for converting the number of bits of data Step, a data bus conversion step of converting data into a format corresponding to a predetermined data bus, a processing step of performing processing corresponding to a digital signal processor, a size conversion step, a format conversion step, a bit number conversion step, a data bus A conversion step and a signal receiving step of receiving a control signal for controlling the processing in the processing step are provided.

According to a third aspect of the present invention, in a transmission medium for transmitting a computer program for verifying a program used in a digital signal processor for performing data processing, a size conversion step for converting data size and a data format are performed. A format conversion step for converting, a bit number conversion step for converting the number of bits of data, a data bus conversion step for converting data into a format corresponding to a predetermined data bus, and a processing step for performing processing corresponding to the digital signal processor When,
A computer program including a size conversion step, a format conversion step, a bit number conversion step, a data bus conversion step, and a signal receiving step for receiving a control signal for controlling processing in the processing step is transmitted.

In the program verifying apparatus according to the first aspect, the size converting means converts the size of the data,
Format conversion means for converting the format of the data, bit number conversion means for converting the number of bits of the data,
Data bus conversion means converts data into a format corresponding to a predetermined data bus, processing means performs processing corresponding to a digital signal processor, and signal reception means performs size conversion means, format conversion means, bit number conversion. Means, a data bus converting means, and a control signal for controlling the processing means.

In the program verification method according to the second aspect and the transmission medium according to the third aspect, the size conversion step converts the size of the data, and the format conversion step converts the format of the data, The number conversion step converts the number of bits of the data, the data bus conversion step converts the data into a format corresponding to a predetermined data bus, the processing step performs a process corresponding to the digital signal processor, and a signal receiving step Is a size conversion step, a format conversion step,
A control signal for controlling processing in the bit number conversion step, the data bus conversion step, and the processing step is received.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows.

That is, a program verifying device according to a first aspect of the present invention is a program verifying device for verifying a program used in a digital signal processor that performs data processing. A size control unit 11), a format conversion unit for converting a data format (for example, the format conversion unit 12 in FIG. 1), and a bit number conversion unit for converting the number of bits of data (for example, the bit length control unit in FIG. 1) 13), data bus conversion means (for example, data bus control unit 14 in FIG. 1) for converting data into a format corresponding to a predetermined data bus, and processing means (for example, FIG. 1 image processing
A DSP verification unit 2) and a signal receiving unit (for example, the input unit 4 in FIG. 1) that receives a control signal for controlling the size converting unit, the format converting unit, the bit number converting unit, the data bus converting unit, and the processing unit. It is characterized by having.

However, of course, this description does not mean that each means is limited to those described.

The configuration of a program verification device to which the present invention is applied will be described with reference to FIG. This program verification device realizes a device for verifying a program for an image processing DSP, which is a kind of image processing device, with a software configuration. In this example, each function of the software is shown as a block, and blocks having the same functions as those of the program verification device shown in FIG. 8 are denoted by the same reference numerals.

The image processing DSP data generator 1 comprises an image size controller 11, a format converter 12, a bit length controller 13, a data bus controller 14, and input data supply units 15-1 and 15-2. The sample image is converted in accordance with the control signal and output to the image processing DSP verification unit 2.

The image size control unit 11 receives the control signal input from the input unit 4 via the interface unit 7, converts the image size according to the control signal, and outputs the image size to the format conversion unit 12. The format conversion unit 12 converts the format of the input data according to the control signal, and outputs the converted data to the bit length control unit 13. The bit length control unit 13 determines the number of bits of the input data as
The signal is converted according to the control signal and output to the data bus control unit 14. The data bus control unit 14 forms the input data into a bus structure by the number of data constituting the pixels of the image data so as to correspond to the input data bus 21 controlled according to the input data bus selection signal, Input data supply unit 1
5-1 or the input data supply unit 15-2. Input image supply units 15-1, 15-2
Input SAM units 22-1 and 22-2, respectively, at predetermined timing via input data bus 21.
22-2.

The image processing DSP verification unit 2 includes an input SAM unit 22-
1, 22-2, processor block unit 23, and output
The SAM unit 24 simulates the operation of the target image processing DSP by software. The input SAM unit 22 stores data input from the input data supply unit 15 via the input data bus 21,
Output to the processor block unit 23 at a predetermined timing. The processor block unit 23 processes the input data according to a separately input program, and outputs
The data is output to the M unit 24. Output SAM unit 24
Stores the input data and outputs it to the output data acquisition unit 3 at a predetermined timing.

The output data obtaining section 3 outputs the input data to the interface section 7 at a predetermined timing. The input unit 4 is a GUI displayed on the image display unit 5 and receives an input image selection signal and an input data bus selection signal input by the user. The image display unit 5 displays data input from the interface unit 7. The data recording medium 6 stores a file in which image data and control signals are set. The interface unit 7 receives data or a control signal from each unit and outputs it to each unit at a predetermined timing. The control unit 8 controls the entire program verification device.

Next, the operation of the program verification device will be described with reference to FIG. In step S1, when an input image selection signal for selecting image data to be a sample is input from the input unit 4, the image data corresponding to the input image selection signal is reproduced from the data recording medium 6 and transmitted via the interface unit 7. The data is output to the image processing DSP data generation unit 1. In step S2, a control signal such as an image size control signal is input from the input unit 4.

The details of the input of the control signal in steps S1 and S2 will be described with reference to FIG. FIG.
2 shows an example of a GUI as an input unit 4 for inputting an input image selection signal displayed on an image display unit 5. Tabs 51, 5
2 is designated by the cursor, and when clicked, switches between the GUI screens IR1 and IR2. On the GUI screens IR1 and IR2, control signals corresponding to data input to the input data supply units 15-1 and 15-2 are set, respectively. When the tab 53 is clicked, a GUI screen OR (not shown) for setting data to be obtained by the output data obtaining unit 3 is displayed. By inputting the image data name in the input image selection unit 54, the image data to be input to the image processing DSP data generation unit 1 is selected. When the reference button 55 is clicked, a list of image data recorded on the data recording medium 6 is displayed. When one of the image data names is designated with a cursor, the designated image data name is input. This is entered in the image selection section 54.

The format specifying section 56 specifies the format of the image data selected by the input image selecting section 54. In this case, bitmap formats (such as RGB),
One of three formats, 4: 2: 2 format or text data format, is specified. Image size input unit 5
In step 7, the number of frames of the image data input to the input data supply unit 15 and the number of pixels of the height and width of the image are input. When the inter-trace mode designating section 58 is checked, the data input to the input data supply section 15 is converted into the inter-trace mode (data that can be handled in common in standards such as NTSC and PAL).

In the control file selection section 59, an input data bus selection signal including a bit length control signal and the like is set in advance (used before and the data recording medium 6).
Is selected by writing the name of a control file (input data bus selection signal setting file) recorded in the file. When the reference button 60 is clicked, a list of control files recorded on the data recording medium 6 is displayed. When one of the file names is designated by the cursor, the designated control file name is changed to the control file name. This is entered in the selection section 59. When the edit button 61 is clicked, a GUI shown in FIG. 4 for editing the settings of the control file is displayed.

The control file name input section 71 shown in FIG.
In the field, a file name when the control file is stored in the data recording medium 6 is written. When the format of the text data format is designated in the format designation section 56, the radix of the text data is designated in the text data format designation section 72. When the bitmap format is designated in the format designation unit 56, the number of data constituting one pixel is designated in the data number designation unit 73 (for example, 3 is designated in the RGB format). ). When the 4: 2: 2 format is specified in the format specification section 56, the 4: 2: 2 format is used.
In the format specification section 74, the configuration of the input data bus is specified.

In the bit length input sections 75 to 80, the bit length of each data constituting one pixel is input corresponding to the number specified by the data number specifying section 73. In the start address parameter input units 81 to 86, parameters for controlling the start address of each data constituting one pixel are input corresponding to the number designated by the data number designation unit 73. When the OK button 87 is clicked, the setting of the control file is completed, and the control file is stored in the data recording medium 6 with the name entered in the control file name input section 71. When the cancel button 88 is clicked, the setting of the control file is stopped, and the GUI is closed.

Returning to the description of FIG. When the OK button 62 is clicked, the set input image selection signal is
The image data is added to the image data selected by the input image selection unit 54 and stored in the data recording medium 6. When the cancel button 63 is clicked, the setting of the input image selection signal is stopped, and the GUI is closed. When the help button 64 is clicked, a description of the setting item is displayed.

Returning to the description of FIG. In step S3, the image size control unit 11 controls the image size input unit 5
The size of the image to be sampled (vertical H dots, horizontal W dots) is determined in accordance with the value input to. Step S
4, the image size control unit 11 controls the position h of the pixel (the number of lines) in the vertical direction in the input image data.
Is set to the initial value h ₀ . In step S5, the image size control section 11 is position w of pixels in the horizontal direction (scanning direction) is set to an initial value w _0, the image data is output to the format conversion unit 12.

In step S 6, the image data input to the format conversion unit 12 is decomposed into a predetermined data format based on the format specified by the format specification unit 56. In step S7, the pixel data having the position w in the scanning direction of the image data and the number h of lines is output to the bit length control unit 13. In step S8,
The number of bits of the pixel data input to the bit length control unit 13 is converted based on the values input at the bit length input units 75 to 80, and is output to the data bus control unit 14.

The details of the bit length conversion processing in step S8 will be described with reference to the flowchart in FIG.

In step S21, the bit number value of the pixel data input to the bit length control unit 13 is confirmed. In step S22, the bit number n input to the bit length input units 75 to 80 is input to the bit length control unit 13 as a bit length control signal. Step S23
In, the number of bits of the pixel data is compared with the magnitude of the bit length control signal n, and the number of bits of the pixel data value
Is larger than the bit length control signal n, step S2
Proceed to 4. In step S24, the pixel data is subjected to a rounding process (higher n bits or less, truncation), and is converted into data having the same bit number n as the bit length control signal n. If the bit number value of the pixel data is smaller than the bit length control signal n, the process of step S24 is skipped. In step S25, the pixel data having the bit number n or less is output to the data bus control unit 14.

Returning to the description of FIG. In step S9, the pixel data is bus-structured by the data bus control unit 14. Details of the bus structuring process in step S9 will be described with reference to the flowchart in FIG.

In step S31, the data bus control unit 14 obtains the number D of data constituting one pixel input by the data number designation unit 73. Step S
At 32, a counter d counting D is initialized to one. In step S33, the start address parameter input units 81 to 86 are controlled by the data bus control unit 14.
The start address of the data on the input data bus 21 is determined on the basis of the value input to. Step S3
In step 4, one of the data constituting the pixel is written in order from the start address determined in step S33. In step S35, the counters d and D
Are compared, and if d is smaller than D, the process proceeds to step S36, d is incremented by 1, and the process returns to step S33 to write the next data constituting the pixel. If it is determined in step S35 that d is equal to D, the process proceeds to step S37. In step S37,
Data in which all the data constituting the pixel are written in order (bus-structured) is output to the input data supply unit 15.

Returning to the description of FIG. As described above, after the bus structuring process is performed in step S9, the process proceeds to step S1.
At 0, the image size control unit 11 compares the position w of the pixel in the scanning direction with its maximum value w ₀ + W. If w is smaller than w ₀ + W, the process proceeds to step S11, and w is incremented by 1. Then, the process returns to step S6 to process the adjacent pixel data on the same line. If w is equal to w ₀ + W, the image size controller 11 compares the number h of lines with its maximum value h ₀ + H in step S12. h is h ₀
If it is smaller than + H, the process proceeds to step S13, h is incremented by 1, and the process returns to step S5 to process the data of the next line. If h is equal to h ₀ + H, the process proceeds to step S14. In step S14, the bus structured data is output from the input data supply unit 15 to the input SAM unit 22 via the input data bus 21 in the image processing DSP verification unit 2.

In step S15, the image processing DSP verification unit 2 performs a program verification process. Note that the operation of this verification processing is the same as the processing described in the flowchart of FIG. 10, and a description thereof will be omitted.

In the above description, the input unit 4 in FIG. 1 is a GUI, but may be a command input type interface using a keyboard.

The program for performing each of the above processes can be transmitted to the user via a transmission medium such as a magnetic disk or a CD-ROM or a network transmission medium such as the Internet or a digital satellite, in addition to a transmission medium including an information recording medium.

[0049]

As described above, the program verification device according to the first aspect, the program verification method according to the second aspect,
According to the transmission medium of the present invention, since the data and the data bus for inputting the data are controlled based on the control signal, the program used for the SIMD type processor can be efficiently verified. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a program verification device to which the present invention has been applied.

FIG. 2 is a flowchart illustrating a verification process of the program verification device of FIG. 1;

FIG. 3 is a diagram illustrating an input example of step S1 in FIG. 2;

FIG. 4 is a diagram illustrating another input example of step S2 in FIG. 2;

FIG. 5 is a flowchart illustrating details of a bit length conversion process in step S8 of FIG. 2;

FIG. 6 is a flowchart illustrating details of a bus structuring process in step S9 of FIG. 2;

FIG. 7 is a block diagram illustrating a configuration of a SIMD processor.

FIG. 8 is a block diagram illustrating a configuration of an example of a conventional program verification device.

FIG. 9 is a flowchart illustrating a verification process of the program verification device of FIG. 8;

FIG. 10 is a flowchart illustrating details of a verification process in step S51 of FIG. 9;

[Explanation of symbols]

1 Image processing DSP data generation unit, 2 Image processing DSP verification unit, 3 Output data acquisition unit, 4 Input unit, 5
Image display unit, 6 data recording medium, 7 interface unit, 8 control unit, 11 image data size control unit, 12 format conversion unit, 13 bit length control unit, 14 data bus control unit, 15 input data supply unit, 21 input data Bus, 22 input SAM unit,
23 processor block section, 24 output SAM section,
91 input SAM section, 92 data memory section, 93 A
LU array section, 94 output SAM section, 95 program control section

Claims (3)

[Claims] 1. A program verification device for verifying a program used in a digital signal processor for performing data processing, comprising: a size conversion unit for converting data size; a format conversion unit for converting data format; Bit number conversion means for conversion, data bus conversion means for converting data into a format corresponding to a predetermined data bus, processing means for performing processing corresponding to the digital signal processor, size conversion means, format conversion means And a signal receiving unit for receiving a control signal for controlling the bit number converting unit, the data bus converting unit, and the processing unit. 2. A program verification method for verifying a program used in a digital signal processor for performing data processing, comprising: a size conversion step for converting data size; a format conversion step for converting data format; A number-of-bits converting step; a data bus converting step of converting data into a format corresponding to a predetermined data bus; a processing step of performing a process corresponding to the digital signal processor; a size converting step; and the format converting step And a signal reception step of receiving a control signal for controlling processing in the bit number conversion step, the data bus conversion step, and the processing step. 3. A transmission medium for transmitting a computer program for verifying a program used in a digital signal processor for performing data processing, a size conversion step for converting data size, a format conversion step for converting data format, A number-of-bits conversion step of converting the number of bits; a data bus conversion step of converting data into a format corresponding to a predetermined data bus; a processing step of performing processing corresponding to the digital signal processor; and the size conversion step; Transmitting a computer program comprising a format conversion step, the bit number conversion step, the data bus conversion step, and a signal reception step of receiving a control signal for controlling processing in the processing step. Characteristic transmission medium.