JPH10254841A - Program verification device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time required for developing a program. SOLUTION: A control part 1 reads input data and the program of a verifying object from a recording medium 7 to respectively output to a data supplying part 3 and a program control part 2. In addition the part 1 reads the file of a verifying condition from the medium 7 and supplies the number of element processors 21-i to use for verification to an element processor operation control circuit 5. Then the part 1 makes the prescribed number of element processor 21-i of a parallel processor simulation part 4 to operate for verification. When the result of verification is not judged to be satisfactory, the program is debugged to verify again. In addition, verification is executed by gradually increasing the number of the element processors to use to be the number N of the element processor provided for the part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a program verification device and method, and more particularly to a program verification device and method for verifying a program processed by an information processing device having a plurality of element processors.

[0002]

2. Description of the Related Art With recent advances in semiconductor technology, images have been treated as electrical data.
In signal processing for such image data, 1
In many cases, the same arithmetic processing is performed on all pixels constituting a sheet of image. In that case, a SIM developed to execute the same arithmetic processing at high speed for many data
A D (Single Instruction Multiple Data-stream) processing device may be used.
In the SIMD type processing device, a required number of arithmetic devices are arranged, and each arithmetic device operates according to the same instruction. Therefore, when separate data is given to each processing device, a calculation result for each data can be obtained by one calculation.

[0003] As an example in which a SIMD type processing apparatus is applied to image processing, for example, "SVP: SERIAL VIDEO PROCESSOR /
PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIR
The device described in "CUITS CONFERENCE / P.17.3.1-4" is known. FIG. 3 shows a configuration example of this device. This device includes an input SAM (serial access memory) section 81, a data memory section 82, an ALU array section 8
3, an output SAM unit 84, a program control unit 85, and the like.

An input SAM unit 81, a data memory unit 82,
The ALU array unit 83 and the output SAM unit 84 constitute a group of multiple element processors which are parallelized in a linear array (linear array) type as a whole.
1 is controlled (SIMD control) in conjunction with the program control unit 85 in accordance with one common program.

The program control section 85 is provided with a program memory and a sequence control circuit for advancing the program. The program control unit 85 generates various control signals according to the program stored in the program memory and controls each part.

The input SAM unit 8 of one of the element processors 101 indicated by a slender vertical area shown by hatching in FIG.
1. Data memory unit 82 and output SAM unit 84
Form the "columns" of the memory. The ALU array unit 83 is a 1-bit ALU (Arithmetic and Logical U
nit), for example, having a full adder (full adder). That is, the element processor 101 is a bit processing processor. For this reason, each element processor 101
Since it can be realized by small-scale hardware, a large number of parallel circuits can be realized. For example, in an image processing apparatus, the parallel number of element processors often coincides with the number of pixels in one horizontal scanning period of a video signal.

FIG. 4 shows an example of a processing flow when a program for such a parallel processor is developed.

First, predetermined data is supplied to the input SAM unit 81 in step S21, and a program to be verified is supplied to the program control unit 85 in step S22. Then, in step S23, the program control unit 85 controls the data memory unit 82 and the ALU array unit 83 to perform data processing according to the program, and outputs the processing result via the output SAM unit 84.

At this time, the user causes the output result to be displayed on a predetermined display device, determines whether or not the result is good. In step S25, the program is debugged, the process returns to step S22, the changed program is input, and the verification is performed again.

In this way, the program is developed while the verification is repeated until the program operates correctly.

[0011]

By the way, when developing a program for a parallel processor, it is necessary to verify the details of the program. Therefore, it is necessary to observe detailed information such as the value of the data memory section of each element processor. is there. Therefore, a program is often developed using a device having a mechanism for observing such detailed information while faithfully simulating a target parallel processor.

However, due to the fact that the parallel processor shown in FIG. 3 is composed of hundreds to thousands of element processors, it is difficult to simulate the parallel processor with software operating on a single processor. Has a problem that it requires a processing time several thousand to tens of thousands times as large as that of an actual machine, and a long time is wasted due to the debugging work repeated many times in program development.

[0013] The present invention has been made in view of such a situation, and a program is developed by verifying a program using some or all of a predetermined number of element processors. To reduce the time required.

[0014]

According to a first aspect of the present invention, there is provided a program verifying apparatus comprising: a processing unit having a first number of element processors; and a second means used for verification among the first number of element processors. It is characterized by comprising selecting means for selecting the number of element processors, supplying means for supplying an instruction code corresponding to the program to the processing means, and output means for outputting the result of verification.

According to a fifth aspect of the present invention, there is provided a program verification method,
A second one of the first number of element processors used for verification.
Selecting the number of element processors, processing the instruction code corresponding to the program by the second number of element processors, and outputting the result of the verification.

In the program verifying device according to the first aspect, the selecting means selects a second number of element processors to be used for verification from among the first number of element processors of the processing means, and supplies the selecting means. Supplies the instruction code corresponding to the program to the processing means, and the output means outputs the result of the verification.

According to a fifth aspect of the present invention, in the program verifying method, a second number of element processors to be used for verification are selected from the first number of element processors, and an instruction code corresponding to the program is stored in the second number of element processors. Process with the number of element processors and output the result of verification.

[0018]

FIG. 1 shows a configuration of an embodiment of a program verifying apparatus according to the present invention. In this program verification device, the control unit 1 (change means, input means) includes a file in which a program of a parallel processor as a target (actual machine) is described, input data to be processed,
A setting file in which the number (initial value) of the element processors is described is read from a recording medium 7 such as a magnetic disk, and the program control unit 2 (supply unit), the data supply unit 3, and the element processor operation control circuit 5 (Selection means). Further, the control unit 1 performs processing in accordance with instructions and data input by the user on the operation unit 11.

The program control section 2 supplies a predetermined operation instruction to each element processor 21-i of the parallel processor simulation section 4 (processing means) in accordance with the program supplied from the control section 1. I have.

The data supply unit 3 converts the data supplied from the control unit 1 into an element processor 21 corresponding to the data.
-I.

The element processor operation control circuit 5 supplies the number N of element processors used for verification supplied from the control unit 1.
N element processors 21-1 to 21-21 corresponding to t
Of -N, the number Nt of element processors are set to an operable state, and the other element processors are set to an operation stop state.

The parallel processor simulation unit 4
It has predetermined N element processors, processes data supplied from the data supply unit 3 according to an instruction supplied from the program control unit 2, and outputs a processing result and a value of a predetermined memory, that is, a verification result. The data is output to the data observation device 6 (output means) and the control unit 1.

The output data observation device 6 converts the verification result supplied from the parallel processor simulation section 4 into display data as appropriate, and displays the data on, for example, a CRT (Cathode Ray Tube) not shown. It has been done.

Next, referring to the flowchart of FIG.
The flow of processing in program development using the program verification device of FIG. 1 will be described.

First, in step S1, the control unit 1
Reads input data stored in the recording medium 7 according to a user operation on the operation unit 11 and outputs the input data to the data supply unit 3.

Next, in step S2, the control unit 1
The program to be verified stored in the recording medium 7 is read out according to a user operation on the operation unit 11,
Output to the program control unit 2.

In step S3, the control unit 1 reads a file in which the verification conditions are described and stored in the recording medium 7 according to the operation of the operation unit 11 by the user, and reads the number of the element processors 21-i used for the verification ( (Initial number) Nt is supplied to the element processor operation control circuit 5.

Then, in step S4, the control unit 1
Supplies a predetermined signal to the program control unit 2, the data supply unit 3, and the element processor operation control circuit 5, and causes the Nt element processors 21-i of the parallel processor simulation unit 4 to operate for verification. .

When the processing in step S4 is completed,
The verification result is supplied from the parallel processor simulation unit 4 to the output data observation device 6 and the control unit 1.

Then, in step S5, it is determined whether or not the verification result is good. If it is determined that the verification result is good, the process proceeds to step S7.

When determining whether or not the verification result is good, the user makes a determination with reference to the display on the output data observation device 6 and operates the operation unit 11 or performs a predetermined operation. The reference value is stored in the control unit 1 in advance, and the reference value is compared with the verification result.

On the other hand, if it is determined that the verification result is not good, the program recorded on the recording medium 7 is changed by the user in step S6. That is, the program is debugged.

After the end of the debugging, the process returns to step S2, and the control unit 1 reads the debugged program from the recording medium 7 in response to the user's operation on the operation unit 11, supplies the read program to the program control unit 2, and executes the program. Let me update. Then, the verification is performed again.

In step S7, the control unit 1 determines that the number Nt of element processors used in the verification in step S4 is N (that is, the element processors 21-1 to 21- provided in the parallel processor simulation unit 4). N) or not, otherwise, in step S8, the number Nt of element processors to be used is increased and supplied to the element processor operation control circuit 5, and the process returns to step S4. The verification is performed again.

On the other hand, when it is determined that Nt ≧ N,
In step S9, the control unit 1 records all the verification results on the recording medium 7 and causes the output data observation device 6 to display the results.

As described above, each time the number Nt of element processors to be used is sequentially increased, the program is verified. Thus, in developing a program, first, by using a small number of element processors,
By performing verification under conditions where errors do not occur relatively, gradually increasing the number of element processors, and verifying the operation of the program when many element processors are used, debugging work becomes easier, The time required for program development can be reduced.

The present invention is not limited to the above embodiment, but can be applied to other devices.

[0038]

As described above, according to the program verifying apparatus of the first aspect and the program verifying method of the fifth aspect, the second one of the first number of element processors used for the verification is used. Is selected, and the instruction code corresponding to the program is processed by the second number of element processors, so that the time required for program development can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a program verification device of the present invention.

FIG. 2 is a flowchart illustrating the development of a program using the program verification device of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a parallel processor of a SIMD format.

FIG. 4 is a flowchart illustrating an example of conventional program development.

[Explanation of symbols]

1 control unit, 2 program control unit, 3 data supply unit, 4 parallel processor simulation unit, 5
Element processor operation control circuit, 6 output data observation device, 7 recording medium, 21-1 to 21-N element processor

Claims (5)

[Claims] 1. A program verification device for verifying a program processed by an information processing device having a plurality of element processors, wherein: a processing unit having a first number of element processors; Selecting means for selecting a second number of element processors to be used for verification; supplying means for supplying an instruction code corresponding to the program to the processing means; and output means for outputting the result of the verification. A program verification device characterized by the above-mentioned. 2. The program verification apparatus according to claim 1, further comprising a change unit that changes the second number according to the number of element processors used in the previous verification. 3. The program verification apparatus according to claim 1, further comprising an input unit that inputs a program changed according to a result of the verification to the supply unit. 4. The program verification device according to claim 1, wherein the information processing device is a parallel processor of a SIMD format. 5. A program verification method for verifying a program processed by an information processing device having a plurality of element processors by using a processing unit having a first number of element processors, wherein the first number of elements is Selecting, from among the processors, a second number of element processors to be used for verification; processing the instruction code corresponding to the program by the second number of element processors; and outputting the result of the verification. And a program verifying method.