JPH0863452A - Simd processor - Google Patents

Abstract

PURPOSE: To provide address generation matching image processing through small hardware for a local and a common memory so that each unit processor can process a partial image of up to several thousands of pixels. CONSTITUTION: A 1st address generator 26 supplies the image signal from a memory 25 to a unit processor 1. This signal includes signals that the unit processor 1 does not require and a control signal generator 28 supplies a signal to a register 11C so that no operation is performed to the unnecessary signals. At the same time, the supplied signal is supplied even to a 2nd address generator 27 so as to stop reading a signal out of the memory 12. In image processing, the shape of array of image signals processed by respective unit processors is in the same shape in the memory 25 and frequently shifts only in position. Therefore, the address generator 27 and control signal generator 28 are mounted on a control part 6 and delay units 18 and 21 are mounted by unit processors so as to absorb the position shift of the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system for executing image processing and the like in parallel, and more particularly to a SIMD processor.

[0002]

2. Description of the Related Art Isosai, Miyata, and Iwase, "Architecture of Cellular Array-type Large-scale Parallel Processor," as a publicly known example of a conventional SIMD type processor, Institute of Information Processing Society of Japan,
There is a computer architecture 73-9 (1988.10). By processing the unit processors and the pixel data in association with each other, it is possible to perform processing in parallel by the number of unit processors. That is, the two-dimensional array of pixel data is stored in a register or a local memory in a unit processor connected in a two-dimensional grid, and access to the pixel data around it is performed by shifting the entire two-dimensional array of pixel data. This is possible by performing data transfer between unit processors.

[0003]

However, in the prior art, in order for a certain unit processor to access the pixel data around it, it is necessary to transfer data between the unit processors, and in terms of hardware, wiring is required. The number was increasing.

An object of the present invention is to mount a unit processor local memory unit capable of holding a partial image composed of a plurality of pixel data so that processing can be completed in each unit processor, and to generate the address thereof. , It is to provide means to realize with minimum necessary hardware.

[0005]

The first invention is N (N
Is a natural number) in a SIMD processor including a unit processor group including a unit processor of a unit number, and the control unit includes an address generator and a control unit local memory, and each unit processor of the unit processor group includes A unit processor local memory unit, an arithmetic unit, an address input terminal, an address output terminal, a delay unit, a data input terminal, a data output terminal, and a data bus, wherein the delay unit has the address input terminal. The signal input to the address processor is delayed by a predetermined period and output to the address output terminal, the signal input to the address input terminal is supplied to the unit processor local memory unit as an address, and the data input terminal The data output terminals are connected by the data bus, and the data bus is connected to the unit processor. Data is supplied to a local memory unit, the data bus and the unit processor local memory unit supply data to the arithmetic unit, and the address generator is the address input terminal of the first unit processor of the unit processor group. To the i-th unit processor (i is 1 to N-1) of the unit processor group.
Natural number) up to the address input terminal of the (i + 1) th unit processor of the unit processor group, and the data output terminal of the i-th unit processor is connected to the (i + 1) th unit. It is characterized in that it is connected to the data input terminal of the processor.

The second invention is based on the first invention.
The delay period of the delay unit of each unit processor of the unit processor group is independently determined for each unit processor.

The third invention is the same as the first invention,
The control unit includes a timing signal generator, and an output signal of the timing signal generator alternately takes a first state and a second state for each predetermined arbitrary period, and the timing signal generator Is supplied to the address generator, and when the output signal of the timing signal generator is in the second state, the address generator stops the address generation.

A fourth aspect of the invention is the same as the third aspect of the invention.
Each unit processor of the unit processor group includes an operation control signal input terminal, an operation control signal output terminal, and a second delay device, and the second delay device is input to the operation control signal input terminal. A signal that is delayed by a predetermined period and is output to the arithmetic control signal output terminal, and the signal input to the arithmetic control signal input terminal is supplied to the arithmetic unit and input to the arithmetic control signal input terminal. In the second state, the operation unit stops the operation, and the timing signal generator causes the timing signal generator to operate in the first group of the unit processors.
A signal is supplied to the operation control signal output terminal of the unit processor, and the operation control signal output terminal of the i-th unit processor is connected to the operation control signal input terminal of the (i + 1) th unit processor. Is characterized by.

A fifth aspect of the invention is the same as the fourth aspect of the invention.
The delay period of the second delay unit of each unit processor of the unit processor group is independently set for each unit processor.

The sixth invention is based on the first invention.
In each unit processor of the unit processor group, the output of the arithmetic unit is supplied to the unit processor local memory unit.

A seventh aspect of the invention is based on the first aspect,
Each unit processor of the unit processor group includes a second data input terminal, a second data output terminal, and a second data bus, and the second data input terminal and the second data input terminal are provided.
Connected to the second data bus by the second data bus, the arithmetic unit supplies data to the second data bus, and the second data output terminal of the unit processor of i has the (i + 1) th data output terminal. ) Is connected to the second data input terminal of the unit processor.

An eighth invention is based on the first invention,
The control unit includes a second address generator, and the second address generator supplies an address to the control unit local memory.

A ninth aspect of the invention is the same as the first aspect of the invention.
In each unit processor of the unit processor group, the data input terminal, the data bus, the data output terminal, the address input terminal, the delay device, and the address output terminal are multiplexed. Is characterized by.

In a tenth aspect based on the fourth aspect, in each unit processor of the unit processor group, the arithmetic control signal input terminal, the second delay device and the arithmetic control signal output terminal are provided. It is characterized by being multiplexed.

[0015]

The present invention focuses on the fact that in image processing, the shape of the arrangement of pixel data required by each unit processor is common, and that the timing at which each unit processor requires pixel data is different. The address generator is installed only in the control unit, and the address and other control signals are delayed and supplied to each unit processor according to the timing shift. This makes it possible to correctly supply the pixel data required by each unit processor with the minimum necessary control means.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. The SIMD processor is composed of a unit processor group 5 and a control unit 6.

In this unit processor group 5, the number N of unit processors is 4, and the arithmetic unit 11 is a selector (SEL) 11
d, an arithmetic and logic unit (ALU) 11a, an adder 11b and a register (REG) 11c, and the unit processor local memory unit 12 includes a unit processor local memory core (PEM) 12a and a selector (SEL) 1.
2b shows the case of being composed of

The control unit 6 includes a control unit local memory (CU).
M) 25 and the first address generator (GUAGU) 26
And a second address generator (PEAGU) 27 and a timing signal generator (TG) 28.

In FIG. 1, 1, 2, 3, and 4 are unit processors, 13 is a data input terminal, 14 is a data output terminal, 15 is a data bus, 16 is an address input terminal, and 17
Is an address output terminal, 18 is a first delay device, 19 is an operation control signal input terminal, 20 is an operation control signal output terminal, 21
Is a second delay device, 22 is a second data input terminal, 23 is a second data output terminal, and 24 is a second data bus.

Pattern matching, which is one of image processing, will be described as an example. Generally, pattern matching is a process of searching for an image of the same size that is most similar to a certain image from images that are larger than that. Figure 2
FIG. 2A and FIG. 2B are diagrams for explaining the processing content of pattern matching in this embodiment. In the following description, an image having a size of 4 pixels × 4 pixels will be referred to as a block. According to the pattern matching of the present embodiment, the block most similar to the target block 100 is searched for in the reference image 101 having a size of 11 pixels × 11 pixels larger than that (a size here is an example). It is a thing.

The following formula is used as an index (difference) of the difference between the two images.

[0023]

[Equation 1]

In the above equation, P ₀ (i, j) is defined as the upper left pixel of the block of interest 100 (0, 0).
Indicates the luminance value of the i-th pixel in the right direction and the j-th pixel in the downward direction, and P
₁ (x + i, y + j) is, in the reference image 101, the pixel at the upper left of the reference image 101 at the x + i-th position in the right direction and the y + j in the downward direction
The luminance value of the th pixel is shown. That is, D (x, y) is equal to each of the 16 pixel values in the target block 100 and the reference image 10
The upper left pixel in 1 is the accumulated value of the absolute difference between each pixel value of the block at the position (x, y), and the smaller this value, the more the block at the position (x, y) It can be said that it is similar to the block of interest 100. Also (x, y)
Since the possible combinations of (0, 0) to (7, 7) are, the number of blocks in the reference image 101 is 64.

Each of the 16 pixel values in the block of interest 100 is a unit processor of the first unit processor 1, the second unit processor 2, the third unit processor 3, and the fourth unit processor 4 of FIG. It is assumed that the data is stored in the local memory core 12a at an address equal to the number of each pixel shown in FIG. Similarly, reference image 101
Each pixel value of 1 is stored in the control unit local memory 25 of the control unit 6 of FIG. 1 at an address equal to the number of each pixel shown in FIG. 2B.

In order to process these pixel values, processing is assigned to four unit processors as follows.
The first unit processor 1 uses the block having the pixel number 0 in the reference image 101 as the upper left corner and the target block 100.
Then, the equation (1) is calculated. Similarly, the second unit processor 2, the third unit processor 3 and the fourth unit processor 4 have pixel numbers 1 and 2 respectively.
Then, the equation (1) is calculated for the block having the pixel number 3 as the upper left corner and the target block 100.

The basic operation of the control section 6 is that the instruction word sequence stored in the instruction memory is sequentially read, a control signal is generated, and the control signal is supplied to the unit processor group 5 and the control section 6 itself. The so-called stored program method is used.

First, of the reference images 101 stored in the control unit local memory 25, the first unit processor 1,
The operation of reading the pixel value of the partial reference image 101a to which the processing is assigned to the second unit processor 2, the third unit processor 3, and the fourth unit processor 4 will be described. Therefore, the first address generator 26 uses the addresses of the pixels of the partial reference pixel 101a (in the case of the present embodiment,
As mentioned above, each address is equal to the pixel number),
One pixel is generated in one cycle. That is, it is in the order indicated by the arrow in FIG. The read enable signal is also the first
Address generator 26.

In order to generate such an address,
Repeat adding 6 to the address 6 times, then 5
Is added (since pixel 6 is moved to pixel 11), and 1 is added again, which is repeated 6 times. The same operation is repeated to generate the addresses up to the pixel 39. A flow chart of this address generation is shown in FIG.

In FIG. 3, ADRS is a variable that holds an address, DISP1 and DISP2 are variables that hold the added value of each address, and CNT1 and CNT2 are variables that hold the upper limit of the number of times in the horizontal and vertical directions, respectively. . Therefore, the configuration of the first address generator 26 includes registers corresponding to the above variables, and sets appropriate values in these registers before the first address generator 26 generates an address. It is necessary to describe the instruction word for doing in the instruction word sequence. It is assumed that the actual address generation is autonomously executed by the first address generator 26 according to the set register contents, triggered by the issuance of an instruction word instructing the start of address generation.

As an address generator which performs such an operation, for example, Goto et al., "Control system in ultra-high speed video signal processor (S-VSP)", IEICE Tech.
D91-101, PP. 23-29 (1991).

Each pixel of the partial reference image 101a read out as described above is supplied to the data input terminal 13 of the first unit processor 1 one pixel in one cycle (connected to the data input terminal 13). The selector 11d in the arithmetic unit 11 is set so as to select the signal of the data input terminal 13). The temporal flow of this operation is shown in the stage of the first address generator 26 in FIG. Each number is an address of each pixel generated by the first address generator 26.

Next, the read operation of the block of interest 100 of FIG. 2A stored in the unit processor local memory core 12a in the first unit processor 1 will be described.

In this embodiment, the address generation for the unit processor local memory core 12a is simple sequential from pixel 0 to pixel 15 as shown in FIG. 2 (a). Therefore, a simple increment counter is sufficient for the second address generator 27. However, if versatility is required, an address generator having the same configuration as the first address generator 26 is desirable. Sequential address generation is also possible with the configuration of the first address generator 26. In any case, like the first address generator 26, the second address generator 27 also executes autonomous address generation by using an instruction word instructing the start of address generation as a trigger, and also generates a read enable signal. It shall be.

By starting the address generation of the second address generator 27 at the same time as that of the first address generator 26 (it is necessary to provide both with an instruction word capable of instructing the start of address generation at the same time). Each of the pixels 0 to 3 in the target block 100 of 2 (a) is shown in FIG.
The partial reference image 101a of (b) is supplied to the arithmetic logic unit 11a of the first unit processor 1 in synchronization with each of the pixels 0 to 3. It is assumed that the arithmetic and logic unit 11a is preset to output the absolute difference value for its two inputs (in order to perform pattern matching as will be described later, the two inputs are compared in magnitude). As an arithmetic and logic unit, a unit that can selectively execute a plurality of operations such as addition and subtraction, logical sum, and logical product in addition to the absolute difference value by a control signal is widely used. The arithmetic logic unit 11a of the embodiment is also the same, and here, it is controlled to execute the absolute difference value by the control signal from the control unit 6). The above time situation,
It is shown in the stage of the first unit processor 1 in association with the generated address of the first address generator 26 of FIG. 4 already described. The numbers 0, 1, 2, and 3 are the addresses of pixel 0, pixel 1, pixel 2, and pixel 3 generated by the second address generator 27 (referred to as the "first unit processor" stage). This is because the output of the second address generator 27 is directly input to the first unit processor without delay as shown in FIG. 1).

However, the pixel 4 of the partial reference image 101a read in the next cycle is the first unit processor 1
It is not a pixel that is assigned to be processed, so it must not be used in the operation.
The same applies to the subsequent pixels 5 and 6.

Therefore, as shown in FIG. 4, the address generation of the second address generator 27 is stopped during the period of these three cycles (broken line portion). Address generation is restarted 4 cycles after the pixel 11 of the partial reference image 101a is read, pixels 4, pixel 5, pixel 6, and pixel 7 of the target block 100 are read, and the subsequent 3 cycles are stopped again. By repeating the same operation thereafter, in the first unit processor 1, the target block 10 in the unit processor local memory core 12a
Each pixel of 0 is supplied to the arithmetic and logic operation unit 11a in synchronization with the corresponding pixel of the partial reference image 101a.

In order to realize such an operation, a timing signal generator 28 is provided in the control unit 6 and a signal as shown in the stage of the timing signal generator 28 of FIG. 4 is generated. The period marked "ON" is the address generation period,
The period described as "OFF" is the address generation suspension period. The address generation of the second address generator 27 can be stopped by a method in which the logical product of this signal and the operation clock is used as the operation clock supplied to the second address generator 27.

FIG. 5 shows a flowchart of the operation of the timing signal generator 28. CNT1 = 4, CNT2 = 3
For CNT3 = 4, the period of "ON" is 4 cycles,
"OFF" period is 3 cycles, and "ON" and "OF"
It is set to repeat F "4 times. Variable O
UTPUT represents the output signal. The period in which the variable DUMMY1 changes from 0 to 3 (the period smaller than CNT1), O
UTPUT = 1, indicating that the period is “ON”. The period during which the variable DUMMY2 changes from 0 to 2 (C
(A period smaller than NT2), OUTPUT = 0, indicating that the period is “OFF”. And the variable DUM
The above is repeated for a period of MY3 from 0 to 3 (a period smaller than CNT3).

Next, the arithmetic unit 1 of the first unit processor 1
Pay attention to 1. As described above, the partial reference image 101a
While the second address generator 27 stops the address generation during the period in which the unnecessary pixels are read out, it is physically considered that the unit processor local memory core 12a outputs some value. Further, the arithmetic logic operation unit 11a performs an operation with this value as an input, and the result is accumulated by the following adder 11b and register 11c. Since this operation is an unnecessary operation, its execution must be stopped. Therefore, as the register 11c, a type capable of controlling write enable / disable is used, and the output signal of the timing signal generator 28 is registered via the operation control signal input terminal 19 as shown in FIG. 11c, and enable / disable control is performed. That is, during the period in which the second address generator 27 generates an address, the writing in the register 11c is also enabled, and during the period in which the second address generator 27 stops the address generation, the writing in the register 11c is also disabled.

As described above, in the first unit processor 1, the target block 100 of FIG. 2A and the target block 100 of FIG.
It is possible to calculate the equation (1) which is the degree of difference with the block in which the pixel 0 of is the upper left. However, in the second unit processor 2, among the pixels of the partial reference image 101a, the pixel to be used for calculation is the control unit local memory 2
The timing of reading from 5 is delayed by one cycle as compared with the case of the first unit processor 1. Furthermore the third
In the order of the unit processor 3 and the fourth unit processor 4 of
This delay increases by one cycle.

Therefore, the first delay device 1 is provided in each unit processor.
By providing 8, the delay will be absorbed. The second delay device 21 is also provided for the enable / disable control signal of the register 11c. These delay devices are preset so as to have a delay amount of 1 cycle. As a result, the second unit processor 2, the third unit processor 3, the fourth unit processor 4
2A, it is possible to calculate the degree of difference between the block of interest 100 of FIG. 2A and each block in which the pixel 1, pixel 2, and pixel 3 of FIG.

FIG. 4 shows the first address generator 26, the first unit processor 1, the second unit processor 2, and the third unit processor 2.
7 shows a time chart of an operation in which the unit processors 3 and 4 of FIG.

The above is the partial reference image 101 of FIG.
It is an explanation of the calculation of formula (1) for a. That is, only the four blocks having the pixel 0, the pixel 1, the pixel 2, and the pixel 3 as the upper left in the reference image 101 are targeted. Since 64 blocks exist in the reference image 101 as described above, it is necessary to perform calculations for the remaining 60 blocks.

The block of interest 100 does not change, and only the partial reference image 101a changes. That is, the calculation for the four blocks having the pixel 4, pixel 5, pixel 6, and pixel 7 in the upper left of FIG.
It will be newly assigned to the second unit processor 2, the third unit processor 3, and the fourth unit processor 4.
That is, the partial reference image 102 shown in FIG. 6 is read from the control unit local memory 25 by the address generation of the first address generator 26. The state of the address generation is shown in FIG. 2 except that the initial value of the address is 4.
It is similar to (c). In other words, before the address is generated,
It is necessary to execute an instruction word that sets the initial value of the address to 4. The subsequent operation is similar to that of the case of the partial reference image 101a of FIG.

After that, by changing the setting of the initial address value of the first address generator 26, the position of the partial reference image to be read is shifted, whereby the reference image 101
The whole can be used as a processing target. This is because the size of the partial reference image is constant at 7 pixels horizontally by 4 pixels vertically, and only the position at the upper left of the partial reference image sequentially moves to the pixels surrounded by the circle in FIG. 7. From this figure, the partial reference image is the reference image 1
There are 16 in 01, and each partial reference image is assigned to and processed by the first unit processor 1, the second unit processor 2, the third unit processor 3, and the fourth unit processor 4. Therefore, each unit processor processes 16 blocks in the reference image 101 in total.

The operation described above is the calculation of the dissimilarity (value of equation (1)) over the entire reference image 101. In addition, various initial settings prior to the execution of this calculation, and the process of finding the minimum value of the equation (1) as described above are necessary.

First, in the initial value setting, the following command words are executed. An instruction word for register setting that determines each operation of the first address generator 26, the timing signal generator 28, and the second address generator 27 (in the case of the first address generator 26, initial address setting, vertical and horizontal Address addition value, vertical / horizontal count value), and an instruction word for setting the arithmetic logical operation value 11a to execute the difference absolute value operation (or this time, every time a cycle in which the difference absolute value operation is required,
A method of supplying a control signal may be considered), and the selector 11d and the selector 12b are respectively connected to the data input terminal 13
Side, register 11c side is set to select an instruction word (similarly to the above, it is possible to supply a control signal appropriately every required cycle), and register 11c is set to 0 (clear). It is a command word.

Finding the block most similar to the target block 100 means that the reference image 101 has 64 blocks in total.
Finding the minimum value among the dissimilarities. This is done by each unit processor finding the minimum value among the 16 differences calculated by itself, and finally finding the minimum value among the minimum values found by these four unit processors. . Therefore, it is necessary to secure a variable area for storing the minimum value of the difference degree at the same address of each unit processor local memory core 12a. Specifically, as an initial setting, an instruction word that stores the largest representable value at that address is executed.

In addition to the minimum value, it is necessary to store the information corresponding to x and y in the equation (1), that is, the position information of each block in the reference image 101, and the variable area for the same as the minimum value is secured. . Since the position of the partial reference image and the position of the block handled by each unit processor have a one-to-one correspondence, the initial address value of the first address generator 26 is supplied to each unit processor and stored as position information. Method is possible.

Further, in order to detect the minimum value of the dissimilarity of each unit processor, each unit processor
Each time the calculation of the dissimilarity between the block of interest 100 and the block assigned to itself in the partial reference image is completed, the minimum dissimilarity at that time and the latest dissimilarity just obtained If the latter is smaller, it is stored as a new minimum value, and if not, the minimum value is left unchanged. At that time, the selector 11
Both d and the selector 12b are selected on the register 11c side,
The arithmetic operation of the arithmetic logical operation unit 11a is subtracted, the minimum value at that time stored in the unit processor local memory core 12a is input to the right input of the arithmetic logical operation unit 11a, and the left input is just now. Enter the calculated dissimilarity. Then, depending on whether the subtraction result is positive or negative, a process of storing the latter in the storage area of the minimum value (update of the minimum value) or not doing anything is selected.

The address for designating the storage area is described in the instruction word as it is, and is supplied to the unit processor local memory core 12a through the second address generator 27, or the second address generator 27. There are several possible methods such as providing another address signal line and supplying. At the same time as this address signal, a read / write enable signal is also supplied to each unit processor. Each unit processor controls the supply of the write enable signal to the unit processor local memory core 12a depending on whether the subtraction result is positive or negative, thereby making it possible to select the minimum value update / no update.

Regarding the position information of the block in the reference image 101 handled by each unit processor, after the processing of updating / not updating the minimum value of the dissimilarity, the first one used for reading the partial reference image at that time point. Address generator 26
It is possible to supply the address initial value of 1 to each unit processor from the control unit 6 and to perform the update / no update process in each unit processor in the same manner as the minimum difference value.

After that, the processing of clearing the register 11c and restoring the selections of the selector 11d and the selector 12b are performed, and the difference degree is calculated for the next partial reference image. Thereafter, this process is repeated, and each unit processor detects the minimum value of the dissimilarity over the entire reference image 101.

The following two methods are conceivable as the method of supplying the control signal required for the minimum value detection and the processing of the block position information in each of the above unit processors. First
Is the same as the address of the second address generator 27 and the signal of the timing signal generator 28.
8. When the first unit processor 1 completes the calculation of the dissimilarity by giving each unit processor the same delay as that of the second delay device 21, the control unit 6 causes the first unit processor 1
It is a method to supply only to. A second method is a method in which the control unit 6 simultaneously supplies the control signals necessary for minimum value detection processing to the four unit processors when the fourth unit processor 4 completes the calculation of the dissimilarity. Is.

By the above method, when each unit processor completes the detection of the minimum value and the block position information over the entire reference image 101, the information held by each unit processor together with the number of each unit processor is used as a second value. Collected in the control unit 6 via the data bus 24 (not shown in the figure, but by feeding back the second data output terminal 23 of the fourth unit processor 4 to the control unit 6),
It is possible to find the minimum value of the dissimilarity among them, and then find x and y based on the position information of the block corresponding to this and the number of the unit processor.

The following processing is another example of pattern matching. As shown in FIG. 8, as a method of taking blocks in the reference image, a block having a pixel at every other pixel in the vertical and horizontal directions as an upper left pixel as shown by a solid circle is taken, and pattern matching between these and the target block is performed. First. As a result, it is assumed that the pixel X is the most similar, and the 8
There is a two-step method in which pattern matching is performed again for a block in which each pixel (pixel a to pixel h) is the upper left pixel. These are methods for reducing the amount of calculation.

This method can be processed as follows by the feature that the delay amount of the delay device of each unit processor can be set independently according to the second and fifth inventions. In this case, it is assumed that eight unit processors are provided, and each block in which the pixel a to the pixel h are located at the upper left is processed by the first unit processor to the eighth unit processor.

At the first stage, in order for each unit processor to properly capture each block in the reference image, the delay amounts of the first delay device 18 and the second delay device 21 must be two cycles. is there. In the second stage, in order to capture the eight pixels of FIG. 8, the delay between the pixel a, the pixel b, and the pixel c, that is, the delay of the first unit processor and the second unit processor is one cycle, The delay between the pixel c and the pixel d, that is, the delay of the third unit processor is set to be 9 cycles (when the reference image is stored as shown in FIG. 11 cycles for one pixel, -2 cycles for 2 pixels to the left), pixel d,
The delay between the pixels e, that is, the delay of the fourth unit processor is 2
The number of cycles is set, the delay between the pixel c and the pixel f is set to 9 cycles again, and the delay between the pixel f, the pixel g, and the pixel h is set to one cycle again.

As a result of calculating the dissimilarity from the pixel a to the pixel h by setting the above delay amount and holding the dissimilarity of the pixel X in the first stage and the accompanying information, a total of 9 differences are stored. By finding the minimum value from the degrees, the final value and the position of the block can be obtained.

Further, in the embodiment shown in FIG. 1, the arithmetic unit 11 includes an arithmetic logic operation unit 11a, an adder 11d, and a register 11.
Although only c is mounted, if a multiplier is mounted and the multiplication result is accumulated by the adder 11b and the register 11c to form a product-sum calculator, filter processing is also possible.

[0062]

As described above, the SI according to the present invention is
In image processing, the MD processor often performs rectangular access to the pixel data in the memory, as in the pattern matching described in the embodiments. Address generators that enable such access include counters,
Since it is necessary to provide a register, an adder, etc., the amount of hardware becomes large. According to the present invention, such an address generator is not mounted in the unit processor but mounted only in the control unit, so that it is possible to access the pixel data necessary for image processing. Moreover, what kind of address generation pattern (size and position of rectangle, etc.) should be set may be considered only for the first unit processor. The subsequent unit processors need only consider that the same operation as that of the first unit processor is executed with a delay, so that the application program can be easily developed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining address generation necessary for pattern matching in the embodiment.

FIG. 3 is a diagram showing a flowchart of the operation of the first address generator 26.

FIG. 4 is a diagram showing a time chart of the operation in the embodiment of the SIMD processor of the present invention.

FIG. 5 is a diagram showing a flowchart of the operation of the timing signal generator 28.

FIG. 6 is a diagram for explaining address generation necessary for pattern matching in the embodiment.

FIG. 7 is a diagram for explaining address generation necessary for pattern matching in the embodiment.

FIG. 8 is a diagram for explaining a delay amount setting in a unit processor in another method of pattern matching of the embodiment.

[Explanation of symbols]

 1, 2, 3, 4 Unit processor 5 Unit processor group 6 Control unit 11 Arithmetic unit 11a Arithmetic logic arithmetic unit 11b Adder 11c Register 12 Unit processor local memory unit 12a Unit processor local memory core 13 Data input terminal 14 Data output terminal 15 Data bus 16 Address input terminal 17 Address output terminal 18 First delay device 19 Operation control signal input terminal 20 Operation control signal output terminal 21 Second delay device 22 Second data input terminal 23 Second data output terminal 24 2 data bus 25 control unit local memory 26 first address generator 27 second address generator 28 timing signal generator

Claims (10)

[Claims] 1. A SIMD processor comprising a unit processor group consisting of N (N is a natural number) unit processors, and a control unit, wherein the control unit comprises an address generator and a control unit local memory, Each unit processor of the unit processor group includes a unit processor local memory unit, an arithmetic unit, an address input terminal, an address output terminal, a delay unit, a data input terminal, a data output terminal, and a data bus, The delay device delays the signal input to the address input terminal by a predetermined period and outputs the delayed signal to the address output terminal, and the signal input to the address input terminal is addressed to the unit processor local memory unit. And the data input terminal and the data output terminal are connected by the data bus, Scan supplies the data to the unit processor local memory unit,
The data bus and the unit processor local memory unit supply data to the operation unit, the address generator supplies an address to the address input terminal of the first unit processor of the unit processor group, and the unit processor The address output terminal of the i-th unit processor (i is a natural number from 1 to N-1) of the group is connected to the address input terminal of the (i + 1) -th unit processor of the unit processor group, The SIM, wherein the data output terminal of the unit processor is connected to the data input terminal of the (i + 1) th unit processor.
D processor. 2. The SIMD processor according to claim 1, wherein the delay period of the delay unit of each unit processor of the unit processor group is independently determined for each unit processor. 3. The control unit includes a timing signal generator, and an output signal of the timing signal generator alternately takes a first state and a second state for each predetermined arbitrary period, An output signal of the timing signal generator is supplied to the address generator, and when the output signal of the timing signal generator is in the second state, the address generator stops address generation. The SIMD processor according to item 1. 4. Each unit processor of the unit processor group includes an operation control signal input terminal, an operation control signal output terminal, and a second delay device, and the second delay device is the operation control signal. The signal input to the input terminal is delayed by a predetermined period and output to the arithmetic control signal output terminal, the signal input to the arithmetic control signal input terminal is supplied to the arithmetic unit, and the arithmetic control signal When the signal input to the input terminal is in the second state, the operation unit stops the operation, and the timing signal generator outputs a signal to the operation control signal output terminal of the first unit processor of the unit processor group. 4. The calculation control signal output terminal of the i-th unit processor is connected to the calculation control signal input terminal of the (i + 1) -th unit processor. The placing of the SIMD processor. 5. The SI according to claim 4, wherein a delay period of the second delay device of each unit processor of the unit processor group is independently determined for each unit processor.
MD processor. 6. The SIMD processor according to claim 1, wherein in each unit processor of the unit processor group, an output of the arithmetic unit is supplied to the unit processor local memory unit. 7. Each unit processor of the unit processor group includes a second data input terminal, a second data output terminal, and a second data bus, and the second data input terminal and the second data input terminal are provided. Two data output terminals are connected by the second data bus, the arithmetic unit supplies data to the second data bus, and the second data output terminal of the unit processor of i has the ( The SIMD processor according to claim 1, wherein the SIMD processor is connected to the second data input terminal of the unit processor i + 1). 8. The SIMD processor according to claim 1, wherein the control unit includes a second address generator, and the second address generator supplies an address to the control unit local memory. 9. In each unit processor of the unit processor group, the data input terminal, the data bus,
The SIMD processor according to claim 1, wherein the data output terminal, the address input terminal, the delay device, and the address output terminal are multiplexed. 10. In each unit processor of the unit processor group, the operation control signal input terminal, the second delay device, and the operation control signal output terminal are multiplexed. Item 4. The SIMD processor according to Item 4.