JP2001229138A - Device and method for image processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for image processing which enable a processor to perform different operation while a coprocessor is issuing an instruction code and to shorten an image processing time. SOLUTION: Instructions and data which are used by the processor 31 and coprocessor 38 and instructions and data which are read in directly by the coprocessor 31 are held in a memory 37. The processor 31 performs a specific processing for a given instruction which is an instruction to be executed by the coprocessor 38, and outputs the result, but it sets a direct read-in flag when the given instruction is an instruction to be read in directly by the coprocessor 38. Where the direct read-in flag is not set, the instruction outputted from the processor 31 is supplied to the coprocessor 38, but where the direct read-in flag is set, a directly read-in instruction in the memory 38 is supplied directly to the coprocessor 38.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method applied to, for example, a digital processing system.

[0002]

2. Description of the Related Art Image data has a larger amount of information than other data such as audio data, and requires many processes at once. Then, in the image signal processing, the same arithmetic processing is often performed on all pixels constituting one image. In order to execute the same arithmetic processing at high speed on many data, SIMD (Single Instruction Multiple Data S
A tream (single instruction multiple data) type architecture has been proposed, and is used not only in image signal processing but also in a wide range of fields.

[0003] The SIMD type architecture has a configuration in which a necessary number of arithmetic units are arranged, and each arithmetic unit operates according to the same instruction. Therefore, if different data is given to each arithmetic unit, an arithmetic result for each data can be obtained at once.

As an application of the SIMD type processing apparatus to image processing, for example, “Kurokawa et al.,” 5.4 GOPS Linear
Array Architecture DSP for Video-Format Conversio
n ″, IEEE 1996 / Feb. ISSCC, FP 15.7. ”is known.

FIG. 7 is a block diagram showing a configuration example of a SIMD type image processor. The SIMD image processor 10 includes an input pointer 11, an input SAM
(Serial access memory) unit 12, data memory unit 1
3, an ALU array unit 14, an output SAM unit 15, an output pointer 16, and a program control unit 17.

In the SIMD type image processor 10, an input SAM unit 12, a data memory unit 13, an ALU
The array unit 14 and the output SAM unit 15 constitute a group of element processors that are parallelized in a large number in a linear array (linear array) type as a whole. These multiple element processors PE are controlled in conjunction (SIMD control) by a single common instruction code in the program control unit 17. The program control unit 17 includes a program memory and a sequence control circuit for advancing the program. The program control unit 17 generates various control signals for each part connected according to a program written in advance in the program memory. Control the part.

Image processing by the SIMD type image processor 10 shown in FIG. 7 is performed in the following procedure. Input data for one horizontal scanning line is taken into the input SAM unit 12 during the horizontal scanning active period, and the data is transferred from the input SAM unit 12 to the data memory unit 13 during the horizontal scanning unit blanking period. In the data memory unit 13 and the ALU array unit 14, arithmetic processing is performed according to a program. A
After the completion of the arithmetic processing in the LU array unit 14, the processing result is transferred to the output SAM unit 15, and data for one horizontal scanning line is output from the output SAM unit 15 during the horizontal scanning active period. During the above processing, all the units are operating in parallel.

In order to perform image processing with a parallel processor in which such element processor groups are arranged in an array, a communication function with the left and right element processors is indispensable, especially in the case of SIMD control. This left / right communication (hereinafter, referred to as LR communication or LR) function enables processing of left and right pixels such as a filter operation and an interpolation operation.

Meanwhile, the SIMD type processing device for performing image processing requires complicated processing, and therefore requires issuing a large number of instruction codes, and the control thereof is becoming more complicated year by year. Therefore, a processor has been used to efficiently and automatically issue an instruction code to a program control unit. This processor is a general processor such as a general-purpose CPU, and the SIMD type image processing apparatus is called a coprocessor for this processor.

[0010] The control signal generated by the program control section in the coprocessor is realized by decoding an instruction code obtained from the processor. Information such as a parameter value of an instruction code for control and a type of operation is processed by a processor and supplied to a coprocessor. For example, when the same operation instruction is continued by the instruction code, the coefficient can be changed only by changing the parameter, and thus there is an advantage that the used area of the data memory can be reduced.

In order for an instruction code used in a coprocessor to be processed by the processor, it must be stored in a data area of a memory (data storage device). Since the instruction code of the coprocessor is also stored in the data memory of the processor, the processor and the coprocessor need to share the memory. This configuration is called a single memory configuration.
The processor and the coprocessor have a subordinate relationship. In order to supply an instruction code (data for the processor) to the coprocessor, the processor needs to acquire data and supply the data to the coprocessor.

Further, some instruction codes of the coprocessor do not need to be processed by the processor, and some are supplied to the coprocessor as they are. Instructions that do not require processing in the processor are read once by the processor and supplied to the coprocessor as it is. In this case, if issuance of a coprocessor instruction that does not require processing continues, the processor will be used only to read data from memory and supply the data to the coprocessor. The processor must wait until the supply of instructions to the coprocessor is completed, even if there is a time-consuming coefficient calculation.

FIG. 8 is a block diagram showing a system configuration example of a conventional image processing apparatus using a processor and a coprocessor. This image processing device 20 includes a processor 21, a coprocessor 22, and a memory 23, as shown in FIG.

In FIG. 8, input data DTIN to a coprocessor 22 which is a SIMD type image processing apparatus is image data on which image processing is actually performed. The output image data DTOUT) is the processed image data.
The format of the data is three primary colors R (red), G (green), and B represented by a computer display.
There is a television signal represented by an RGB format based on (blue) or NTSC, but is not limited to a specific format.

The processor 21 controls the memory 23
A data read request (read request) and an address at which data is stored are supplied. When data is to be held, a data write request (write request), an address for storing data, and data are supplied. Upon receiving the read request, the memory 23 returns the data stored at the specified address to the processor. At this time, an enable signal indicating that data has been output is returned to the processor 21. In the case of a write request, data is stored at a specified address. The processor 21 is a memory 23
If necessary, it operates on the data received from it to generate an instruction code for the coprocessor 22. The generated instruction code is supplied to the coprocessor 22. Coprocessor 22
Performs image processing on the input data DTIN according to the supplied instruction code. The coprocessor 22 repeatedly executes the instructions of the processor 21 and outputs the output data DTOUT when all the instructions have been executed.

Next, the main process in the image processing apparatus of FIG. 8 will be described with reference to the flowchart of FIG.

First, in step ST1, input image data DTIN is read into the coprocessor 22. Next, in step ST2, an instruction to be executed by the processor 21 is read. If the read instruction is not an instruction for issuing an instruction code to the coprocessor 22 (single instruction code issuance instruction) in step ST3, the processor 21 proceeds to the process of step ST7.
Note that issuing a single instruction code means supplying one instruction code in the data stored in the memory 23 to the coprocessor 22 through the processor 21.

In step ST3, the coprocessor 2
If it is determined that the instruction is a single instruction code issuance instruction to the second instruction code, the processor 21 acquires data from the memory 23 in step ST4. This data becomes the instruction code of the coprocessor 22 as it is. Next, in step ST5, the processor 21 supplies the obtained data to the coprocessor 22. Then, step ST6
In, the program counter, which is the counter of the instruction of the processor 21, is incremented, and the process returns to step ST2.

If it is determined in step ST7 that the read instruction is an end instruction of the processor 21, the process proceeds to step ST18. On the other hand, if it is determined in step ST7 that the instruction read is not the end instruction of the processor 21, the processor 21 executes the instruction read in step ST8. And step S
At T9, the program counter which is the counter of the instruction of the processor 21 is incremented, and the program proceeds to step ST9.
It returns to the process of 2. In step ST10, it is confirmed that the operation of the coprocessor 22 has been completed, and the image data is output.

FIG. 10 is a diagram showing an example of the execution order of instructions of the conventional image processing apparatus 10. As shown in FIG. 10, in the conventional image processing apparatus 10, instructions 1 to 7 and copro instructions 1 to 5 are sequentially performed in a predetermined order.

[0021]

As described above, the instruction code of the coprocessor 22 is issued by the processor 21. The instruction code can be generated using a result calculated by the processor 21. For example, coprocessor 2
The coefficient of the operation performed in 1 can be calculated by the processor and supplied to the coprocessor 22 as a constant value.

By the way, it is not necessary that all the instruction codes are calculated by the processor 21 and then supplied to the coprocessor 22. The data stored in the memory 23 may be supplied to the coprocessor 22 as it is. In a program having a large number of such instruction codes, the processor 21 repeatedly executes the instruction for issuing the instruction from the coprocessor 22, so that there is a problem that other arithmetic processing cannot be executed. For example, when it is necessary to calculate a coefficient of the coprocessor 22 by performing a time-consuming operation, the operation cannot be performed while the instruction is issued to the coprocessor 22, so that the processing speed of the entire image processing is reduced. Problem arises.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus and an image processing apparatus capable of performing another operation by a processor while an instruction code of a coprocessor is being issued, thereby shortening an image processing time. It is to provide a processing method.

[0024]

In order to achieve the above object, the present invention provides a coprocessor for performing image processing based on instructions supplied to input image data and outputting the same, If the instruction is an instruction to be executed by the coprocessor, a predetermined process for the instruction is performed and output. If the given instruction is an instruction to be read directly by the coprocessor, a direct read flag setting request is issued. An issuing processor, an access determination circuit that sets a direct reading flag when the direct reading flag setting request is received, an instruction and data used in the processor and the coprocessor, and an instruction and data read directly by the coprocessor. When an access request is received from the processor, instructions and data in the memory are stored in the memory. If the direct read flag is not set by the access determination circuit, the instruction output from the processor is supplied to the coprocessor, and if the direct read flag is set, Has selection means for supplying the instructions and data for directly reading the memory from the memory to the coprocessor.

In the present invention, there is provided an access requesting means for issuing an access request for the memory to the selecting means when the direct reading flag is set by the access determining circuit. The selection means is
When the access request is issued by the access request unit, the direct read instruction and data of the memory are supplied to the coprocessor.

In the present invention, the access request means receives the direct read instruction read from the memory by the selection means, decodes the instruction, and sets an end flag if the result of the decoding is an end instruction. When the end flag is set, the access determination circuit cancels the setting of the direct read flag.

[0027] In the present invention, when the access request by the processor and the access request by the access request unit are received simultaneously, the selecting unit gives priority to the access request by the processor.

According to the present invention, the coprocessor includes:
A plurality of element processors arranged one-dimensionally in parallel and performing predetermined arithmetic processing on image data supplied according to a control code, and a control code for controlling the plurality of element programs in conjunction with each other based on an application program. And a program control unit for generating.

In the present invention, each of the element processors performs an operation with an input serial access memory unit having a plurality of means for inputting image data, a data memory unit holding input data and operation results. It includes a part of an ALU array unit and an output serial access memory unit provided with a plurality of means for acquiring output image data.

Further, the present invention uses a coprocessor for performing image processing and outputting based on instructions supplied to input image data, and a processor for supplying and controlling instructions executed by the coprocessor. In the image processing method, the instructions and data used in the processor and the coprocessor, and the instructions and data to be read directly by the coprocessor are stored in a memory, and the given instruction is executed by the processor. If the instruction is an instruction to be executed by the coprocessor, a predetermined process for the instruction is performed and output.If the instruction is an instruction to be read directly by the coprocessor, a flag for direct reading is set. If the read flag is not set, the instruction output from the processor is supplied to the coprocessor, and the instruction is read directly. If the write flag is set, the direct read instruction of the memory and supplies data directly to the coprocessor.

According to the present invention, in a processor, when a given instruction is an instruction to be executed by a coprocessor, predetermined processing is performed on the instruction and output to the selection means. On the other hand, if the given instruction is an instruction that is directly read by the coprocessor, the direct read flag is set by the access determination circuit. If the direct read flag is not set, the instruction output from the processor is supplied to the coprocessor. If the direct read flag is set, the direct read instruction and data in the memory are copied. Supplied directly to the processor. Therefore, another operation can be performed by the processor while the coprocessor issues an instruction, so that many operations can be performed by the processor within the same processing time. Since the instruction can be issued without passing through the processor, the instruction can be issued to the coprocessor quickly. Since the number of instructions issued to the coprocessor increases, many image processing operations can be realized. As a result, the image processing time can be reduced.

[0032]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

The image processing apparatus 30 includes a processor 31
It comprises an access determination circuit 32, an instruction selector 33, an address decoder 34, an end flag generation circuit 35, a memory selector 36, a memory 37, and a coprocessor 38. The address decoder 34 and the end flag generation circuit 35 constitute an access request unit, and the instruction selector 33 and the memory selector 36 constitute a selection unit.

The processor 31 basically controls the processing realized by the coprocessor 38. Specifically, the processor 31 issues an instruction code of the coprocessor 38 for processing image data. Processor 3
1 issues a read request, data and address to the memory selector 36. Then, at the time of reading, the processor 31 receives the data stored in the memory 37 from the memory selector 36. When the received data is the instruction code of the coprocessor 38, the processor 31 determines a coefficient operation of the instruction code, performs an interrupt process, and supplies the instruction code to the instruction selector 33.

For example, assuming that the variable of the processor 31 is x and the data memory of the coprocessor 38 is Mem, for example, an instruction to add the variable x and the content at address 4 of the data memory of the coprocessor 38 is , As follows: Mem [3] = Addi (Mem [4], x)

The memory 27 has the following information. COP (Mem [3] = Addi (Mem [4],
x)) Here, COP indicates an instruction issued to the coprocessor 38.

The processor 31 determines from the COP that the instruction is an instruction to be issued to the coprocessor 38, and
Is supplied to the instruction selector 33 as an instruction code. For example, when the variable x is 3, the instruction is supplied to the instruction selector 33 in the following form. Mem [3] = Addi (Mem [4], 3)

At this time, the processor 31 outputs a processor enable signal to the instruction selector 33 at the same time.
Further, the instruction code of the coprocessor 38 is directly stored in the memory 37.
From the processor 31 to the coprocessor 38
, The processor 31 issues a request to the access determination circuit 32 to set (activate) an access flag for direct read (a flag for direct read).

An instruction to be read directly from the memory 37 into the coprocessor 38 is represented, for example, by the following format. COPREAD (Address) Here, Address is the start address (start address) of the memory 37 in which the instruction code to be issued to the coprocessor 38 is stored.

The processor 31 sends a request for setting an access flag and a start address to the access determination circuit 32 using COPREAD as an identifier. While the access flag is on, the processor 31
It is assumed that an instruction other than the instruction code issuance to the processor 8, ie, an instruction that can be processed in the processor 31, can be executed. Further, the processor 31 cannot supply an instruction to the instruction selector 33 when the access flag is set. When supplying an instruction code to the instruction selector 33 or issuing an access request to the access determination circuit 32 when the access flag is raised, the processor 31 stops until the access flag is lowered.

The access decision circuit 32 is
When a more direct read request is received, an access flag is set. Then, the access determination circuit 32 notifies the instruction selector 33 and the address decoder 34 that the access flag is set, and supplies the start address to the address decoder 34. The access determination circuit 32
When the end flag is received from the address decoder 34, the access flag is lowered. The access flag is a flag indicating that continuous instruction code issuance from the memory 37 to the coprocessor 38 is being executed.

The instruction selector 33 includes the access determination circuit 3
2 when the access flag (direct read flag) is set, the data is received from the memory selector 36. When the access flag is lowered, the processor 3
Receive data from 1. Also, the instruction selector 33
If the access flag is not set, the processor 31
When the access flag is set, the instruction is supplied to the coprocessor 38 only when the enable signal of the memory selector 36 is set.

The address decoder 34 is a selector for generating an address of data stored in the memory 37. When a new instruction code continuous issuance request is issued from the processor 31 to the access determination circuit 32, the address decoder 34 supplies the new address received from the access determination circuit 32 to the end flag generation circuit 35. If the access flag has already been raised and the end flag has not been raised, the address decoder 34 increments the address and issues a request for the next data. The incremented address is supplied to the end flag generation circuit 35. Similarly, the address decoder 34 passes the access flag to the end flag generation circuit 35.

The end flag generation circuit 35 supplies the access flag and the address obtained from the address decoder 34 to the memory selector 36. End flag generation circuit 3
5 decodes a part of the instruction code obtained from the memory selector 36, and sets an end flag in the case of an end instruction. The end flag is supplied to the address decoder 34 and the memory selector 36. The end flag generation circuit 35
For example, when the following instruction code is obtained from the memory 37, an end flag is set. COPEND ()

The memory selector 36 receives a read, write request, data and address from the processor 31 and an access request and address from the end flag generation circuit 35, and passes the read, write request, data and address to the memory 37. The memory selector 36 determines whether the data obtained from the memory 37 is an access request from the processor 31 or an access request obtained from the end flag generation circuit 35, and returns the data and the enable signal to the destination that has received the access request. When the memory selector 36 receives requests and the like from both the processor 31 and the end flag generation circuit 35 at the same time, the memory selector 36 gives priority to the requests and the like from the processor 31. When the instruction obtained from the memory 37 is “COPEND”, the memory selector 36 determines whether the end flag generation circuit 3
5 and receives an end flag at the time of decoding. At this time, since the memory selector 36 is not an instruction realized by the coprocessor 38, no enable signal is set (not activated).

The memory 37 stores instructions and data used by the processor 31 and the coprocessor 38. When receiving a read request and an address from the memory selector 36, the memory 37 returns the value stored at the specified address to the memory selector 36. Also, the memory 37
Receives a write request, an address, and data, and writes the data to the specified address. Note that the read request of the coprocessor instruction and the read request of the processor data are not performed in the memory 37 but are separated at the memory selector 36 stage. When an instruction code is issued to the coprocessor 38 through the processor 31,
It looks like this: COP (coprocessor instruction code) On the other hand, when the memory selector 36 supplies the COP directly to the coprocessor 38, the COP does not need to be reduced, and is stored in the following form. Coprocessor instruction code

In the memory 37, instruction codes to be continuously issued for the coprocessor 38 are stored in the order shown in FIG. 2, for example. In FIG. 2, ADD, SUB, and MUL are instruction codes realized by the coprocessor 38.

The coprocessor 38 performs image processing on the input data DTIN according to the instruction code supplied by the instruction selector 33. And the coprocessor 38
The instruction supplied from the instruction selector 31 is repeatedly executed, and when the execution of all the instructions is completed, the output data DT
Output OUT.

The coprocessor 38 is constituted by, for example, an SIMD type image processor as shown in FIG.

This SIMD type image processor 380
As shown in FIG. 3, an input pointer 381, a first input SAM (serial access memory) section 382a, a second input SAM section 382b, a data memory section 383, an ALU array section 384, a first output SAM section 385a, 2-output S
It has an AM unit 385b, an output pointer 386, and a program control unit 387. In the present embodiment,
A combination of each block corresponding to one pixel is called an element processor PE. The SIMD type image processor 380 is composed of an element processor group in which element processors PE are arranged in an array in the size of an image. In this embodiment, the input SAM unit and the output SAM
Although the configuration having two units is shown, in order to realize the present invention, the number of the input SAM unit and the output SAM unit may be one or two or more. The SIMD image processor 380 may be configured by hardware or may be realized by software.

The input pointer 381 is set in the ALU array unit 3
When the write address 84 points to the input pointer 381, the input SAM unit 382a and the input SAM unit 382b are controlled in response to the operation result of the ALU array unit 384. The input SAM unit 382a and the input SAM unit 38
The input pointer for 2b control may be separately provided, or may have the same pointer address.

The input SAM unit 382a receives the input pointer 3
In accordance with the instruction 81, the image data stored in the first input frame memory 21 is input to a predetermined position, including processing such as skipping, and the data is supplied to the data memory unit 383. The input SAM unit 382b includes an input pointer 381
In accordance with the instruction, image data stored in the second input frame memory 22 is input to a predetermined position, including processing such as skipping, and the data is supplied to the data memory unit 383.

The data memory unit 383 is composed of a memory of several hundred bits per one element processor PE.
According to the control code of the program control unit 387, the input SA
It holds data from the M units 382a and 382b,
The data for the LU array unit 384 to perform an operation is ALU
It sends the result to the array unit 384 and holds the operation result of the ALU array unit 384.

The ALU array section 384 receives data from the data memory section 383, and inputs the data to the program control section 387.
Write the operation result to the address pointer specified by.
If the address pointer is the data memory unit 383, the specified address of the data memory unit 383 is
The operation result of the U array unit 384 is written. The address pointer is the input pointer 381 and the output pointer 3
If it is 86, the operation result of the ALU array unit 384 is written to the input pointer 381 and the output pointer 382.

The output SAM section 385a outputs the write address of the control code of the program control section 387 as the output SAM.
In the case of pointing to the unit 385a, the operation result of the ALU array unit 384 is input, and data is supplied to the first output frame memory 23. The output SAM section 385b outputs the write address of the control code of the program control section 387 as the output SA.
When pointing to the M section 385b, the ALU array section 384
And supplies data to the second output frame memory 24. In this embodiment, two output SAM units are provided. However, in order to explain arbitrary pixel number conversion, one output SAM unit may be provided, or two or more output SAM units may be provided. May be.

The output pointer 386 indicates that the ALU array unit 3
84 write address S384b is the output pointer 38
6, the output SAM unit 385a that receives the operation result of the ALU array unit 384 as an input, and the output SA
It controls the M section 385b. The output SAM unit 385a
And an output pointer for controlling the output SAM unit 385b, or may have the same pointer address.

The program control section 387 controls the input SAM sections 382a and 382b, the data memory section 383, the ALU array section 384, and the control code output S387 for controlling the output SAM sections 385a and 385b in accordance with a predetermined control code.
Generate

The element processor PE has the input SAM unit 38
2a, 382b, the data memory unit 383, the ALU array unit 384, and the output SAM units 385a, 385b, each of which corresponds to one pixel. The processor is constituted by a plurality of element processors. That is, in an ordinary processor, its hardware is generally a word processing processor, and performs processing in units of words. However, one element processor PE indicated by a vertically elongated range shown by hatching in FIG. , The data memory unit 13 and the output SAM unit 15 are “columns” of the memory.
And the ALU array section 14 has a 1-bit AL
U, which is essentially a circuit mainly based on full adders (full adders). Therefore, unlike an ordinary processor, it is a bit processing processor, and performs processing in units of bits. 8-bit machine or 16 which is called by ordinary CPU
A bit machine is a 1-bit machine. Since the bit processing processor has a small hardware and can realize as many parallel numbers as cannot be normally realized, in the case of an image, the parallel number of the element processor linear array is determined by the number of pixels (H) in one horizontal scanning period of the video signal. ).

Image processing by the SIMD type image processor 380 shown in FIG. 3 is performed in the following procedure. During the horizontal scanning active period, the input SAM units 382a, 382
82b, input data DTIN1 and DTIN for one horizontal scanning line.
2 during the horizontal scanning section blanking period.
The data is transferred from the M units 382a and 382b to the data memory unit 383. In the data memory unit 383 and the ALU array unit 384, arithmetic processing is performed according to a program. After the completion of the arithmetic processing in the ALU array section 384, the processing result is transferred to the output SAM sections 385a and 385b,
During the horizontal scanning active period, the output SAM unit 385a,
385b outputs data for one horizontal scanning line. During the above processing, all the units are operating in parallel.

In order to perform image processing by a parallel processor in which such element processor groups are arranged in an array, a communication function with the left and right element processors is indispensable, especially in the case of SIMD control. This left / right communication (hereinafter, referred to as LR communication or LR) function enables calculation processing of left and right pixels such as filter calculation and interpolation calculation. The communication between the element processors is called left-right communication (LR communication), which enables calculation of adjacent pixels on the left and right.

Next, the image processing apparatus 30 having the above configuration
Will be described with reference to the flowcharts of FIGS. FIG. 4 shows a main process which is a flow of the entire operation, and FIG. 5 shows a sub-process showing an operation of supplying data from a memory to a coprocessor which operates in parallel during execution of the main process.

First, in step ST101, the input image data DTIN is read into the coprocessor 31. Next, in step ST102, an instruction to be executed by the processor 31 is read. If the read instruction is not an instruction for issuing an instruction code to the coprocessor 38 (single instruction code issuing instruction) in step ST103, the processor 31 proceeds to the process of step ST107. Note that issuing a single instruction code refers to supplying one instruction code in the data stored in the memory 37 to the coprocessor 38 through the processor 31. On the other hand, issuing a continuous instruction means supplying data directly from the memory 37 to the processor without passing through the processor 31.

If it is determined in step ST103 that the instruction is a single instruction code issuance instruction to the coprocessor 382, the processor 31 issues a read request, data and address to the memory selector 36 in step ST104, The data stored in 37 is received from the memory selector 36. If the received data is the instruction code of the coprocessor 38, the processor 31 determines a coefficient operation of the instruction code, interrupt processing, and the like, and supplies the instruction code to the instruction selector 33 in step ST105. At this time, the processor 31
Outputs the processor enable signal to the instruction selector 33, and the access flag by the access determination circuit 32 is lowered. Therefore, the instruction selector 33 receives the data from the processor 31 and supplies the data to the coprocessor 38. Then, in step ST106, the program counter which is the counter of the instruction of the processor 31 is incremented, and in step ST102
Return to the processing of.

In step ST107, it is determined whether or not the instruction is a continuous issuance instruction to the coprocessor 38. If it is determined that the instruction is not a continuous issue instruction to the coprocessor 38, the process proceeds to step ST115.
If it is determined that the instruction is a continuous issuance instruction to the coprocessor 38, a subprocess is executed in step ST108. At this time, the processor 31 sets an execution flag, which is a request for setting an access flag, and supplies a start address to the access determination circuit 32. This allows
The access determination circuit 32 sets an access flag, notifies the instruction selector 33 and the address decoder 34 that the access flag is set, and supplies the start address to the address decoder 34.

The sub-process starts operation when a start command is issued in the main process. As shown in FIG. 5, in step ST1081, the coprocessor 3
8 reads data from the memory 37 via the memory selector 36 and the instruction selector 33. Then, in step 1082, the read data is decoded, and in step ST1083, the address is decoded. Here, in step ST1084, if it is an end command, an end code is issued. If the instruction is not an end instruction, the process returns to step ST1081.

When a stop signal is issued in step ST109 and the end flag generation circuit 35 generates an end flag in step ST110, the process returns to step ST102.

On the other hand, if the stop signal has not been issued in step ST109, the process proceeds to step ST1.
Then, the process proceeds to step S11. In step ST111,
The instruction to be executed is executed by the read processor 31. At this time, if the control instruction executed by the processor 31 is an instruction issued to the coprocessor 38 (single instruction code issuance instruction and continuous instruction code issuance), a stop signal is issued. Then, in step ST112, the program counter which is the counter of the instruction of the processor 31 is incremented. Then, step ST
In step 113, when an end code indicating that data has been sent from the memory 37 to the coprocessor 38 is received in the subprocess, an end flag is generated in step ST114, and the process returns to step ST102. On the other hand, if the end flag for issuing the continuous instruction code has not been generated, the process returns to step ST109.

If it is determined in step ST115 that the read instruction is not the end instruction of the processor 31, the processor 31 executes the instruction read in step ST116. And step S
In T117, the program counter, which is the counter of the instruction of the processor 31, is incremented, and the process returns to step ST102. In step ST118, it is confirmed that the operation of the coprocessor 38 has been completed, and the image data is output.

By the above-described processing, the processor 31 continuously issues instructions to the coprocessor 38, whereby it becomes possible to operate in parallel as shown in FIG.

As described above, according to the present embodiment, the instructions and data used by the processor 31 and the coprocessor 38 and the instructions and data read directly by the coprocessor 31 are held in the memory 37. In the processor 31, the given instruction is
If the given instruction is an instruction to be executed by the coprocessor 38, the instruction is read out directly by the coprocessor 38. When the flag is not set, the instruction output from the processor 31 is supplied to the coprocessor 38. When the flag for direct reading is set, the instruction and data to be directly read from the memory 37 are supplied to the coprocessor 38. Is supplied directly to the processor, so that the processor can perform another operation while the coprocessor issues an instruction, so that the processor can realize many operations within the same processing time. Since the instruction can be issued without passing through the processor, the instruction can be issued to the coprocessor quickly. Since the number of instructions issued to the coprocessor increases, many image processing operations can be realized. As a result, the image processing time can be reduced.

[0071]

As described above, according to the present invention,
Another operation can be performed by the processor while the instruction code of the coprocessor is being issued. Therefore, many operations can be realized by the processor within the same processing time. Also, since the instruction can be issued without passing through the processor, the instruction code can be issued to the coprocessor quickly. As a result, the number of instruction codes issued to the coprocessor increases, so that many image processing operations can be realized, and the image processing time can be shortened.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a diagram showing an example of holding data in a memory according to the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a coprocessor according to the present invention.

FIG. 4 is a flowchart showing a main process which is a flow of the entire operation of the image processing apparatus according to the present invention.

FIG. 5 is a flowchart showing a sub-process representing an operation of supplying data to a coprocessor from a memory which operates in parallel during execution of a main process.

FIG. 6 is a diagram illustrating an example of an execution order of instructions of the image processing apparatus according to the present invention.

FIG. 7 is a block diagram illustrating a configuration example of a SIMD type image processor.

FIG. 8 is a block diagram illustrating a system configuration example of a conventional image processing apparatus using a processor and a coprocessor.

FIG. 9 is a flowchart illustrating a main process in the image processing apparatus of FIG. 8;

FIG. 10 is a diagram illustrating an example of an execution order of instructions of a conventional image processing apparatus.

[Explanation of symbols]

Reference Signs List 30 image processing device, 31 processor, 32 access determination circuit, 33 instruction selector, 34 address decoder, 35 end flag generation circuit, 36 memory selector, 37 memory, 38 coprocessor, 380 SI
MD type image processor, 381... Input pointer, 3
82a: first input SAM unit, 382b: second input SAM
Unit, 383: data memory unit, 384: ALU array unit, 385a: first output SAM unit, 385b: second output SAM unit, 386: output pointer, 387: program control unit.

Claims (8)

[Claims] 1. A coprocessor that performs image processing based on an instruction supplied to input image data and outputs the processed image data, and when a given instruction is an instruction to be executed by the coprocessor, When a given instruction is an instruction to be read directly by the coprocessor, a processor that issues a direct read flag setting request, and a processor that issues a direct read flag setting request, An access determination circuit for setting a flag for direct reading, an instruction and data used in the processor and the coprocessor, and an instruction to directly read in the coprocessor;
A memory for holding data and, when an access request is received by the processor,
If the instructions and data of the memory are supplied to the processor, and the direct read flag is not set by the access determination circuit, the instruction output from the processor is supplied to the coprocessor, and the direct read flag is supplied. An image processing apparatus having, if set, a command to directly read the memory from the memory and selection means for supplying data to the coprocessor; 2. An access requesting means for issuing an access request for the memory to the selecting means when a direct reading flag is set by the access determining circuit, wherein the selecting means comprises: 2. The image processing apparatus according to claim 1, wherein when the access request is issued by the access request unit, the instruction and data for directly reading the memory are supplied to the coprocessor. 3. The access request means receives the direct read instruction read from the memory by the selection means, decodes the instruction, and sets an end flag if the result of the decoding is an end instruction. 3. The image processing apparatus according to claim 2, wherein the circuit cancels the setting of the direct reading flag when the end flag is set. 4. The image processing apparatus according to claim 2, wherein said selection means gives priority to an access request from said processor when an access request from said processor and an access request from said access request means are received simultaneously. 5. The image processing apparatus according to claim 3, wherein said selecting means gives priority to an access request from said processor when an access request from said processor and an access request from said access requesting means are received simultaneously. 6. The plurality of coprocessors are arranged one-dimensionally in multi-parallel, perform predetermined arithmetic processing on image data supplied in accordance with a control code, and include the plurality of coprocessors based on an application program. The image processing apparatus according to claim 1, further comprising: a program control unit that generates a control code that controls the programs in conjunction with each other. 7. Each of the element processors includes an input serial access memory unit having a plurality of means for inputting image data, a data memory unit for storing input data and operation results, and an ALU array unit for performing operations. 7. The image processing apparatus according to claim 6, including a part of an output serial access memory unit having a plurality of means for acquiring output image data. 8. An image processing method using a coprocessor for performing image processing and outputting based on instructions supplied to input image data, and a processor for supplying and controlling instructions to be executed by the coprocessor. An instruction, data, and an instruction to be read directly by the coprocessor, which are used by the processor and the coprocessor,
The data is held in a memory, and in the processor, when a given instruction is an instruction to be executed by the coprocessor, a predetermined process for the instruction is performed and output, and the given instruction is If the instruction is read directly by the coprocessor, the direct read flag is set. If the direct read flag is not set, the instruction output from the processor is supplied to the coprocessor, and the direct read flag is set. When the setting is made, an image processing method for directly supplying the command and data for directly reading the memory from the memory to the coprocessor.