JPH0992775A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0992775A
JPH0992775A JP24420495A JP24420495A JPH0992775A JP H0992775 A JPH0992775 A JP H0992775A JP 24420495 A JP24420495 A JP 24420495A JP 24420495 A JP24420495 A JP 24420495A JP H0992775 A JPH0992775 A JP H0992775A
Authority
JP
Japan
Prior art keywords
lead
semiconductor chip
lead frame
package
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24420495A
Other languages
Japanese (ja)
Other versions
JP3163961B2 (en
Inventor
Tatsuya Otaka
達也 大高
Kazuhisa Hatano
和久 幡野
Hajime Murakami
村上　　元
Takaharu Yonemoto
隆治 米本
Osamu Yoshioka
修 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP24420495A priority Critical patent/JP3163961B2/en
Publication of JPH0992775A publication Critical patent/JPH0992775A/en
Application granted granted Critical
Publication of JP3163961B2 publication Critical patent/JP3163961B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To make a package small in thickness in a CSP (Chip Scale Package) structure by which a lead frame of the same size is mounted on a semiconductor chip. SOLUTION: A lead frame 4 to be adhered to a semiconductor chip 1 is almost the same in size as the chip 1. The surface 4e of an inner lead 4a of the lead frame 4 is coined to form a coined part 5 with reduced thickness. The lead frame 4 and the end surface 1c of the chip 1 are adhered to each other with a double-faced adhesive tape 3 interposed. The coined part 5 of the inner lead 4a is connected with a bonding pad 2 of the chip 1 through a bonding wire 9. The surface 1a of the chip 1 is packaged with a mold resin 8, thereby exposing only the surface 4c of an outer lead 4b on the packaged resin surface 8a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明はリードフレームを使
用した半導体装置に係り、特にチップサイズと略同一の
サイズをもつ薄型かつ小型の半導体パッケージ構造に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a lead frame, and more particularly to a thin and small semiconductor package structure having a size substantially equal to a chip size.

【０００２】[0002]

【従来の技術】大容量のＤＲＡＭ（Dynamic Random Acc
ess Memory）では、高密度実装の要求に対応して、比較
的小さなパッケージに大形化した半導体チップを収納で
きるＬＯＣ（Lead On Chip）構造が採用されているが、
容量の増加により更にチップサイズレベルにまで小形化
されたパッケージが要求されるようになってきた。ま
た、電子機器用の半導体パッケージも、パソコン、ファ
ックス，パーソナル電話機、ＩＣカード等のサイズの縮
小に伴って、より小形化することが要求されている。し
かも、この小形化は、単にパッケージの専有する面積に
のみ求められるのではなく、パッケージの厚さ方向にも
求められている。2. Description of the Related Art A large-capacity DRAM (Dynamic Random Acc.)
ESS Memory) has adopted a LOC (Lead On Chip) structure that can accommodate a large semiconductor chip in a relatively small package in response to the demand for high-density packaging.
Due to an increase in capacity, a package that is further downsized to a chip size level has been required. Also, semiconductor packages for electronic devices are required to be further downsized as the sizes of personal computers, fax machines, personal telephones, IC cards, etc. are reduced. In addition, this miniaturization is required not only in the area occupied by the package but also in the thickness direction of the package.

【０００３】従来、これらの要請に応えるものとして、
リードの一部のみをパッケージの底面に露出させたＣＳ
Ｐ（Chip Scale Package）と呼ばれる半導体装置が提案
されている（特開平６−１３２４５３号公報）。具体的
には、図７に示すように、半導体チップ２１の配線面
（表面）２１ａに半導体チップ２１と同一サイズのリー
ドフレーム２２を端面を合わせて接着剤２３で貼り付け
る。リードフレーム２２のインナリード２２ａと半導体
チップ２１とをボンディングワイヤ２４で接続した後、
モールド樹脂２５で封止する際、半導体チップ２１の表
面側をモールド樹脂２５で封止して、モールド樹脂２５
の表面２５ａにアウタリード２２ｂの表面２２ｃを露出
させたものである。Conventionally, in response to these demands,
CS with only some of the leads exposed on the bottom of the package
A semiconductor device called P (Chip Scale Package) has been proposed (JP-A-6-132453). Specifically, as shown in FIG. 7, a lead frame 22 of the same size as the semiconductor chip 21 is attached to the wiring surface (front surface) 21 a of the semiconductor chip 21 with an adhesive 23 with its end faces aligned. After connecting the inner leads 22a of the lead frame 22 and the semiconductor chip 21 with the bonding wires 24,
When sealing with the molding resin 25, the front surface side of the semiconductor chip 21 is sealed with the molding resin 25,
The surface 22c of the outer lead 22b is exposed on the surface 25a of the.

【０００４】ここに、インナリード２２ａと半導体チッ
プ２１とを接続するボンディングワイヤ２４が、アウタ
リード２２ｂの表面２２ｃと面一にしたモールド樹脂２
５の表面２５ａからはみださないように、リードに段差
を設ける必要があるが、この従来例では、リードフレー
ム２２をダウンセット加工することによって、インナリ
ード２２ａをアウタリード２２ｂよりも一段低くしてい
る。Here, the molding resin 2 in which the bonding wire 24 connecting the inner lead 22a and the semiconductor chip 21 is flush with the surface 22c of the outer lead 22b.
It is necessary to provide a step on the lead so as not to protrude from the surface 25a of No. 5, but in this conventional example, the inner lead 22a is made lower than the outer lead 22b by downsetting the lead frame 22. ing.

【０００５】[0005]

【発明が解決しようとする課題】上述した従来技術によ
って、パッケージの小形化は、パッケージの専有する面
積に反映されるばかりでなく、パッケージの厚さ方向に
も反映されるようになってきた。しかし、リードフレー
ムをダウンセット加工することによってリードに段差を
設けるようにしているので、リード厚を超えた加工深さ
が必要となり、その分、パッケージ厚さを薄くできな
い。According to the above-mentioned conventional technique, the miniaturization of the package has been reflected not only in the area occupied by the package but also in the thickness direction of the package. However, since the lead frame is provided with a step by down-setting the lead frame, a processing depth exceeding the lead thickness is required, and the package thickness cannot be reduced accordingly.

【０００６】また、パッケージのサイズが半導体チップ
１と同一であると、最小のパッケージを得ることができ
るが、半導体チップ１の大きさのばらつきによっては、
モールド樹脂封止時にモールド金型が半導体チップ１の
一部を破損してしまうおそれがある。If the package size is the same as that of the semiconductor chip 1, the smallest package can be obtained. However, depending on the size variation of the semiconductor chip 1,
There is a risk that the molding die may damage a part of the semiconductor chip 1 when the molding resin is sealed.

【０００７】さらに、半導体チップへのリードフレーム
の接着固定は、インナリード側のみで行なっているた
め、モールド樹脂封止の際に、アウタリード側の厚み方
向での固定が十分でない場合が生じるが、固定が十分で
ないと、アウタリードの表面にモールド樹脂が薄く回り
込み、表面を削り出す必要があった。Further, since the lead frame is bonded and fixed to the semiconductor chip only on the inner lead side, there is a case where the outer lead side is not sufficiently fixed in the thickness direction at the time of sealing with the mold resin. If the fixing was not sufficient, the molding resin was thinly wrapped around the surface of the outer lead, and the surface had to be ground.

【０００８】本発明の目的は、上述した従来技術の問題
点を解消して、パッケージ厚さをより薄くできる半導体
装置を提供することにある。また、本発明の目的は、モ
ールド樹脂封止時、半導体チップが破損しない半導体装
置を提供することにある。さらに、本発明の目的は、モ
ールド樹脂封止後、アウタリード表面の削り出しを必要
としない半導体装置を提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor device capable of reducing the package thickness. Another object of the present invention is to provide a semiconductor device in which a semiconductor chip is not damaged during molding resin encapsulation. A further object of the present invention is to provide a semiconductor device which does not require shaving of the outer lead surface after molding resin encapsulation.

【０００９】[0009]

【課題を解決するための手段】本発明の半導体装置は、
半導体チップの表面に半導体チップと略同一サイズのリ
ードフレームを重ね合わせて接着剤を介して貼り付け、
リードフレームのインナリードと半導体チップとをボン
ディングワイヤで接続し、アウタリードの表面と面一と
なるように半導体チップの表面側をモールド樹脂で封止
して、封止樹脂表面にアウタリードの表面を露出させた
半導体装置において、インナリードに接続されるボンデ
ィングワイヤがアウタリードの表面を越えないように、
インナリードの表面側の厚みを減らしてインナリード表
面をアウタリード表面より一段低くしたものである。こ
のようにインナリードの厚みをアウタリードよりも減ら
してインナリードをアウタリードより一段低くできるよ
うにすると、リードをダウンセットする場合に比して、
パッケージ厚さをより薄くすることができる。According to the present invention, there is provided a semiconductor device comprising:
A lead frame of approximately the same size as the semiconductor chip is overlaid on the surface of the semiconductor chip and attached with an adhesive,
The inner lead of the lead frame and the semiconductor chip are connected with a bonding wire, the surface side of the semiconductor chip is sealed with mold resin so that it is flush with the surface of the outer lead, and the outer lead surface is exposed on the sealing resin surface. In the semiconductor device, the bonding wire connected to the inner lead does not exceed the surface of the outer lead.
The inner lead surface is made one step lower than the outer lead surface by reducing the thickness of the inner lead surface side. If the inner lead can be made thinner than the outer lead and the inner lead can be made one step lower than the outer lead in this way, compared to the case where the lead is down-set,
The package thickness can be made thinner.

【００１０】また、このような本発明の半導体装置にお
いて、リードフレームのサイズを半導体チップよりやや
大きめに形成し、リードフレームを半導体チップの表面
に重ね合わせたとき形成される端面間のギャップもモー
ルド樹脂で封止することが、半導体チップの破損を有効
に防止できる。また、半導体チップの表面にリードフレ
ームを貼り付ける接着剤を、インナリード側のみならず
アウタリード側にも介在させることが、アウタリードの
表面へのモールド樹脂の回り込みを防止できる。Further, in such a semiconductor device of the present invention, the size of the lead frame is formed slightly larger than that of the semiconductor chip, and the gap between the end faces formed when the lead frame is superposed on the surface of the semiconductor chip is also molded. Sealing with a resin can effectively prevent damage to the semiconductor chip. Further, by interposing an adhesive for attaching the lead frame on the surface of the semiconductor chip not only on the inner lead side but also on the outer lead side, it is possible to prevent the molding resin from flowing around the surface of the outer lead.

【００１１】[0011]

【発明の実施の形態】以下に本発明の半導体装置の実施
の形態を図面を用いて詳細に説明する。図１は、半導体
チップ１上に同一サイズのリードフレーム４を載せたＣ
ＳＰ構造の断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a C in which a lead frame 4 of the same size is mounted on a semiconductor chip 1.
It is sectional drawing of SP structure.

【００１２】半導体チップ１は、その配線面である表面
１ａの中央近傍にボンディングパッド２が配置されて構
成される。この半導体チップ１の表面１ａに貼り付けら
れるリードフレーム４は、半導体チップ１と同一サイズ
で構成され、半導体チップ１と接続するためのインナリ
ード４ａと、外部端子となるアウタリード４ｂとを有す
る。半導体チップ１とリードフレーム４との貼付けは、
半導体チップ１の端面１ｃとリードフレーム４の端面４
ｄとが一致するように、半導体チップ１とリードフレー
ム４とを重ね合わせて、両面接着剤付テープ３を介して
行う。The semiconductor chip 1 is constructed by arranging a bonding pad 2 in the vicinity of the center of a surface 1a which is a wiring surface of the semiconductor chip 1. The lead frame 4 attached to the surface 1a of the semiconductor chip 1 has the same size as the semiconductor chip 1, and has an inner lead 4a for connecting to the semiconductor chip 1 and an outer lead 4b serving as an external terminal. For the attachment of the semiconductor chip 1 and the lead frame 4,
The end surface 1c of the semiconductor chip 1 and the end surface 4 of the lead frame 4
The semiconductor chip 1 and the lead frame 4 are overlapped with each other so that they coincide with d, and this is performed through the double-sided adhesive tape 3.

【００１３】リードフレーム４は折曲していない代り
に、一部の厚さを減らして薄くしてある。すなわち、リ
ードフレーム４のインナリード４ａは、その貼付け面と
反対面（表面４ｅ）側をコイニングしてアウタリード４
ｂよりも薄くしたコイニング部５を形成し、インナリー
ド４ａと半導体チップ１のボンディングパッド２とを接
続するボンディングワイヤ９の高さをアウタリード４ｂ
の貼付け面と反対面（表面４ｃ）よりも低くなるように
してある。Although the lead frame 4 is not bent, a part of the lead frame 4 is reduced in thickness to be thin. That is, the inner lead 4a of the lead frame 4 is coined on the surface (front surface 4e) opposite to the surface to which the outer lead 4a is attached.
The coining portion 5 thinner than b is formed, and the height of the bonding wire 9 connecting the inner lead 4a and the bonding pad 2 of the semiconductor chip 1 is set to the outer lead 4b.
It is designed to be lower than the surface (surface 4c) opposite to the surface to which is attached.

【００１４】このようにして厚さを減らしてアウタリー
ド４ｂの表面４ｃよりも一段低くしたインナリード４ａ
のコイニング部５には銀めっき６が施され、銀めっき６
が施されたコイニング部５と半導体チップ１の中央近傍
に配されたボンディングパッド２とがボンディングワイ
ヤ９によって接続される。コイニング部５が一段低くな
っているため、ボンディングワイヤ９の高さは、アウタ
リード４ｂの表面４ｃより低く抑えることができる。In this way, the inner lead 4a whose thickness is reduced to be one step lower than the surface 4c of the outer lead 4b is provided.
Silver coating 6 is applied to the coining portion 5 of
The coining portion 5 provided with and the bonding pad 2 arranged near the center of the semiconductor chip 1 are connected by a bonding wire 9. Since the coining portion 5 is one step lower, the height of the bonding wire 9 can be kept lower than the surface 4c of the outer lead 4b.

【００１５】モールド樹脂８による封止は、半導体チッ
プ１の表面１ａ側で行なわれる。モールド樹脂８の厚さ
を、アウタリード４ｂの表面４ｃと同一高さにして、イ
ンナリード４ａおよびボンディングワイヤ９などをモー
ルド樹脂８中に埋めて保護するが、アウタリード４ｂの
表面４ｃは封止樹脂表面８ａに露出させる。このとき、
パッケージの面積を小さく、かつパッケージの厚さを薄
くするために、モールド樹脂８は、リードフレーム４の
端面４ｄ及び半導体チップ１の端面１ｃ及び半導体チッ
プ１の裏面１ｂに回りこまないようにする。The sealing with the mold resin 8 is performed on the front surface 1a side of the semiconductor chip 1. The thickness of the molding resin 8 is set to be the same height as the surface 4c of the outer lead 4b, and the inner lead 4a and the bonding wire 9 are buried in the molding resin 8 for protection, but the surface 4c of the outer lead 4b is the sealing resin surface. Exposed to 8a. At this time,
In order to reduce the area of the package and reduce the thickness of the package, the mold resin 8 is prevented from wrapping around the end surface 4d of the lead frame 4, the end surface 1c of the semiconductor chip 1 and the back surface 1b of the semiconductor chip 1.

【００１６】このように構成された半導体パッケージ
は、コイニングによってリードに段差を設けているた
め、従来のようにリードフレームをダウンセットする必
要はない。また、パッケージ厚さは半導体チップ厚、両
面接着剤付テープ厚、及び１枚のリード厚を合計した厚
さとなり、ダウンセットが要求するリード厚の２倍以上
の加工深さがリード部分に要求されないため、パッケー
ジの厚さをより薄くすることができる。In the semiconductor package thus constructed, the leads are stepped by coining, so that it is not necessary to downset the lead frame as in the conventional case. Also, the package thickness is the sum of the semiconductor chip thickness, the double-sided adhesive tape thickness, and the thickness of one lead, and the lead portion requires a processing depth that is at least twice the lead thickness required for downset. Since this is not done, the thickness of the package can be made thinner.

【００１７】上述した半導体パッケージを製造するに
は、まず、モールド樹脂８の端面８ｂを半導体チップ１
の端面１ｃに一致させるために、パッケージに使用され
るリードフレーム４は、その樹脂ダムバー１７の位置
を、図２に示すように、一点鎖線で示した半導体チップ
１の外周に沿って配置するように構成する。また、パッ
ケージ製造時に使用するモールド金型は、半導体チップ
１の外形とほぼ同じ大きさとし、半導体チップ１の裏面
１ｂ側にモールド樹脂８が回らないようにして、半導体
チップの表面側のみをモールドする。なお、リードフレ
ーム４の端面４ｄは樹脂ダムバー１７の切断面となる。In order to manufacture the above-mentioned semiconductor package, first, the end surface 8b of the mold resin 8 is attached to the semiconductor chip 1.
In order to match the end face 1c of the semiconductor chip 1, the lead frame 4 used in the package is arranged such that the position of the resin dam bar 17 is arranged along the outer periphery of the semiconductor chip 1 shown by the chain line as shown in FIG. To configure. In addition, the mold used for manufacturing the package has substantially the same size as the outer shape of the semiconductor chip 1, and only the front surface side of the semiconductor chip is molded so that the mold resin 8 does not rotate on the back surface 1b side of the semiconductor chip 1. . The end surface 4d of the lead frame 4 serves as a cut surface of the resin dam bar 17.

【００１８】モールド後、樹脂ダムバー１７を金型で切
断し、リード４ａ、４ｂを個々に切り離す。ここで、樹
脂ダムバー１７を切断する前に、モールド樹脂８の表面
８ａに露出するアウタリード４ｂの表面４ｃに、半田と
の濡れが良好な銀めっき７をインナリード４ａのコイニ
ング部５の銀めっき６と同時に行っておくのがよい。こ
うするとアウタリード４ｂの表面の外装半田めっきは不
要となり、コスト低減できるとともに、モールド後、パ
ッケージにダメージを与える工程を減らすことができる
点でも有利である。After the molding, the resin dam bar 17 is cut with a die to separate the leads 4a and 4b individually. Here, before the resin dam bar 17 is cut, the surface 4c of the outer lead 4b exposed on the surface 8a of the mold resin 8 is provided with silver plating 7 which is well wetted by solder and silver plating 6 of the coining portion 5 of the inner lead 4a. It is good to go at the same time. This eliminates the need for external solder plating on the surface of the outer leads 4b, which is advantageous in that the cost can be reduced and the number of steps that damage the package after molding can be reduced.

【００１９】本製造方法によれば、従来より行われてい
るＬＯＣリードフレームの製造工程、および樹脂モール
ド工程をそのまま、または、一部省略して利用すること
ができるため、従来のモールドパッケージと比較して価
格的に同等でありながら、より小型かつ薄型のパッケー
ジを得ることができる。According to this manufacturing method, the conventional LOC lead frame manufacturing process and the resin molding process can be used as they are or by omitting a part thereof. Therefore, compared with the conventional mold package. Thus, it is possible to obtain a smaller and thinner package at the same price.

【００２０】ところで、図１に示すパッケージ構造のモ
ールド領域では、パッケージのサイズが半導体チップ１
と同一であるため、半導体チップ１の大きさのばらつき
によっては、モールド金型が半導体チップ１の一部を破
損してしまうことが懸念される。このような懸念は、図
３に示すように、半導体チップ１に対してモールド領域
を若干拡大する設定を行うことよって解消できる。すな
わち、リードフレーム４のサイズを半導体チップ１より
やや大きめに形成し、このやや大きめに形成したリード
フレーム４の樹脂ダムバー１７にモールド金型の大きさ
を合わせて形成すると、半導体チップ１の大きさにばら
つきが合っても、モールド金型は半導体チップ１の端面
１ｃに触れなくなるから半導体チップ１の破損を防止で
きる。なお、モールド樹脂８による封止により、リード
フレーム４の端面４ｄと半導体チップ１の端面１ｃとの
間に形成されるギャップＧは、モールド樹脂１１で埋め
られる。したがって、半導体チップ１の端面１ｃは、樹
脂封止後はモールド樹脂１１によって保護される。By the way, in the mold region of the package structure shown in FIG.
Therefore, there is a concern that the molding die may damage a part of the semiconductor chip 1 depending on the variation in the size of the semiconductor chip 1. Such concern can be resolved by setting the semiconductor chip 1 so that the mold region is slightly enlarged as shown in FIG. That is, when the lead frame 4 is formed to be slightly larger than the semiconductor chip 1 and the resin dam bar 17 of the lead frame 4 formed to be slightly larger is formed to match the size of the molding die, the size of the semiconductor chip 1 is reduced. Even if there are variations, the mold die does not touch the end surface 1c of the semiconductor chip 1, so that the semiconductor chip 1 can be prevented from being damaged. It should be noted that the gap G formed between the end surface 4 d of the lead frame 4 and the end surface 1 c of the semiconductor chip 1 by the sealing with the mold resin 8 is filled with the mold resin 11. Therefore, the end surface 1c of the semiconductor chip 1 is protected by the mold resin 11 after resin sealing.

【００２１】また、図１及び図３に示すパッケージ構造
では、パッケージをモールドする際に、両面接着剤付テ
ープ３によるアウタリード４ｂ側の厚み方向での固定が
十分でないと、アウタリード４ｂの表面４ｃにモールド
樹脂が薄く回り込み、表面を削り出す必要が生じてしま
う。これは図４に示すように、パッケージ外周近傍の半
導体チップ１とアウタリード４ｂ間に、インナリード側
の両面接着剤付テープ３と同等の厚みをもつ両面接着剤
付テープ１３を介在させることにより、モールド樹脂８
のアウタリード表面４ｃへの回りこみを有効に防止でき
る。なお、図３と図４を組み合わせた構造としてもよい
ことはもちろんである。Further, in the package structure shown in FIGS. 1 and 3, if the outer lead 4b side tape 3 is not sufficiently fixed in the thickness direction by the double-sided adhesive tape 3 when the package is molded, the outer lead 4b has a surface 4c. The mold resin wraps around thinly, and the surface needs to be carved out. As shown in FIG. 4, a double-sided adhesive tape 13 having the same thickness as the double-sided adhesive tape 3 on the inner lead side is interposed between the semiconductor chip 1 and the outer lead 4b near the outer periphery of the package, Mold resin 8
Can be effectively prevented from sneaking into the outer lead surface 4c. Needless to say, the structure may be a combination of FIGS. 3 and 4.

【００２２】また、図１、図３、図４の構造では、アウ
タリード４ｂの表面４ｃの全面に銀めっき７を施した
が、そうすると銀の目付量が増加してコストが上昇する
ことが予想される。しかし、図５に示すように、アウタ
リード４ｂの銀めっき１４の領域を小さくすることによ
って、銀の目付量を減少でき、コスト的に有利にするこ
とができる。なお、符号１５は銀めっきを施していない
部分を示す。In the structures shown in FIGS. 1, 3, and 4, silver plating 7 is applied to the entire surface 4c of the outer lead 4b. However, if this is done, it is expected that the weight of silver will increase and the cost will increase. It However, as shown in FIG. 5, by reducing the area of the silver plating 14 of the outer leads 4b, the weight of silver can be reduced, which is advantageous in terms of cost. Note that reference numeral 15 indicates a portion that is not plated with silver.

【００２３】図６はアウタリード４ｂの表面４ｃに半田
めっき１６を外装した例を示す。既述したように、アウ
タリード４ｂの表面に半田めっきを外装することは、モ
ールド後、パッケージにダメージを与える工程が増える
ことを意味するが、本発明はこれを排除するものではな
い。FIG. 6 shows an example in which the surface 4c of the outer lead 4b is covered with the solder plating 16. As described above, coating the surface of the outer lead 4b with the solder plating means that the number of steps for damaging the package after molding increases, but the present invention does not exclude this.

【００２４】以上述べた本実施の形態において、使用し
た半導体チップの厚さは０．３mm、リードフレームの厚
さは０．１５mm、両面接着剤付テープの総厚は０．０５
mmである。また、インナリードには０．０７５mmのコイ
ニングを施した。また、本実施の形態ではインナリード
の厚さを減らす手法としてコイニング法を用いたが、ハ
ーフエッチ法を用いてもよい。また、リードフレームを
半導体チップに貼り付ける手段として両面接着剤付テー
プを用いたが、単に接着剤としてもよい。In the present embodiment described above, the semiconductor chip used has a thickness of 0.3 mm, the lead frame has a thickness of 0.15 mm, and the total thickness of the double-sided adhesive tape is 0.05.
mm. The inner lead was coined with a thickness of 0.075 mm. Further, although the coining method is used as the method of reducing the thickness of the inner lead in the present embodiment, the half etching method may be used. Further, although the double-sided adhesive-attached tape is used as a means for attaching the lead frame to the semiconductor chip, it may be simply an adhesive.

【００２５】[0025]

【発明の効果】本発明によれば、インナリードの厚みを
減らすことによってリードに段差を設けるようにしたの
で、ダウンセット加工することによって段差を設けるよ
うにした従来例のように、リード厚を超えた加工深さを
必要としないため、パッケージ厚さをより薄くできる。
また、リードフレームのサイズを半導体チップよりやや
大きめに形成したので、モールド金型による半導体チッ
プの損傷を有効に防止できる。さらに、半導体チップの
表面にリードフレームを貼り付ける接着剤を、アウタリ
ード側にも介在させるようにしたので、アウタリード表
面へのモールド樹脂の回り込みを防止でき、表面の削り
出しを要しない。According to the present invention, since the step is formed on the lead by reducing the thickness of the inner lead, the lead thickness can be reduced as in the conventional example in which the step is formed by down setting. Since it does not require an excessive processing depth, the package thickness can be made thinner.
Further, since the lead frame is formed slightly larger than the semiconductor chip, it is possible to effectively prevent the semiconductor chip from being damaged by the molding die. Further, since the adhesive for attaching the lead frame to the surface of the semiconductor chip is also provided on the outer lead side, it is possible to prevent the mold resin from wrapping around the outer lead surface, and it is not necessary to cut the surface.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置の第１の実施の形態を説明
するための半導体パッケージ構造の断面図である。FIG. 1 is a cross-sectional view of a semiconductor package structure for explaining a first embodiment of a semiconductor device of the present invention.

【図２】第１の実施の形態の半導体パッケージ構造に使
用されるリードフレームの平面図である。FIG. 2 is a plan view of a lead frame used in the semiconductor package structure of the first embodiment.

【図３】第２の実施の形態の半導体パッケージ構造の断
面図である。FIG. 3 is a sectional view of a semiconductor package structure according to a second embodiment.

【図４】第３の実施の形態の半導体パッケージ構造の断
面図である。FIG. 4 is a sectional view of a semiconductor package structure according to a third embodiment.

【図５】第４の実施の形態の半導体パッケージ構造の断
面図である。FIG. 5 is a sectional view of a semiconductor package structure according to a fourth embodiment.

【図６】第５の実施の形態の半導体パッケージ構造の断
面図である。FIG. 6 is a sectional view of a semiconductor package structure according to a fifth embodiment.

【図７】従来例の半導体パッケージ構造の断面図であ
る。FIG. 7 is a cross-sectional view of a conventional semiconductor package structure.

【符号の説明】[Explanation of symbols]

１ 半導体チップ １ａ 半導体チップの表面 ３ 両面接着剤付テープ ４ リードフレーム ４ａ インナリード ４ｅ インナリードの表面 ４ｂ アウタリード ４ｃ アウタリードの表面 ５ コイニング部 ８ モールド樹脂 ８ａ 封止樹脂表面 ９ ボンディングワイヤ 1 Semiconductor Chip 1a Surface of Semiconductor Chip 3 Double-sided Adhesive Tape 4 Lead Frame 4a Inner Lead 4e Inner Lead Surface 4b Outer Lead 4c Outer Lead Surface 5 Coining Part 8 Mold Resin 8a Sealing Resin Surface 9 Bonding Wire

───────────────────────────────────────────────────── フロントページの続き (72)発明者 米本 隆治 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 (72)発明者 吉岡 修 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryuji Yonemoto 3550, Kitayo-cho, Tsuchiura-shi, Ibaraki Hitachi Cable, Ltd. System Materials Laboratory (72) Inventor Osamu Yoshioka 3550, Kidayo-cho, Tsuchiura, Ibaraki Hitachi Cable System Materials Laboratory Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】半導体チップの表面に半導体チップと略同
一サイズのリードフレームを重ね合わせて接着剤を介し
て貼り付け、リードフレームのインナリードと半導体チ
ップとをボンディングワイヤで接続し、アウタリードの
表面と面一となるように半導体チップの表面側をモール
ド樹脂で封止して、封止樹脂表面にアウタリードの表面
を露出させた半導体装置において、インナリードに接続
されるボンディングワイヤがアウタリードの表面を越え
ないように、インナリードの表面側の厚みを減らしてイ
ンナリード表面をアウタリード表面より一段低くしたこ
とを特徴とする半導体装置。1. A surface of a semiconductor chip, a lead frame of approximately the same size as the semiconductor chip is superposed and attached via an adhesive, the inner lead of the lead frame and the semiconductor chip are connected by a bonding wire, and the surface of the outer lead. In a semiconductor device in which the surface side of the semiconductor chip is sealed with a molding resin so that the surface of the outer lead is exposed so that it is flush with the surface of the outer lead, the bonding wire connected to the inner lead is A semiconductor device in which the thickness of the inner lead surface side is reduced so that the inner lead surface is made lower than the outer lead surface so as not to exceed the inner lead surface. 【請求項２】上記リードフレームのサイズを半導体チッ
プよりやや大きめに形成し、該リードフレームを半導体
チップの表面に重ね合わせたとき形成される端面間のギ
ャップもモールド樹脂で封止するようにした請求項１に
記載の半導体装置。2. The size of the lead frame is formed to be slightly larger than that of the semiconductor chip, and a gap between end faces formed when the lead frame is superposed on the surface of the semiconductor chip is also sealed with a molding resin. The semiconductor device according to claim 1. 【請求項３】上記半導体チップの表面にリードフレーム
を貼り付ける接着剤を、インナリード側のみならずアウ
タリード側にも介在させた請求項１または２に記載の半
導体装置。3. The semiconductor device according to claim 1, wherein an adhesive for attaching a lead frame to the surface of the semiconductor chip is provided not only on the inner lead side but also on the outer lead side.
JP24420495A 1995-09-22 1995-09-22 Semiconductor device Expired - Fee Related JP3163961B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24420495A JP3163961B2 (en) 1995-09-22 1995-09-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24420495A JP3163961B2 (en) 1995-09-22 1995-09-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0992775A true JPH0992775A (en) 1997-04-04
JP3163961B2 JP3163961B2 (en) 2001-05-08

Family

ID=17115325

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3163961B2 (en)

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