JPH0992775A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH0992775A
JPH0992775A JP24420495A JP24420495A JPH0992775A JP H0992775 A JPH0992775 A JP H0992775A JP 24420495 A JP24420495 A JP 24420495A JP 24420495 A JP24420495 A JP 24420495A JP H0992775 A JPH0992775 A JP H0992775A
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JP
Japan
Prior art keywords
surface
semiconductor chip
lead
lead frame
outer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24420495A
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Japanese (ja)
Other versions
JP3163961B2 (en
Inventor
Kazuhisa Hatano
Hajime Murakami
Tatsuya Otaka
Takaharu Yonemoto
Osamu Yoshioka
修 吉岡
達也 大高
和久 幡野
村上  元
隆治 米本
Original Assignee
Hitachi Cable Ltd
日立電線株式会社
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Application filed by Hitachi Cable Ltd, 日立電線株式会社 filed Critical Hitachi Cable Ltd
Priority to JP24420495A priority Critical patent/JP3163961B2/en
Publication of JPH0992775A publication Critical patent/JPH0992775A/en
Application granted granted Critical
Publication of JP3163961B2 publication Critical patent/JP3163961B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To make a package small in thickness in a CSP (Chip Scale Package) structure by which a lead frame of the same size is mounted on a semiconductor chip. SOLUTION: A lead frame 4 to be adhered to a semiconductor chip 1 is almost the same in size as the chip 1. The surface 4e of an inner lead 4a of the lead frame 4 is coined to form a coined part 5 with reduced thickness. The lead frame 4 and the end surface 1c of the chip 1 are adhered to each other with a double-faced adhesive tape 3 interposed. The coined part 5 of the inner lead 4a is connected with a bonding pad 2 of the chip 1 through a bonding wire 9. The surface 1a of the chip 1 is packaged with a mold resin 8, thereby exposing only the surface 4c of an outer lead 4b on the packaged resin surface 8a.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明はリードフレームを使用した半導体装置に係り、特にチップサイズと略同一のサイズをもつ薄型かつ小型の半導体パッケージ構造に関するものである。 The present invention relates to relates to a semiconductor device using a lead frame, to a thin and compact semiconductor package structure particularly with the chip size and substantially the same size.

【0002】 [0002]

【従来の技術】大容量のDRAM(Dynamic Random Acc DRAM Background of the Invention large capacity (Dynamic Random Acc
ess Memory)では、高密度実装の要求に対応して、比較的小さなパッケージに大形化した半導体チップを収納できるLOC(Lead On Chip)構造が採用されているが、 In ess Memory), in response to a request of high density mounting, but relatively large in smaller packaged semiconductor chips can hold LOC (Lead On Chip) structure is employed,
容量の増加により更にチップサイズレベルにまで小形化されたパッケージが要求されるようになってきた。 Furthermore has come to packages miniaturized to a chip size level is required by the increased capacity. また、電子機器用の半導体パッケージも、パソコン、ファックス,パーソナル電話機、ICカード等のサイズの縮小に伴って、より小形化することが要求されている。 The semiconductor package of electronics also PCs, fax machines, personal phones, along with the reduction in the size of an IC card, has been required to be more compact. しかも、この小形化は、単にパッケージの専有する面積にのみ求められるのではなく、パッケージの厚さ方向にも求められている。 Moreover, the miniaturization is not simply determined only on the area to be occupied in the package, it is also required in the thickness direction of the package.

【0003】従来、これらの要請に応えるものとして、 [0003] Conventionally, as to respond to these requests,
リードの一部のみをパッケージの底面に露出させたCS CS to expose only a portion of the lead in the bottom of the package
P(Chip Scale Package)と呼ばれる半導体装置が提案されている(特開平6−132453号公報)。 P (Chip Scale Package) semiconductor device called has been proposed (JP-A-6-132453). 具体的には、図7に示すように、半導体チップ21の配線面(表面)21aに半導体チップ21と同一サイズのリードフレーム22を端面を合わせて接着剤23で貼り付ける。 Specifically, as shown in FIG. 7, pasted with adhesive 23 together end face on the wiring surface (surface) 21a of the semiconductor chip 21 and the lead frame 22 having the same size of the semiconductor chip 21. リードフレーム22のインナリード22aと半導体チップ21とをボンディングワイヤ24で接続した後、 After connecting the inner leads 22a and the semiconductor chip 21 of the lead frame 22 by bonding wires 24,
モールド樹脂25で封止する際、半導体チップ21の表面側をモールド樹脂25で封止して、モールド樹脂25 When sealed with the mold resin 25, it seals the surface side of the semiconductor chip 21 with the molding resin 25, the mold resin 25
の表面25aにアウタリード22bの表面22cを露出させたものである。 The surface 25a of the is obtained by exposing the surface 22c of the outer lead 22b.

【0004】ここに、インナリード22aと半導体チップ21とを接続するボンディングワイヤ24が、アウタリード22bの表面22cと面一にしたモールド樹脂2 [0004] Here, the inner leads 22a and the bonding wires 24 for connecting the semiconductor chip 21, the molding resin 2 that the surface 22c is flush with the outer lead 22b
5の表面25aからはみださないように、リードに段差を設ける必要があるが、この従来例では、リードフレーム22をダウンセット加工することによって、インナリード22aをアウタリード22bよりも一段低くしている。 So as not to protrude from the fifth surface 25a, it is necessary to provide a step in the lead, in this conventional example, by down-set working the lead frame 22, the inner leads 22a and one step lower than the outer leads 22b ing.

【0005】 [0005]

【発明が解決しようとする課題】上述した従来技術によって、パッケージの小形化は、パッケージの専有する面積に反映されるばかりでなく、パッケージの厚さ方向にも反映されるようになってきた。 The [0005] prior art described above, miniaturization of the package is not only reflected on the area to be occupied in the package, has come to be reflected in the thickness direction of the package. しかし、リードフレームをダウンセット加工することによってリードに段差を設けるようにしているので、リード厚を超えた加工深さが必要となり、その分、パッケージ厚さを薄くできない。 However, since the so providing the step to the lead by down-set working the lead frame, the machining depth beyond the lead thickness is required, correspondingly, it can not reduce the package thickness.

【0006】また、パッケージのサイズが半導体チップ1と同一であると、最小のパッケージを得ることができるが、半導体チップ1の大きさのばらつきによっては、 Further, when the size of the package is the same as the semiconductor chip 1, it is possible to obtain the smallest package, due to variations in size of the semiconductor chip 1,
モールド樹脂封止時にモールド金型が半導体チップ1の一部を破損してしまうおそれがある。 Molding die when molding the resin sealing may be damaged a part of the semiconductor chip 1.

【0007】さらに、半導体チップへのリードフレームの接着固定は、インナリード側のみで行なっているため、モールド樹脂封止の際に、アウタリード側の厚み方向での固定が十分でない場合が生じるが、固定が十分でないと、アウタリードの表面にモールド樹脂が薄く回り込み、表面を削り出す必要があった。 Furthermore, the adhesive fixing of the lead frame to the semiconductor chip, since performed in only the inner lead side, when the mold resin sealing, but occurs when fixed in the thickness direction of the outer lead side is not sufficient, If fixing is not sufficient, the mold resin wraparound thinly on the surface of the outer lead, it is necessary to cut out the surface.

【0008】本発明の目的は、上述した従来技術の問題点を解消して、パッケージ厚さをより薄くできる半導体装置を提供することにある。 An object of the present invention is to solve the problems of the prior art described above, it is to provide a semiconductor device and more can be made thin package thickness. また、本発明の目的は、モールド樹脂封止時、半導体チップが破損しない半導体装置を提供することにある。 Another object of the present invention, when the mold resin sealing is to provide a semiconductor device in which a semiconductor chip is not damaged. さらに、本発明の目的は、モールド樹脂封止後、アウタリード表面の削り出しを必要としない半導体装置を提供することにある。 Furthermore, object of the present invention, after the mold resin sealing is to provide a semiconductor device which does not require shaving of the outer lead surface.

【0009】 [0009]

【課題を解決するための手段】本発明の半導体装置は、 The semiconductor device of the present invention According to an aspect of the
半導体チップの表面に半導体チップと略同一サイズのリードフレームを重ね合わせて接着剤を介して貼り付け、 The surface of the semiconductor chip by superimposing the semiconductor chip and the lead frame of substantially the same size adhered via an adhesive,
リードフレームのインナリードと半導体チップとをボンディングワイヤで接続し、アウタリードの表面と面一となるように半導体チップの表面側をモールド樹脂で封止して、封止樹脂表面にアウタリードの表面を露出させた半導体装置において、インナリードに接続されるボンディングワイヤがアウタリードの表面を越えないように、 Connecting the inner leads and the semiconductor chip of a lead frame by bonding wires, seals the surface side of the semiconductor chip at the molding resin so as to flush with the surface of the outer lead, the exposed surfaces of the outer leads to the sealing resin surface in the semiconductor device with, as bonding wire connected to the inner leads is not beyond the surface of the outer leads,
インナリードの表面側の厚みを減らしてインナリード表面をアウタリード表面より一段低くしたものである。 It is obtained by a one-step lower level than the outer lead surface inner lead surface by reducing the surface side of the thickness of the inner lead. このようにインナリードの厚みをアウタリードよりも減らしてインナリードをアウタリードより一段低くできるようにすると、リードをダウンセットする場合に比して、 With this as the thickness of the inner lead can be one step lower than the outer lead to the inner lead reduced than the outer leads, as compared with the case of down-set lead,
パッケージ厚さをより薄くすることができる。 It is possible to further reduce the package thickness.

【0010】また、このような本発明の半導体装置において、リードフレームのサイズを半導体チップよりやや大きめに形成し、リードフレームを半導体チップの表面に重ね合わせたとき形成される端面間のギャップもモールド樹脂で封止することが、半導体チップの破損を有効に防止できる。 [0010] In the semiconductor device of the present invention, the size of the lead frame and slightly larger form than the semiconductor chip, also the gap between the end surfaces formed when superposed lead frame on the surface of the semiconductor chip mold be sealed with resin, it is possible to effectively prevent damage to the semiconductor chip. また、半導体チップの表面にリードフレームを貼り付ける接着剤を、インナリード側のみならずアウタリード側にも介在させることが、アウタリードの表面へのモールド樹脂の回り込みを防止できる。 Further, an adhesive to the surface of the semiconductor chip pasting a lead frame, also is interposed outer lead side not the inner lead side only, can be prevented wraparound molding resin to the surface of the outer lead.

【0011】 [0011]

【発明の実施の形態】以下に本発明の半導体装置の実施の形態を図面を用いて詳細に説明する。 It will be described in detail with reference to the drawings an embodiment of the semiconductor device of the present invention in the following DETAILED DESCRIPTION OF THE INVENTION. 図1は、半導体チップ1上に同一サイズのリードフレーム4を載せたC 1, C carrying the lead frame 4 of the same size on the semiconductor chip 1
SP構造の断面図である。 It is a cross-sectional view of the SP structure.

【0012】半導体チップ1は、その配線面である表面1aの中央近傍にボンディングパッド2が配置されて構成される。 [0012] The semiconductor chip 1 is configured to be arranged bonding pads 2 in the vicinity of the center of the surface 1a which is the wiring surface. この半導体チップ1の表面1aに貼り付けられるリードフレーム4は、半導体チップ1と同一サイズで構成され、半導体チップ1と接続するためのインナリード4aと、外部端子となるアウタリード4bとを有する。 Lead frame 4 which is attached to the surface 1a of the semiconductor chip 1 has been configured with the semiconductor chip 1 and the same size, and the inner leads 4a for connecting the semiconductor chip 1, and outer leads 4b serving as an external terminal. 半導体チップ1とリードフレーム4との貼付けは、 Paste the semiconductor chip 1 and the lead frame 4,
半導体チップ1の端面1cとリードフレーム4の端面4 The end face of the end face 1c and the lead frame 4 of the semiconductor chip 1 4
dとが一致するように、半導体チップ1とリードフレーム4とを重ね合わせて、両面接着剤付テープ3を介して行う。 As the d match, by overlapping the semiconductor chip 1 and the lead frame 4 is performed via the tape 3 with double-sided adhesive.

【0013】リードフレーム4は折曲していない代りに、一部の厚さを減らして薄くしてある。 [0013] The lead frame 4 is in place that is not bent, are thinned by reducing the portion of the thickness. すなわち、リードフレーム4のインナリード4aは、その貼付け面と反対面(表面4e)側をコイニングしてアウタリード4 That is, the inner lead 4a of the lead frame 4, the outer leads 4 and coining the opposite surface (surface 4e) side and its joining surfaces
bよりも薄くしたコイニング部5を形成し、インナリード4aと半導体チップ1のボンディングパッド2とを接続するボンディングワイヤ9の高さをアウタリード4b Forming a coining portion 5 which is thinner than b, height outer leads 4b of the bonding wires 9 for connecting the bonding pads 2 of the inner lead 4a and the semiconductor chip 1
の貼付け面と反対面(表面4c)よりも低くなるようにしてある。 Joining surfaces of the are set to be lower than the opposite surface (surface 4c).

【0014】このようにして厚さを減らしてアウタリード4bの表面4cよりも一段低くしたインナリード4a [0014] inner leads 4a was one step lower than the surface 4c of the outer leads 4b by reducing the thus thickness
のコイニング部5には銀めっき6が施され、銀めっき6 The coining portion 5 silver plating 6 is applied, silver plating 6
が施されたコイニング部5と半導体チップ1の中央近傍に配されたボンディングパッド2とがボンディングワイヤ9によって接続される。 And the bonding pads 2 arranged in the vicinity of the center of the coining portion 5 and the semiconductor chip 1 that has undergone are connected by a bonding wire 9. コイニング部5が一段低くなっているため、ボンディングワイヤ9の高さは、アウタリード4bの表面4cより低く抑えることができる。 Since the coining portion 5 is turned one step lower, the height of the bonding wires 9 can be suppressed lower than the surface 4c of the outer leads 4b.

【0015】モールド樹脂8による封止は、半導体チップ1の表面1a側で行なわれる。 The sealing by mold resin 8 is performed on the surface 1a side of the semiconductor chip 1. モールド樹脂8の厚さを、アウタリード4bの表面4cと同一高さにして、インナリード4aおよびボンディングワイヤ9などをモールド樹脂8中に埋めて保護するが、アウタリード4bの表面4cは封止樹脂表面8aに露出させる。 The thickness of the mold resin 8, and the surface 4c the same height as the outer lead 4b, protects fills and inner lead 4a and the bonding wires 9 in the molded resin 8, the surface 4c of the outer lead 4b the sealing resin surface It is exposed to 8a. このとき、 At this time,
パッケージの面積を小さく、かつパッケージの厚さを薄くするために、モールド樹脂8は、リードフレーム4の端面4d及び半導体チップ1の端面1c及び半導体チップ1の裏面1bに回りこまないようにする。 Reduce the area of ​​the package, and in order to reduce the thickness of the package, the molding resin 8, to avoid crowded around the end face 4d and the end face 1c and the semiconductor chip 1 of the back surface 1b of the semiconductor chip 1 of the lead frame 4.

【0016】このように構成された半導体パッケージは、コイニングによってリードに段差を設けているため、従来のようにリードフレームをダウンセットする必要はない。 [0016] configured semiconductor package in this way, since the provided with a step on the lead by coining, it is not necessary to down-set lead frame as in the prior art. また、パッケージ厚さは半導体チップ厚、両面接着剤付テープ厚、及び1枚のリード厚を合計した厚さとなり、ダウンセットが要求するリード厚の2倍以上の加工深さがリード部分に要求されないため、パッケージの厚さをより薄くすることができる。 Also, the package thickness is a semiconductor chip thickness, tape thickness double-sided adhesive, and becomes the total combined thickness of a sheet of a lead thickness, required more than twice the processing depth of the lead thickness of down-set is required to lead portions because it is not, it is possible to further reduce the thickness of the package.

【0017】上述した半導体パッケージを製造するには、まず、モールド樹脂8の端面8bを半導体チップ1 [0017] To manufacture the semiconductor package described above, first, the semiconductor chip 1 and the end face 8b of the molded resin 8
の端面1cに一致させるために、パッケージに使用されるリードフレーム4は、その樹脂ダムバー17の位置を、図2に示すように、一点鎖線で示した半導体チップ1の外周に沿って配置するように構成する。 To match the end surface 1c, the lead frame 4 which is used for packaging, the position of the resin dam bar 17, as shown in FIG. 2, to place along the outer periphery of the semiconductor chip 1 shown by the dashed line It is configured. また、パッケージ製造時に使用するモールド金型は、半導体チップ1の外形とほぼ同じ大きさとし、半導体チップ1の裏面1b側にモールド樹脂8が回らないようにして、半導体チップの表面側のみをモールドする。 Further, the molding die used during package manufacture, substantially the same size Satoshi the contour of the semiconductor chip 1, as a mold resin 8 does not turn on the back surface 1b side of the semiconductor chip 1, molded only the surface side of the semiconductor chip . なお、リードフレーム4の端面4dは樹脂ダムバー17の切断面となる。 The end face 4d of the lead frame 4 is the cut surface of the resin dam bar 17.

【0018】モールド後、樹脂ダムバー17を金型で切断し、リード4a、4bを個々に切り離す。 [0018] After the mold, cutting the resin dam bar 17 in the mold, disconnecting leads 4a, and 4b individually. ここで、樹脂ダムバー17を切断する前に、モールド樹脂8の表面8aに露出するアウタリード4bの表面4cに、半田との濡れが良好な銀めっき7をインナリード4aのコイニング部5の銀めっき6と同時に行っておくのがよい。 Here, before cutting the resin dam bar 17, the surface 4c of the outer leads 4b exposed on the surface 8a of the molded resin 8, wet silver plating good silver plating 7 inner leads 4a coining portion 5 with the solder 6 good idea to go to simultaneously with. こうするとアウタリード4bの表面の外装半田めっきは不要となり、コスト低減できるとともに、モールド後、パッケージにダメージを与える工程を減らすことができる点でも有利である。 In this way the outer solder plating on the surface of the outer lead 4b is not required, it is possible to reduce costs, after being molded, it is also advantageous in that it can reduce the process damage to the package.

【0019】本製造方法によれば、従来より行われているLOCリードフレームの製造工程、および樹脂モールド工程をそのまま、または、一部省略して利用することができるため、従来のモールドパッケージと比較して価格的に同等でありながら、より小型かつ薄型のパッケージを得ることができる。 According to the present manufacturing method, manufacturing process of the LOC lead frame has been done conventionally, and the resin molding process as it is or, it is possible to use partially omitted, compared with a conventional mold package and yet the price equivalent, it is possible to obtain a more compact and thin package.

【0020】ところで、図1に示すパッケージ構造のモールド領域では、パッケージのサイズが半導体チップ1 [0020] In the mold region of the package structure shown in FIG. 1, the size of the package the semiconductor chip 1
と同一であるため、半導体チップ1の大きさのばらつきによっては、モールド金型が半導体チップ1の一部を破損してしまうことが懸念される。 It is the same as, the variation in the size of the semiconductor chip 1, there is a concern that the molding die is damaged a part of the semiconductor chip 1. このような懸念は、図3に示すように、半導体チップ1に対してモールド領域を若干拡大する設定を行うことよって解消できる。 Such concerns, as shown in FIG. 3, can be eliminated I by carrying out the setting to expand the mold area slightly to the semiconductor chip 1. すなわち、リードフレーム4のサイズを半導体チップ1よりやや大きめに形成し、このやや大きめに形成したリードフレーム4の樹脂ダムバー17にモールド金型の大きさを合わせて形成すると、半導体チップ1の大きさにばらつきが合っても、モールド金型は半導体チップ1の端面1cに触れなくなるから半導体チップ1の破損を防止できる。 That is, the size of the lead frame 4 somewhat larger form than the semiconductor chip 1, to form together the size of the mold to the resin dam bar 17 of the lead frame 4 which is slightly larger form, of the semiconductor chip 1 size even if there are variations, the breakage of the semiconductor chip 1 from the molding die will not touch the end surface 1c of the semiconductor chip 1 can be prevented. なお、モールド樹脂8による封止により、リードフレーム4の端面4dと半導体チップ1の端面1cとの間に形成されるギャップGは、モールド樹脂11で埋められる。 Note that, by sealing with the molding resin 8, the gap G formed between the end face 1c of the end face 4d and the semiconductor chip 1 of the lead frame 4 is filled with the mold resin 11. したがって、半導体チップ1の端面1cは、樹脂封止後はモールド樹脂11によって保護される。 Therefore, the end surface 1c of the semiconductor chip 1 after the resin sealing is protected by the mold resin 11.

【0021】また、図1及び図3に示すパッケージ構造では、パッケージをモールドする際に、両面接着剤付テープ3によるアウタリード4b側の厚み方向での固定が十分でないと、アウタリード4bの表面4cにモールド樹脂が薄く回り込み、表面を削り出す必要が生じてしまう。 Moreover, the package structure shown in FIGS. 1 and 3, when molding the package, the fixation in the thickness direction of the outer lead 4b side by the tape 3 double-sided adhesive is insufficient, the surface 4c of the outer leads 4b mold resin wraparound thin, must cut out the surface occurs. これは図4に示すように、パッケージ外周近傍の半導体チップ1とアウタリード4b間に、インナリード側の両面接着剤付テープ3と同等の厚みをもつ両面接着剤付テープ13を介在させることにより、モールド樹脂8 This is because, as shown in FIG. 4, between the package near the outer periphery of the semiconductor chip 1 and the outer lead 4b, by interposing a double-sided adhesive tape with 13 having the same thickness and the tape 3 double-sided adhesive of the inner lead side, molding resin 8
のアウタリード表面4cへの回りこみを有効に防止できる。 Roundabout to the outer lead surface 4c can be effectively prevented. なお、図3と図4を組み合わせた構造としてもよいことはもちろんである。 Incidentally, it is of course may have a structure that combines Figures 3 and 4.

【0022】また、図1、図3、図4の構造では、アウタリード4bの表面4cの全面に銀めっき7を施したが、そうすると銀の目付量が増加してコストが上昇することが予想される。 Further, FIGS. 1, 3, in the structure of FIG. 4 has been subjected to silver plating 7 on the entire surface 4c of the outer lead 4b, Then basis weight of the silver is increased is expected that cost increases that. しかし、図5に示すように、アウタリード4bの銀めっき14の領域を小さくすることによって、銀の目付量を減少でき、コスト的に有利にすることができる。 However, as shown in FIG. 5, by reducing the area of ​​the silver plating 14 of the outer lead 4b, can reduce the basis weight of silver, it can be cost effective. なお、符号15は銀めっきを施していない部分を示す。 Reference numeral 15 denotes a portion not plated with silver.

【0023】図6はアウタリード4bの表面4cに半田めっき16を外装した例を示す。 [0023] Figure 6 shows an example in which the outer solder plating 16 on the surface 4c of the outer leads 4b. 既述したように、アウタリード4bの表面に半田めっきを外装することは、モールド後、パッケージにダメージを与える工程が増えることを意味するが、本発明はこれを排除するものではない。 As already described, to the exterior of the solder plating on the surface of the outer lead 4b after molding, but means that the step is increased to damage the package, the present invention does not exclude this.

【0024】以上述べた本実施の形態において、使用した半導体チップの厚さは0.3mm、リードフレームの厚さは0.15mm、両面接着剤付テープの総厚は0.05 [0024] In this embodiment as described above, the thickness of the semiconductor chips used were 0.3 mm, the total thickness thickness 0.15 mm, the tape double-sided adhesive leadframe 0.05
mmである。 A mm. また、インナリードには0.075mmのコイニングを施した。 In addition, the inner lead was subjected to coining of 0.075mm. また、本実施の形態ではインナリードの厚さを減らす手法としてコイニング法を用いたが、ハーフエッチ法を用いてもよい。 Although using coining method as a method of reducing the thickness of the inner leads in this embodiment, it may be a half etching method. また、リードフレームを半導体チップに貼り付ける手段として両面接着剤付テープを用いたが、単に接着剤としてもよい。 Although using a tape with double-sided adhesive as a means for pasting the lead frame to the semiconductor chip may be simply as an adhesive.

【0025】 [0025]

【発明の効果】本発明によれば、インナリードの厚みを減らすことによってリードに段差を設けるようにしたので、ダウンセット加工することによって段差を設けるようにした従来例のように、リード厚を超えた加工深さを必要としないため、パッケージ厚さをより薄くできる。 According to the present invention. Thus providing the step to the lead by reducing the thickness of the inner lead, as in the conventional example so as to provide a step by down-set processing, the lead thickness requires no machining depth in excess, it can be thinner package thickness.
また、リードフレームのサイズを半導体チップよりやや大きめに形成したので、モールド金型による半導体チップの損傷を有効に防止できる。 Also, since the forming size of the lead frame somewhat larger than the semiconductor chip can be effectively prevented from being damaged semiconductor chip by mold. さらに、半導体チップの表面にリードフレームを貼り付ける接着剤を、アウタリード側にも介在させるようにしたので、アウタリード表面へのモールド樹脂の回り込みを防止でき、表面の削り出しを要しない。 Furthermore, does not require an adhesive paste lead frame on the surface of the semiconductor chip, since the cause may be interposed outer lead side, can be prevented wraparound molding resin to the outer lead surface, the shaving surface.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の半導体装置の第1の実施の形態を説明するための半導体パッケージ構造の断面図である。 1 is a cross-sectional view of a semiconductor package structure for explaining a first embodiment of a semiconductor device of the present invention.

【図2】第1の実施の形態の半導体パッケージ構造に使用されるリードフレームの平面図である。 2 is a plan view of a lead frame used in a semiconductor package structure of the first embodiment.

【図3】第2の実施の形態の半導体パッケージ構造の断面図である。 3 is a sectional view of a semiconductor package structure of the second embodiment.

【図4】第3の実施の形態の半導体パッケージ構造の断面図である。 4 is a cross-sectional view of a semiconductor package structure of the third embodiment.

【図5】第4の実施の形態の半導体パッケージ構造の断面図である。 5 is a cross-sectional view of a semiconductor package structure of the fourth embodiment.

【図6】第5の実施の形態の半導体パッケージ構造の断面図である。 6 is a cross-sectional view of a semiconductor package structure of the fifth embodiment.

【図7】従来例の半導体パッケージ構造の断面図である。 7 is a cross-sectional view of a semiconductor package structure of a conventional example.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 半導体チップ 1a 半導体チップの表面 3 両面接着剤付テープ 4 リードフレーム 4a インナリード 4e インナリードの表面 4b アウタリード 4c アウタリードの表面 5 コイニング部 8 モールド樹脂 8a 封止樹脂表面 9 ボンディングワイヤ 1 semiconductor chip 1a semiconductor chip surface 3 tape double-sided adhesive 4 of the lead frame 4a inner leads 4e inner lead surface 4b outer leads 4c outer leads of the surface 5 coining portion 8 mold resin 8a sealing resin surface 9 bonding wire

───────────────────────────────────────────────────── フロントページの続き (72)発明者 米本 隆治 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 (72)発明者 吉岡 修 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Ryuji Yonemoto Tsuchiura, Ibaraki Prefecture Kidamari-cho, 3550 address Hitachi Cable, Ltd. system material in the Laboratory (72) inventor Osamu Yoshioka Tsuchiura, Ibaraki Prefecture Kidamari-cho, 3550 address Hitachi Cable Corporation system Materials in the Laboratory

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体チップの表面に半導体チップと略同一サイズのリードフレームを重ね合わせて接着剤を介して貼り付け、リードフレームのインナリードと半導体チップとをボンディングワイヤで接続し、アウタリードの表面と面一となるように半導体チップの表面側をモールド樹脂で封止して、封止樹脂表面にアウタリードの表面を露出させた半導体装置において、インナリードに接続されるボンディングワイヤがアウタリードの表面を越えないように、インナリードの表面側の厚みを減らしてインナリード表面をアウタリード表面より一段低くしたことを特徴とする半導体装置。 1. A on the surface of the semiconductor chip by superimposing the semiconductor chip and the lead frame of substantially the same size adhered via an adhesive, to connect the lead frame inner leads and the semiconductor chip by bonding wires, the surface of the outer leads When the surface side of the semiconductor chip so as to be flush sealed with mold resin, the semiconductor device to expose the surface of the outer leads to the sealing resin surface, a surface bonding wire of outer leads connected to the inner leads so as not to exceed, the semiconductor device characterized by the step lower than the outer lead surface inner lead surface by reducing the surface side of the thickness of the inner lead.
  2. 【請求項2】上記リードフレームのサイズを半導体チップよりやや大きめに形成し、該リードフレームを半導体チップの表面に重ね合わせたとき形成される端面間のギャップもモールド樹脂で封止するようにした請求項1に記載の半導体装置。 2. A slightly larger form than the semiconductor chip size of the lead frame, even the gap between the end surfaces formed when superposed the lead frame to the surface of the semiconductor chip so as to seal with a molding resin the semiconductor device according to claim 1.
  3. 【請求項3】上記半導体チップの表面にリードフレームを貼り付ける接着剤を、インナリード側のみならずアウタリード側にも介在させた請求項1または2に記載の半導体装置。 Wherein said semiconductor chip surface in an adhesive paste lead frame, a semiconductor device according to claim 1 or 2 interposed in the outer lead side not the inner lead side only.
JP24420495A 1995-09-22 1995-09-22 Semiconductor device Expired - Fee Related JP3163961B2 (en)

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