KR100753405B1 - A semiconductor device with package of lead on chip type - Google Patents

A semiconductor device with package of lead on chip type Download PDF

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KR100753405B1
KR100753405B1 KR1020020041557A KR20020041557A KR100753405B1 KR 100753405 B1 KR100753405 B1 KR 100753405B1 KR 1020020041557 A KR1020020041557 A KR 1020020041557A KR 20020041557 A KR20020041557 A KR 20020041557A KR 100753405 B1 KR100753405 B1 KR 100753405B1
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semiconductor chip
lead frame
lead
package
package body
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KR1020020041557A
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Korean (ko)
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KR20040006946A (en
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정관호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 LOC형 패키지를 갖는 반도체 장치에 관한 것으로서, 일면에 회로가 형성된 반도체 칩과, 상기 반도체 칩과 일단(one end)이 전기적으로 연결된 리드프레임과, 상기 반도체 칩의 회로 형성면에 상기 리드프레임의 일단을 접착시키는 접착 수단과, 상기 리드프레임의 타단(other end)이 외부로 노출되도록 하여 상기 반도체 칩과 리드프레임을 봉지하는 패키지 몸체부를 포함하는 LOC형 패키지를 갖는 반도체 장치에 있어서, 상기 리드프레임은, 상기 패키지 몸체부의 내부에 배치되는 내부 리드와 상기 패키지 몸체부의 외부에 배치되는 외부 리드로 구성되고, 상기 내부 리드가 상기 접착 수단 근처에서 상기 타단으로부터 상기 일단으로 가는 방향으로 하강부를 가짐과 아울러 상기 패키지 몸체부 내부의 둘레에서 상기 타단으로부터 상기 일단으로 가는 방향으로 상승부를 가지도록 구비된 것을 특징으로 한다. 이러한 구성에 의해 리드프레임은 반도체 칩 표면으로부터 충분한 거리를 가지게 되고, 결과적으로 충전재가 리드프레임과 반도체 칩 사이에 끼여지는 일이 발생하지 않으므로 충전재에 의해 버퍼 층과 회로 층이 손상되는 일은 발생하지 않게 된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a LOC type package, comprising: a semiconductor chip having a circuit formed on one surface thereof, a lead frame electrically connected to the semiconductor chip at one end thereof, and a lead formed on a circuit forming surface of the semiconductor chip. 1. A semiconductor device having an LOC type package including adhesive means for adhering one end of a frame and a package body part encapsulating the semiconductor chip and a lead frame by exposing the other end of the lead frame to the outside. The lead frame includes an inner lead disposed inside the package body portion and an outer lead disposed outside the package body portion, the inner lead having a lower portion in a direction from the other end to the one end near the bonding means. And from the other end to the one end around the inside of the package body portion. Is characterized in that it is provided to have a rise in the direction. With this configuration, the leadframe has a sufficient distance from the surface of the semiconductor chip, and as a result, the filler is not sandwiched between the leadframe and the semiconductor chip, so that the buffer layer and the circuit layer are not damaged by the filler. do.

패키지, 리드프레임, 상승, 하강, 반도체 칩, 손상Package, Leadframe, Rising, Falling, Semiconductor Chip, Damaged

Description

리드온칩형 패키지를 갖는 반도체 장치{A SEMICONDUCTOR DEVICE WITH PACKAGE OF LEAD ON CHIP TYPE}A SEMICONDUCTOR DEVICE WITH PACKAGE OF LEAD ON CHIP TYPE

도 1은 종래의 LOC형 패키지를 갖는 반도체 장치에서의 충전재에 의한 반도체 칩 표면의 손상을 설명하는 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining the damage of the semiconductor chip surface by the filler in the semiconductor device which has a conventional LOC type package.

도 2는 본 발명의 제1 실시예에 의한 반도체 장치의 구성도.2 is a configuration diagram of a semiconductor device according to the first embodiment of the present invention.

도 3은 본 발명의 제2 실시예에 의한 반도체 장치의 구성도.3 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention.

본 발명은 반도체 장치에 관한 것으로서, 특히 리드온칩형 패키지를 갖는 반도체 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a lead-on chip package.

최근 핸드폰, PDA(Personal Digital Assistants)와 같은 휴대용 전자제품의 수요가 급격히 증가하면서 이에 이용되는 반도체 칩의 패키지에 대한 박형화(薄型化), 소형화(小型化), 경량화(輕量化)의 요구가 더욱 커지고 있다. 이러한 요구에 따라 리드온칩(lead on chip: 이하, "LOC"라고 함)형 패키지가 크게 각광받고 있다.Recently, as the demand for portable electronic products such as mobile phones and PDAs (Personal Digital Assistants) increases rapidly, the demand for thinning, miniaturization, and lightening of semiconductor chip packages used therein is further increased. It's growing. In response to these demands, lead-on-chip (hereinafter referred to as "LOC") packages have gained much attention.

도 1은 종래의 LOC형 패키지를 갖는 반도체 장치에서의 충전재에 의한 반도 체 칩 표면의 손상을 설명하는 도면이다. 도 1에 도시되어 있는 바와 같이 반도체 장치(100)는 반도체 칩(102), 리드프레임(108), 본딩 와이어(110), 패키지 몸체부(112)로 이루어져 있다. 1 is a view for explaining the damage of the semiconductor chip surface by the filler in the semiconductor device having a conventional LOC type package. As shown in FIG. 1, the semiconductor device 100 includes a semiconductor chip 102, a lead frame 108, a bonding wire 110, and a package body 112.

반도체 칩(102)에서 상면(104)은 활동 영역이고, 하면(106)은 비활동 영역이다. 본딩 패드(114)는 활동 영역 상에 형성된다. 활동 영역(104)은 회로가 형성되는 회로 층(126)과, 이 회로 층(126)을 보호하기 위하여 폴리이미드(polyimide) 등으로 구성되는 버퍼 층(buffer layer)(128)을 구비하고 있다. 리드프레임(108)은 대략 100㎛의 두께를 갖는 접착 테이프(111)에 의해 반도체 칩(102)에 물리적으로 접착되며, 본딩 와이어(110)에 의해 본딩 패드(114)에 전기적으로 연결된다. LOC형 패키지에 사용되는 리드프레임의 형태는 일반적으로 2차원적으로 구성되며, 반도체 칩(102)의 높이 방향으로는 특별한 구성을 가지고 있지 않다. 즉 다운 세트이나 업 세트로 구성되어 있지 않다. 본딩 와이어(110)는 은(Au), 알루미늄(Al), 구리(Cu) 등의 도전성 금속선으로 이루어진다. 본딩 와이어(110)는 본딩 패드(114)에 볼 본딩(ball bonding)되고, 리드프레임(108)에 스티치 본딩(stitch bonding)된다. 패키지 몸체부(112)는 통상 에폭시 성형 수지(epoxy molding compound : 이하, "EMC"라고 함)로 이루어지며, 리드프레임의 일단만이 돌출하도록 반도체 칩(102), 리드프레임(108), 본딩와이어(110) 등을 밀봉한다. EMC는 패키지의 강도를 높이기 위하여 10㎛ 내지 150㎛ 크기의 실리카(SiO2)를 충전재(filler)로 포함하고 있다. In the semiconductor chip 102, the top surface 104 is an active region and the bottom surface 106 is an inactive region. Bond pads 114 are formed on the active area. The active region 104 includes a circuit layer 126 on which circuits are formed, and a buffer layer 128 made of polyimide or the like to protect the circuit layer 126. The lead frame 108 is physically bonded to the semiconductor chip 102 by an adhesive tape 111 having a thickness of approximately 100 μm, and is electrically connected to the bonding pad 114 by the bonding wire 110. The shape of the lead frame used in the LOC type package is generally two-dimensional, and has no special configuration in the height direction of the semiconductor chip 102. That is, it is not comprised of a down set or an up set. The bonding wire 110 is made of a conductive metal wire such as silver (Au), aluminum (Al), copper (Cu), or the like. The bonding wire 110 is ball bonded to the bonding pad 114 and stitch bonded to the lead frame 108. The package body 112 is usually made of an epoxy molding compound (hereinafter referred to as "EMC"), and the semiconductor chip 102, the lead frame 108, and the bonding wires so that only one end of the lead frame protrudes. 110, etc. are sealed. In order to increase the strength of the package, EMC includes silica (SiO 2 ) having a size of 10 μm to 150 μm as a filler.

이와 같은 LOC 형 반도체 칩 패키지는 패키지 대비 반도체 칩의 점유 면적을 크게 할 수 있어 패키지 크기의 축소에 효과적이다. 그러나 도 1의 확대된 부분(120)에 도시되어 있는 바와 같이, 충전재(124)가 리드프레임(108)과 반도체 칩(102) 사이에 끼이는 경우, 버퍼 층(128)에 균열(crack)이 발생하므로 반도체 칩(102) 상의 회로 층(126)이 손상될 수 있는 문제점을 가지고 있다. Such a LOC type semiconductor chip package can increase the occupied area of the semiconductor chip compared to the package, which is effective in reducing the package size. However, as shown in the enlarged portion 120 of FIG. 1, when the filler 124 is sandwiched between the leadframe 108 and the semiconductor chip 102, cracks are present in the buffer layer 128. As a result, the circuit layer 126 on the semiconductor chip 102 may be damaged.

본 발명은 이와 같은 문제점을 해결하기 위하여 제안된 것으로서, 에폭시 몰딩 화합물과 같은 봉지재로 리드프레임과 칩을 봉지하는 과정에서 리드프레임과 반도체 칩 사이에 봉지재가 유입됨에 따라 봉지재에 포함되어 있는 충전재에 의해 칩이 손상되는 것을 방지하는 것을 목적으로 한다. The present invention has been proposed to solve such a problem, and the filler included in the encapsulant as the encapsulant is introduced between the leadframe and the semiconductor chip in the process of encapsulating the leadframe and the chip with an encapsulant such as an epoxy molding compound. The purpose is to prevent the chip from being damaged.

이러한 목적과 관련하여 새로운 형태의 리드프레임을 갖는 LOC형 패키지의 반도체 장치가 제공된다. 본 발명은 일면에 회로가 형성된 반도체 칩; 상기 반도체 칩과 일단(one end)이 전기적으로 연결된 리드프레임; 상기 반도체 칩의 회로 형성면에 상기 리드프레임의 일단을 접착시키는 접착 수단; 및 상기 리드프레임의 타단(other end)이 외부로 노출되도록 하여 상기 반도체 칩과 리드프레임을 봉지하는 패키지 몸체부;를 포함하는 LOC형 패키지를 갖는 반도체 장치에 있어서, 상기 리드프레임은, 상기 패키지 몸체부의 내부에 배치되는 내부 리드와 상기 패키지 몸체부의 외부에 배치되는 외부 리드로 구성되고, 상기 내부 리드가 상기 접착 수단 근처에서 상기 타단으로부터 상기 일단으로 가는 방향으로 하강부를 가짐과 아울러 상기 패키지 몸체부 내부의 둘레에서 상기 타단으로부터 상기 일단으로 가는 방향으로 상승부를 가지도록 구비된 것을 특징으로 한다.
이러한 구성에 의해 리드프레임은 반도체 칩 표면으로부터 충분한 거리를 가지게 되고, 결과적으로 충전재가 리드프레임과 반도체 칩 사이에 끼여지는 일이 발생하지 않으므로 충전재에 의해 버퍼 층과 회로 층이 손상되는 일은 발생하지 않게 된다. 또한 상기 구성에 의해 와이어의 변형이 방지됨으로써 와이어의 손상을 방지할 수 있다. In connection with this purpose, a semiconductor device of a LOC type package having a new type of lead frame is provided. The present invention is a semiconductor chip having a circuit formed on one surface; A lead frame electrically connected to the semiconductor chip at one end; Bonding means for bonding one end of the lead frame to a circuit forming surface of the semiconductor chip; And a package body part encapsulating the semiconductor chip and the lead frame by exposing the other end of the lead frame to the outside, wherein the lead frame includes the package body. An inner lead disposed inside the portion and an outer lead disposed outside the package body portion, wherein the inner lead has a lower portion in a direction from the other end to the one end near the bonding means, and inside the package body portion. It is characterized in that it is provided to have a rising portion in the direction from the other end to the one end around.
With this configuration, the leadframe has a sufficient distance from the surface of the semiconductor chip, and as a result, the filler is not sandwiched between the leadframe and the semiconductor chip, so that the buffer layer and the circuit layer are not damaged by the filler. do. In addition, since the deformation of the wire is prevented by the above configuration, damage to the wire can be prevented.

삭제delete

(실시예)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. 설명의 일관성을 위하여 도면에서 동일한 참조부호는 동일 또는 유사한 구성요소 및 신호를 가리키는 것으로 사용한다. (Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

도 2는 본 발명의 제1 실시예에 의한 반도체 장치의 구성도이다. 도 2에 도시되어 있는 바와 같이 반도체 장치(200)는 반도체 칩(202), 접착 테이프(204), 리드 프레임(206), 본딩 와이어(208), 본딩 패드(210), 패키지 몸체부(212) 등을 구비하고 있다. 리드프레임(206) 중에서 패키지(212) 외부의 부분(218)을 외부 리드(outer lead)라고 하고, 패키지(212) 내부의 부분(220)을 내부 리드(inner lead)라고 한다. 외부 리드(218)에서 내부 리드(220)로 가는 방향을 기준으로 할 때, 리드프레임(206)은 반도체 칩(202)의 높이 방향으로 상승부(216)와 하강부(214)를 구비하고 있다. 이와 같이 리드프레임(206)이 상승부(216)와 하강부(214)를 구비하고 있는 점에서 도 1의 리드프레임(108)과 구별된다. 반도체 장치(200)의 다른 구성요소는 도 1의 구성요소와 동일하다. 2 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 2, the semiconductor device 200 includes a semiconductor chip 202, an adhesive tape 204, a lead frame 206, a bonding wire 208, a bonding pad 210, and a package body 212. Etc. are provided. The portion 218 of the lead frame 206 outside the package 212 is called an outer lead, and the portion 220 inside the package 212 is called an inner lead. Based on the direction from the outer lead 218 to the inner lead 220, the lead frame 206 includes a rising portion 216 and a falling portion 214 in the height direction of the semiconductor chip 202. . The lead frame 206 is distinguished from the lead frame 108 of FIG. 1 in that the lead frame 206 includes the rising portion 216 and the falling portion 214. Other components of the semiconductor device 200 are the same as those of FIG. 1.

먼저 하강부(214)는 패키지(212) 내부의 접착 필름(204) 근처에서 하강 높이(d1)가 0에서 1500㎛의 범위를 갖도록 형성된다. 리드프레임(206)이 하강부(214)를 갖도록 구성하면 그만큼 리드프레임(206)은 반도체 칩(202)의 표면으로부터 충분한 거리를 가지게 되고, 결과적으로 충전재가 리드프레임과 반도체 칩 사이에 끼여지는 일이 발생하지 않으므로 충전재에 의해 버퍼 층과 회로 층이 손상되는 일은 발생하지 않게 된다. 또한 본딩 와이어(208)의 변형이 방지됨으로써 와이어의 손상을 방지할 수 있다. First, the lower portion 214 is formed such that the lowered height d1 is in a range of 0 to 1500 μm near the adhesive film 204 inside the package 212. When the leadframe 206 is configured to have the lower portion 214, the leadframe 206 has a sufficient distance from the surface of the semiconductor chip 202, and as a result, the filler is sandwiched between the leadframe and the semiconductor chip. Since this does not occur, the buffer layer and the circuit layer are not damaged by the filler. In addition, since the deformation of the bonding wire 208 is prevented, damage to the wire can be prevented.

상승부(216)는 패키지(212) 내부의 둘레에서 상승 높이(d2)가 5에서 600㎛의 범위를 갖도록 형성된다. 이러한 상승부(216)에 의해 반도체 칩(202)과 리드프레임(206) 사이의 높이 불균형에 의해 발생되는 워페이지(warpage)를 방지할 수 있다. The raised portion 216 is formed such that the raised height d2 is in a range of 5 to 600 μm around the inside of the package 212. The raised portion 216 may prevent warpage caused by the height imbalance between the semiconductor chip 202 and the lead frame 206.

도 3은 본 발명의 제2 실시예에 의한 반도체 장치의 구성도이다. 도 2에 도시된 반도체 장치(200)의 리드프레임(206)은 하강부(214)와 상승부(216)를 모두 구비하고 있으나, 도 3에 도시된 반도체 장치(300)의 리드프레임(306)은 하강부(314)만을 구비하고 있다. 즉, 반도체 장치(300)의 리드프레임(306)은 도 2에 도시된 반도체 장치(200)의 리드프레임(206)과는 달리 상승부를 구비하고 있지 않다. 따라서 외부 리드(318)가 그만큼 길어진다. 3 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention. Although the lead frame 206 of the semiconductor device 200 illustrated in FIG. 2 includes both a lower portion 214 and a raised portion 216, the lead frame 306 of the semiconductor device 300 illustrated in FIG. 3 is provided. Has only the lowering portion 314. That is, the lead frame 306 of the semiconductor device 300 does not have a rising part unlike the lead frame 206 of the semiconductor device 200 shown in FIG. 2. Therefore, the outer lead 318 becomes that long.

여기서 설명된 실시예들은 본 발명을 당업자가 용이하게 이해하고 실시할 수 있도록 하기 위한 것일 뿐이며, 본 발명의 범위를 한정하려는 것은 아니다. 따라서 당업자들은 본 발명의 범위 안에서 다양한 변형이나 변경이 가능함을 주목하여야 한다. 본 발명의 범위는 원칙적으로 후술하는 특허청구범위에 의하여 정하여진다.The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

본 발명에서와 같이 리드프레임이 하강부를 갖도록 구성하면 그만큼 리드프레임은 반도체 칩의 표면으로부터 충분한 거리를 가지게 되고, 결과적으로 충전재가 리드프레임과 반도체 칩 사이에 끼여지는 일이 발생하지 않으므로 충전재에 의해 버퍼 층과 회로 층이 손상되는 일은 발생하지 않게 된다. 또한 본딩 와이어의 변형이 방지됨으로써 와이어의 손상을 방지할 수 있다. 또한 리드프레임이 상승부를 갖도록 구성하면 반도체 칩과 리드프레임 사이의 높이 불균형에 의해 발생되는 워페이지(warpage)를 방지할 수 있다. When the lead frame is configured to have a lower portion as in the present invention, the lead frame has a sufficient distance from the surface of the semiconductor chip, and as a result, the filler is not sandwiched between the lead frame and the semiconductor chip, so that the buffer is filled by the filler. Damage to layers and circuit layers will not occur. In addition, since the deformation of the bonding wire is prevented, damage to the wire can be prevented. In addition, if the lead frame has a rising portion, warpage caused by the height imbalance between the semiconductor chip and the lead frame can be prevented.

Claims (2)

일면에 회로가 형성된 반도체 칩; 상기 반도체 칩과 일단(one end)이 전기적으로 연결된 리드프레임; 상기 반도체 칩의 회로 형성면에 상기 리드프레임의 일단을 접착시키는 접착 수단; 및 상기 리드프레임의 타단(other end)이 외부로 노출되도록 하여 상기 반도체 칩과 리드프레임을 봉지하는 패키지 몸체부;를 포함하는 LOC형 패키지를 갖는 반도체 장치에 있어서, A semiconductor chip having a circuit formed on one surface thereof; A lead frame electrically connected to the semiconductor chip at one end; Bonding means for bonding one end of the lead frame to a circuit forming surface of the semiconductor chip; And a package body part encapsulating the semiconductor chip and the lead frame so that the other end of the lead frame is exposed to the outside. 상기 리드프레임은, 상기 패키지 몸체부의 내부에 배치되는 내부 리드와 상기 패키지 몸체부의 외부에 배치되는 외부 리드로 구성되고, 상기 내부 리드가 상기 접착 수단 근처에서 상기 타단으로부터 상기 일단으로 가는 방향으로 하강부를 가짐과 아울러 상기 패키지 몸체부 내부의 둘레에서 상기 타단으로부터 상기 일단으로 가는 방향으로 상승부를 가지도록 구비된 것을 특징으로 하는 LOC형 패키지를 갖는 반도체 장치. The lead frame may include an inner lead disposed inside the package body portion and an outer lead disposed outside the package body portion, and the lower portion may be lowered in a direction from the other end to the one end near the adhesive means. And a rising portion in the direction from the other end to the one end in the circumference of the inside of the package body. 삭제delete
KR1020020041557A 2002-07-16 2002-07-16 A semiconductor device with package of lead on chip type KR100753405B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0138940Y1 (en) * 1995-12-08 1999-05-01 유기범 Handset gradle for facsimile
KR20010038940A (en) * 1999-10-28 2001-05-15 박종섭 Stacked buttom leaded plastic package and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0138940Y1 (en) * 1995-12-08 1999-05-01 유기범 Handset gradle for facsimile
KR20010038940A (en) * 1999-10-28 2001-05-15 박종섭 Stacked buttom leaded plastic package and manufacturing method thereof

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