JPH098132A - Semiconductor element and its manufacturing method - Google Patents

Abstract

PURPOSE: To increase the radius of curvature of a junction surface and to effectively suppress current concentration at a PN junction periphery edge part by spreading the a diffusion region larger than a depth for a reference edge prescribed by an inner periphery edge at the surface side of the substrate of an opening. CONSTITUTION: A diffusion region 2 of a semiconductor element is spread to a substrate surface larger than a depth Yj for a reference edge 4c prescribed by an inner edge part at the side of a substrate 1 at a second opening part with a larger radius of curvature than the periphery edge part. That is, the diffusion region is formed so that Xj>=Yj can be established with the spread of the diffusion region in side direction from the reference edge 4c as Xj. The diffusion region 2 is formed so that it spread to the substrate surface larger than the depth for the reference edge 4c prescribed by a peripheral edge at the side of the substrate 1 of a second opening part 4b. Further, the radius of curvature of the peripheral edge part of the junction surface for demarcating the diffusion region 2 is formed to have a larger value than the depth of the diffusion region 2, thus suppressing the current concentration at a part for forming the curved surface of the PN junction surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which the spread of the bonding surface at the peripheral portion of the diffusion region to the surface of the substrate is increased, and the withstand voltage due to current concentration is improved, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor element having a PN junction surface formed by introducing impurities into a semiconductor substrate is used as an essential element for various semiconductor elements such as bipolar and MOS individual devices and integrated circuits. The introduction of impurities into the substrate is carried out by appropriately combining thermal diffusion, ion implantation, etc. according to the depth and profile shape of the PN junction surface to be formed.

Generally, when the diffusion region is formed by introducing impurities into the substrate by thermal diffusion, the impurities are diffused in the vertical direction, that is, in the inward direction of the substrate orthogonal to the surface of the substrate, and at the same time, on the surface of the substrate. It is also diffused in the horizontal direction,
As a result, a diffusion region defined by the PN junction surface composed of the curved peripheral portion is formed. More specifically, for example, as shown in FIG. 3, a thermal oxide film 12 of SiO ₂ is formed on the surface of the semiconductor substrate on which the N type epitaxial layer 11 is formed.
When an opening 13 for introducing impurities is formed in the thermal oxide film and boron as an impurity is introduced into the substrate 11 through the opening 13, the impurities are not limited to the vertical direction (x) of the substrate. At the same time, the PN junction surface 14 which is diffused in the lateral direction (y) is formed so as to terminate in a state where it enters the lower surface of the thermal oxide film 12 at the peripheral edge thereof, and the diffusion region 15 is formed in the substrate 11. Defined.

[0004]

When impurities are introduced into the semiconductor substrate 11 by thermal diffusion, the lateral (y) of the impurities is introduced.
Although it is difficult to accurately grasp the diffusion distance yj in the direction, it is generally considered to be about 80% of the diffusion distance xj in the vertical (x) direction, that is, yj = 0.8xj. ing.

Therefore, the PN junction surface formed by the diffusion of impurities has a small radius of curvature at its peripheral portion when it is formed relatively shallow, but the radius of curvature increases as it is formed deeper. . However, when the radius of curvature of the peripheral portion of the PN junction surface is formed to be small in a relatively shallow diffusion region, current concentration is likely to occur at the peripheral portion of the junction surface when the element is used, and the withstand voltage is lowered. Also, problems such as easy breakdown of the device occur in the overload test.

On the other hand, a method of forming a relatively shallow diffusion layer on the substrate surface by an ion implantation method instead of or together with the thermal diffusion is also widely used, but this method also results in the peripheral portion of the PN junction surface. The radius of curvature of cannot be increased beyond a certain level. Therefore, it is an object of the present invention to obtain a semiconductor element and a method for manufacturing the same in which the radius of curvature of the bonding surface at the peripheral portion of the diffusion region is increased to improve the withstand voltage due to current concentration.

[0007]

According to the present invention, a semiconductor substrate, a diffusion region having a conductivity type opposite to that of the semiconductor substrate, an oxide film formed on the surface of the substrate, and an oxide film are formed. Electrode wiring connected to the diffusion area through the formed opening, and the diffusion area extends to the substrate surface by a depth larger than the reference edge defined by the inner peripheral edge of the opening on the substrate surface side. A semiconductor device is provided.

The opening can be composed of a first opening portion formed on the surface side of the oxide film and a second opening portion formed on the substrate side in an opening cross section smaller than the first opening portion. According to the present invention, further, a polysilicon layer is patterned on the surface of the semiconductor substrate, an oxide film is grown to cover and embed at least the outer periphery of the polysilicon layer, and the central portion of the upper surface of the polysilicon layer is exposed. The first opening portion is formed in the oxide film so that the impurity is diffused into the polysilicon layer through the first opening portion and is diffused to the surface of the substrate to form a diffusion region, and then the polysilicon layer is formed. To form an integrated oxide film, and then form a second opening in the integrated oxide film portion to expose the diffusion region. Will be provided.

[0009]

Since the impurities to the substrate are diffused through the polysilicon layer formed to have a diameter larger than that of the first opening portion, the radius of curvature is large at the peripheral edge portion although the substrate surface is relatively shallow. A diffusion layer spreading laterally is formed. In this case, since polysilicon has a diffusion rate with respect to impurities larger than that of silicon crystals, for example, boron (B), the lateral diffusion width can be increased on the substrate surface by interposing the polysilicon layer. .

The diffusion region formed spreads over the substrate surface by a depth larger than the reference edge defined by the peripheral edge of the second opening formed on the substrate side on the substrate side, and has a larger radius of curvature on the peripheral edge portion. Granted. Therefore, when the device is used, the PN that often occurs in the conventional device.
It is possible to effectively suppress the current concentration at the peripheral edge of the junction, thereby improving the withstand voltage of the element.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIG.
2 will be described in detail according to an embodiment.
The semiconductor device according to the present invention has a cross section as shown in FIG.
An N ⁺ type semiconductor substrate 1 having an N ⁻ type epitaxial layer formed on the surface thereof, a diffusion region 2 having a conductivity type opposite to that of the diffusion region 2 formed on the surface of the substrate 1, and an oxidation formed on the surface of the substrate 1. The film 3 is connected to the diffusion region 2 through the opening 4, which is composed of the film 3, the first opening 4a formed on the surface side of the oxide film 3 and the second opening 4b formed on the substrate side. And an electrode portion 5 made of a conductive metal. In the embodiment shown in FIG. 1, the remaining polysilicon layer 6a made of unoxidized polysilicon is buried in the oxide film 3 surrounding the second opening 4b.

Here, the diffusion region 2 of the semiconductor device of the present invention.
Has a larger radius of curvature at its peripheral edge portion and spreads over the substrate surface by a depth greater than the depth Yj with respect to the reference edge 4c defined by the inner peripheral edge of the second opening portion on the substrate 1 side. That is, the diffusion region is formed in such a size that the relation of Xj ≧ Yj is established, where Xj is the spread of the diffusion region in the lateral direction from the reference edge 4c.

The semiconductor device of the present invention, as described above,
The diffusion region 2 is formed so as to extend over the substrate surface by a depth greater than the reference edge 4c defined by the peripheral edge of the second opening portion 4b on the substrate 1 side. The radius of curvature is formed to have a larger value with respect to the depth of the diffusion region 2. For this reason, it is possible to effectively suppress the occurrence of current concentration in the portion forming the curved surface of the peripheral portion of the PN junction surface, and thus it is possible to obtain higher withstand voltage.

Next, a method of manufacturing the element of the present invention will be described. First, a semiconductor substrate 1 is prepared by growing and forming an epitaxial layer of N ⁻ conductivity type on the surface of a starting substrate made of, for example, N ⁺ conductivity type silicon. After the substrate 1 is prepared, a thermal oxide film 3a is formed on the surface of the substrate 1 to have a uniform layer thickness of about 800 Å, and an opening having a size of about 8 μm is formed by photolithography on the substrate. A polysilicon film is formed on the surface of No. 1 and the surface of the oxide film 3a by vapor deposition so as to have a film thickness of about 2000 angstroms at the opening, and the formed polysilicon film is etched by a photo-etching method. 2 (a)
As shown in FIG. 3, a polysilicon layer 6 having a large diameter portion of about φ12 μm aligned with the opening is patterned.
The layer thickness of the polysilicon layer 6 can be appropriately set in the range of about 500 to 5000 angstroms according to the design of the element to be formed and the like.

Next, after the oxide film 3a on the surface of the substrate 1 is thermally grown to fill the outer periphery of the polysilicon layer 6, the oxide film 3 is etched so that the central portion of the upper surface of the polysilicon layer 6 is exposed. As a result, the first opening portion 4a having a size of about φ6 μm is formed. As described above, the first opening 4 is formed in the oxide film 3.
After forming a, boron (B) as an impurity is added to about 11
When thermally diffusing into the polysilicon layer 6 through the first opening portion under the diffusion condition of 50 ° C. and about 360 minutes, the impurities introduced into the polysilicon layer 6 are further diffused toward the surface of the substrate 1, As shown in FIG. 2B, a diffusion region 2 due to impurities from the polysilicon layer 6 is formed on the surface of the substrate 1.

At this time, the impurities into the substrate 1 are diffused through the polysilicon layer 6 formed to have a diameter larger than that of the first opening portion 4a, so that the peripheral edge portion spreads laterally on the surface of the substrate 1. The shallow diffusion layer 2 is formed with a large radius of curvature.
The impurity may be introduced into the polysilicon layer 6 by using an ion implantation method instead of the thermal diffusion as described above.

Then, the polysilicon layer 6 is oxidized from the side of the first opening portion 4a to thereby form the polysilicon layer 6
As shown in FIG. 2 (c), the oxidation progresses from the central portion of the upper surface, and is integrated with the oxide film 3 already formed leaving the peripheral edge portion 6a. After the progress of this oxidation reaches the surface of the diffusion region 2 of the substrate 1, the oxidation is completed. Then
By etching, the portion integrated with the oxide film 3 is etched to form a second opening portion 4b having an opening cross section smaller than the first opening portion to expose the surface of the diffusion layer 2 to the first opening portion 4 side. Then, as shown in FIG. 2D, the first and second
A conductive metal such as Al is formed by vapor deposition on the surface of the substrate 1 defined by the openings 4 including the opening portions 4a and 4b, that is, the surface of the diffusion region 2, and the electrode wiring 5 is formed together with other necessary wirings. By doing so, the semiconductor device of the present invention can be obtained.

Although the remaining polysilicon layer is left in the oxide film during the oxidation of the polysilicon layer in the above-mentioned embodiments, it goes without saying that it is not always necessary to leave it. Further, in the above-described embodiment, the polysilicon layer is formed in the shape of a flange with the upper peripheral portion protruding, but the present invention is not limited to this, and the element may be manufactured by forming it in the shape of a cylinder.

[0019]

When the device is used, it is possible to effectively suppress the current concentration at the peripheral edge of the PN junction, which often occurs in the conventional device, so that the withstand voltage of the device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device of the present invention.

FIG. 2 is a diagram showing steps of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a profile of a general bonding surface formed by introducing impurities into a substrate.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Diffusion Region 3 Oxide Film 4a First Opening Portion 4b Second Opening Portion 4c Reference Edge 5 Electrode Wiring 6 Polysilicon Layer 6a Remaining Polysilicon Layer

Claims (3)

[Claims] 1. A semiconductor substrate, a diffusion region having a conductivity type opposite to that of the semiconductor substrate, an oxide film formed on a surface of the substrate, and an opening formed in the oxide film. An electrode wiring connected to the diffusion region, wherein the diffusion region extends to the substrate surface by a depth larger than a reference edge defined by the inner peripheral edge of the opening on the substrate surface side. Semiconductor device. 2. The opening comprises a first opening portion formed on the surface side of the oxide film, and a second opening portion formed on the substrate side in an opening cross section smaller than the first opening portion. The semiconductor device according to 1. 3. A polysilicon layer is patterned on the surface of a semiconductor substrate, an oxide film is grown to cover and fill at least the outer periphery of the polysilicon layer, and the central portion of the upper surface of the polysilicon layer is exposed. Forming the first opening portion in the oxide film as described above, diffusing impurities into the polysilicon layer through the first opening portion, and diffusing into the surface of the substrate to form a diffusion region. A semiconductor characterized in that a silicon layer is oxidized to be integrated with the oxide film, and then a second opening is formed in the integrated oxide film to expose the diffusion region. Device manufacturing method.